1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#ifndef PCI_HOST_SPAPR_H
21#define PCI_HOST_SPAPR_H
22
23#include "hw/ppc/spapr.h"
24#include "hw/pci/pci.h"
25#include "hw/pci/pci_host.h"
26#include "hw/ppc/xics.h"
27
28#define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge"
29
30#define SPAPR_PCI_HOST_BRIDGE(obj) \
31 OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
32
33#define SPAPR_PCI_DMA_MAX_WINDOWS 2
34
35typedef struct sPAPRPHBState sPAPRPHBState;
36
37typedef struct spapr_pci_msi {
38 uint32_t first_irq;
39 uint32_t num;
40} spapr_pci_msi;
41
42typedef struct spapr_pci_msi_mig {
43 uint32_t key;
44 spapr_pci_msi value;
45} spapr_pci_msi_mig;
46
47struct sPAPRPHBState {
48 PCIHostState parent_obj;
49
50 uint32_t index;
51 uint64_t buid;
52 char *dtbusname;
53 bool dr_enabled;
54
55 MemoryRegion memspace, iospace;
56 hwaddr mem_win_addr, mem_win_size, mem64_win_addr, mem64_win_size;
57 uint64_t mem64_win_pciaddr;
58 hwaddr io_win_addr, io_win_size;
59 MemoryRegion mem32window, mem64window, iowindow, msiwindow;
60
61 uint32_t dma_liobn[SPAPR_PCI_DMA_MAX_WINDOWS];
62 hwaddr dma_win_addr, dma_win_size;
63 AddressSpace iommu_as;
64 MemoryRegion iommu_root;
65
66 struct spapr_pci_lsi {
67 uint32_t irq;
68 } lsi_table[PCI_NUM_PINS];
69
70 GHashTable *msi;
71
72 int32_t msi_devs_num;
73 spapr_pci_msi_mig *msi_devs;
74
75 QLIST_ENTRY(sPAPRPHBState) list;
76
77 bool ddw_enabled;
78 uint64_t page_size_mask;
79 uint64_t dma64_win_addr;
80
81 uint32_t numa_node;
82
83 bool pcie_ecs;
84
85
86 bool pre_2_8_migration;
87 uint32_t mig_liobn;
88 hwaddr mig_mem_win_addr, mig_mem_win_size;
89 hwaddr mig_io_win_addr, mig_io_win_size;
90};
91
92#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
93#define SPAPR_PCI_MEM32_WIN_SIZE \
94 ((1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET)
95#define SPAPR_PCI_MEM64_WIN_SIZE 0x10000000000ULL
96
97
98
99#define SPAPR_PCI_BASE (1ULL << 45)
100#define SPAPR_PCI_LIMIT (1ULL << 46)
101
102#define SPAPR_PCI_2_7_MMIO_WIN_SIZE 0xf80000000
103#define SPAPR_PCI_IO_WIN_SIZE 0x10000
104
105#define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL
106
107static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
108{
109 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
110
111 return spapr_qirq(spapr, phb->lsi_table[pin].irq);
112}
113
114PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index);
115
116int spapr_populate_pci_dt(sPAPRPHBState *phb, uint32_t xics_phandle, void *fdt,
117 uint32_t nr_msis);
118
119void spapr_pci_rtas_init(void);
120
121sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid);
122PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid,
123 uint32_t config_addr);
124
125
126void spapr_phb_remove_pci_device_cb(DeviceState *dev);
127
128
129#ifdef CONFIG_LINUX
130bool spapr_phb_eeh_available(sPAPRPHBState *sphb);
131int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
132 unsigned int addr, int option);
133int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb, int *state);
134int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option);
135int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb);
136void spapr_phb_vfio_reset(DeviceState *qdev);
137#else
138static inline bool spapr_phb_eeh_available(sPAPRPHBState *sphb)
139{
140 return false;
141}
142static inline int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
143 unsigned int addr, int option)
144{
145 return RTAS_OUT_HW_ERROR;
146}
147static inline int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb,
148 int *state)
149{
150 return RTAS_OUT_HW_ERROR;
151}
152static inline int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option)
153{
154 return RTAS_OUT_HW_ERROR;
155}
156static inline int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb)
157{
158 return RTAS_OUT_HW_ERROR;
159}
160static inline void spapr_phb_vfio_reset(DeviceState *qdev)
161{
162}
163#endif
164
165void spapr_phb_dma_reset(sPAPRPHBState *sphb);
166
167#endif
168