LXR qemu/target/arm/cpu64.c

   1/*
   2 * QEMU AArch64 CPU
   3 *
   4 * Copyright (c) 2013 Linaro Ltd
   5 *
   6 * This program is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU General Public License
   8 * as published by the Free Software Foundation; either version 2
   9 * of the License, or (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, see
  18 * <http://www.gnu.org/licenses/gpl-2.0.html>
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "qapi/error.h"
  23#include "cpu.h"
  24#include "qemu-common.h"
  25#if !defined(CONFIG_USER_ONLY)
  26#include "hw/loader.h"
  27#endif
  28#include "hw/arm/arm.h"
  29#include "sysemu/sysemu.h"
  30#include "sysemu/kvm.h"
  31#include "kvm_arm.h"
  32#include "qapi/visitor.h"
  33
  34static inline void set_feature(CPUARMState *env, int feature)
  35{
  36    env->features |= 1ULL << feature;
  37}
  38
  39static inline void unset_feature(CPUARMState *env, int feature)
  40{
  41    env->features &= ~(1ULL << feature);
  42}
  43
  44#ifndef CONFIG_USER_ONLY
  45static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
  46{
  47    ARMCPU *cpu = arm_env_get_cpu(env);
  48
  49    /* Number of cores is in [25:24]; otherwise we RAZ */
  50    return (cpu->core_count - 1) << 24;
  51}
  52#endif
  53
  54static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
  55#ifndef CONFIG_USER_ONLY
  56    { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
  57      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
  58      .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
  59      .writefn = arm_cp_write_ignore },
  60    { .name = "L2CTLR",
  61      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
  62      .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
  63      .writefn = arm_cp_write_ignore },
  64#endif
  65    { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
  66      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
  67      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  68    { .name = "L2ECTLR",
  69      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
  70      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  71    { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
  72      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
  73      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  74    { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
  75      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
  76      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  77    { .name = "CPUACTLR",
  78      .cp = 15, .opc1 = 0, .crm = 15,
  79      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  80    { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
  81      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
  82      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  83    { .name = "CPUECTLR",
  84      .cp = 15, .opc1 = 1, .crm = 15,
  85      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  86    { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
  87      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
  88      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  89    { .name = "CPUMERRSR",
  90      .cp = 15, .opc1 = 2, .crm = 15,
  91      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  92    { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
  93      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
  94      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
  95    { .name = "L2MERRSR",
  96      .cp = 15, .opc1 = 3, .crm = 15,
  97      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
  98    REGINFO_SENTINEL
  99};
 100
 101static void aarch64_a57_initfn(Object *obj)
 102{
 103    ARMCPU *cpu = ARM_CPU(obj);
 104
 105    cpu->dtb_compatible = "arm,cortex-a57";
 106    set_feature(&cpu->env, ARM_FEATURE_V8);
 107    set_feature(&cpu->env, ARM_FEATURE_VFP4);
 108    set_feature(&cpu->env, ARM_FEATURE_NEON);
 109    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 110    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 111    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 112    set_feature(&cpu->env, ARM_FEATURE_EL2);
 113    set_feature(&cpu->env, ARM_FEATURE_EL3);
 114    set_feature(&cpu->env, ARM_FEATURE_PMU);
 115    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
 116    cpu->midr = 0x411fd070;
 117    cpu->revidr = 0x00000000;
 118    cpu->reset_fpsid = 0x41034070;
 119    cpu->isar.mvfr0 = 0x10110222;
 120    cpu->isar.mvfr1 = 0x12111111;
 121    cpu->isar.mvfr2 = 0x00000043;
 122    cpu->ctr = 0x8444c004;
 123    cpu->reset_sctlr = 0x00c50838;
 124    cpu->id_pfr0 = 0x00000131;
 125    cpu->id_pfr1 = 0x00011011;
 126    cpu->id_dfr0 = 0x03010066;
 127    cpu->id_afr0 = 0x00000000;
 128    cpu->id_mmfr0 = 0x10101105;
 129    cpu->id_mmfr1 = 0x40000000;
 130    cpu->id_mmfr2 = 0x01260000;
 131    cpu->id_mmfr3 = 0x02102211;
 132    cpu->isar.id_isar0 = 0x02101110;
 133    cpu->isar.id_isar1 = 0x13112111;
 134    cpu->isar.id_isar2 = 0x21232042;
 135    cpu->isar.id_isar3 = 0x01112131;
 136    cpu->isar.id_isar4 = 0x00011142;
 137    cpu->isar.id_isar5 = 0x00011121;
 138    cpu->isar.id_isar6 = 0;
 139    cpu->isar.id_aa64pfr0 = 0x00002222;
 140    cpu->id_aa64dfr0 = 0x10305106;
 141    cpu->pmceid0 = 0x00000000;
 142    cpu->pmceid1 = 0x00000000;
 143    cpu->isar.id_aa64isar0 = 0x00011120;
 144    cpu->id_aa64mmfr0 = 0x00001124;
 145    cpu->dbgdidr = 0x3516d000;
 146    cpu->clidr = 0x0a200023;
 147    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
 148    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
 149    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
 150    cpu->dcz_blocksize = 4; /* 64 bytes */
 151    cpu->gic_num_lrs = 4;
 152    cpu->gic_vpribits = 5;
 153    cpu->gic_vprebits = 5;
 154    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 155}
 156
 157static void aarch64_a53_initfn(Object *obj)
 158{
 159    ARMCPU *cpu = ARM_CPU(obj);
 160
 161    cpu->dtb_compatible = "arm,cortex-a53";
 162    set_feature(&cpu->env, ARM_FEATURE_V8);
 163    set_feature(&cpu->env, ARM_FEATURE_VFP4);
 164    set_feature(&cpu->env, ARM_FEATURE_NEON);
 165    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 166    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 167    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 168    set_feature(&cpu->env, ARM_FEATURE_EL2);
 169    set_feature(&cpu->env, ARM_FEATURE_EL3);
 170    set_feature(&cpu->env, ARM_FEATURE_PMU);
 171    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
 172    cpu->midr = 0x410fd034;
 173    cpu->revidr = 0x00000000;
 174    cpu->reset_fpsid = 0x41034070;
 175    cpu->isar.mvfr0 = 0x10110222;
 176    cpu->isar.mvfr1 = 0x12111111;
 177    cpu->isar.mvfr2 = 0x00000043;
 178    cpu->ctr = 0x84448004; /* L1Ip = VIPT */
 179    cpu->reset_sctlr = 0x00c50838;
 180    cpu->id_pfr0 = 0x00000131;
 181    cpu->id_pfr1 = 0x00011011;
 182    cpu->id_dfr0 = 0x03010066;
 183    cpu->id_afr0 = 0x00000000;
 184    cpu->id_mmfr0 = 0x10101105;
 185    cpu->id_mmfr1 = 0x40000000;
 186    cpu->id_mmfr2 = 0x01260000;
 187    cpu->id_mmfr3 = 0x02102211;
 188    cpu->isar.id_isar0 = 0x02101110;
 189    cpu->isar.id_isar1 = 0x13112111;
 190    cpu->isar.id_isar2 = 0x21232042;
 191    cpu->isar.id_isar3 = 0x01112131;
 192    cpu->isar.id_isar4 = 0x00011142;
 193    cpu->isar.id_isar5 = 0x00011121;
 194    cpu->isar.id_isar6 = 0;
 195    cpu->isar.id_aa64pfr0 = 0x00002222;
 196    cpu->id_aa64dfr0 = 0x10305106;
 197    cpu->isar.id_aa64isar0 = 0x00011120;
 198    cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
 199    cpu->dbgdidr = 0x3516d000;
 200    cpu->clidr = 0x0a200023;
 201    cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
 202    cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
 203    cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
 204    cpu->dcz_blocksize = 4; /* 64 bytes */
 205    cpu->gic_num_lrs = 4;
 206    cpu->gic_vpribits = 5;
 207    cpu->gic_vprebits = 5;
 208    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 209}
 210
 211static void aarch64_a72_initfn(Object *obj)
 212{
 213    ARMCPU *cpu = ARM_CPU(obj);
 214
 215    cpu->dtb_compatible = "arm,cortex-a72";
 216    set_feature(&cpu->env, ARM_FEATURE_V8);
 217    set_feature(&cpu->env, ARM_FEATURE_VFP4);
 218    set_feature(&cpu->env, ARM_FEATURE_NEON);
 219    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 220    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 221    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 222    set_feature(&cpu->env, ARM_FEATURE_EL2);
 223    set_feature(&cpu->env, ARM_FEATURE_EL3);
 224    set_feature(&cpu->env, ARM_FEATURE_PMU);
 225    cpu->midr = 0x410fd083;
 226    cpu->revidr = 0x00000000;
 227    cpu->reset_fpsid = 0x41034080;
 228    cpu->isar.mvfr0 = 0x10110222;
 229    cpu->isar.mvfr1 = 0x12111111;
 230    cpu->isar.mvfr2 = 0x00000043;
 231    cpu->ctr = 0x8444c004;
 232    cpu->reset_sctlr = 0x00c50838;
 233    cpu->id_pfr0 = 0x00000131;
 234    cpu->id_pfr1 = 0x00011011;
 235    cpu->id_dfr0 = 0x03010066;
 236    cpu->id_afr0 = 0x00000000;
 237    cpu->id_mmfr0 = 0x10201105;
 238    cpu->id_mmfr1 = 0x40000000;
 239    cpu->id_mmfr2 = 0x01260000;
 240    cpu->id_mmfr3 = 0x02102211;
 241    cpu->isar.id_isar0 = 0x02101110;
 242    cpu->isar.id_isar1 = 0x13112111;
 243    cpu->isar.id_isar2 = 0x21232042;
 244    cpu->isar.id_isar3 = 0x01112131;
 245    cpu->isar.id_isar4 = 0x00011142;
 246    cpu->isar.id_isar5 = 0x00011121;
 247    cpu->isar.id_aa64pfr0 = 0x00002222;
 248    cpu->id_aa64dfr0 = 0x10305106;
 249    cpu->pmceid0 = 0x00000000;
 250    cpu->pmceid1 = 0x00000000;
 251    cpu->isar.id_aa64isar0 = 0x00011120;
 252    cpu->id_aa64mmfr0 = 0x00001124;
 253    cpu->dbgdidr = 0x3516d000;
 254    cpu->clidr = 0x0a200023;
 255    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
 256    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
 257    cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
 258    cpu->dcz_blocksize = 4; /* 64 bytes */
 259    cpu->gic_num_lrs = 4;
 260    cpu->gic_vpribits = 5;
 261    cpu->gic_vprebits = 5;
 262    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 263}
 264
 265static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name,
 266                               void *opaque, Error **errp)
 267{
 268    ARMCPU *cpu = ARM_CPU(obj);
 269    visit_type_uint32(v, name, &cpu->sve_max_vq, errp);
 270}
 271
 272static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,
 273                               void *opaque, Error **errp)
 274{
 275    ARMCPU *cpu = ARM_CPU(obj);
 276    Error *err = NULL;
 277
 278    visit_type_uint32(v, name, &cpu->sve_max_vq, &err);
 279
 280    if (!err && (cpu->sve_max_vq == 0 || cpu->sve_max_vq > ARM_MAX_VQ)) {
 281        error_setg(&err, "unsupported SVE vector length");
 282        error_append_hint(&err, "Valid sve-max-vq in range [1-%d]\n",
 283                          ARM_MAX_VQ);
 284    }
 285    error_propagate(errp, err);
 286}
 287
 288/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
 289 * otherwise, a CPU with as many features enabled as our emulation supports.
 290 * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
 291 * this only needs to handle 64 bits.
 292 */
 293static void aarch64_max_initfn(Object *obj)
 294{
 295    ARMCPU *cpu = ARM_CPU(obj);
 296
 297    if (kvm_enabled()) {
 298        kvm_arm_set_cpu_features_from_host(cpu);
 299    } else {
 300        uint64_t t;
 301        uint32_t u;
 302        aarch64_a57_initfn(obj);
 303
 304        t = cpu->isar.id_aa64isar0;
 305        t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
 306        t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
 307        t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
 308        t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
 309        t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
 310        t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
 311        t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
 312        t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
 313        t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
 314        t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
 315        cpu->isar.id_aa64isar0 = t;
 316
 317        t = cpu->isar.id_aa64isar1;
 318        t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
 319        cpu->isar.id_aa64isar1 = t;
 320
 321        t = cpu->isar.id_aa64pfr0;
 322        t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
 323        t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
 324        t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
 325        cpu->isar.id_aa64pfr0 = t;
 326
 327        /* Replicate the same data to the 32-bit id registers.  */
 328        u = cpu->isar.id_isar5;
 329        u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
 330        u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
 331        u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
 332        u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
 333        u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
 334        u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
 335        cpu->isar.id_isar5 = u;
 336
 337        u = cpu->isar.id_isar6;
 338        u = FIELD_DP32(u, ID_ISAR6, DP, 1);
 339        cpu->isar.id_isar6 = u;
 340
 341        /*
 342         * FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet,
 343         * so do not set MVFR1.FPHP.  Strictly speaking this is not legal,
 344         * but it is also not legal to enable SVE without support for FP16,
 345         * and enabling SVE in system mode is more useful in the short term.
 346         */
 347
 348#ifdef CONFIG_USER_ONLY
 349        /* For usermode -cpu max we can use a larger and more efficient DCZ
 350         * blocksize since we don't have to follow what the hardware does.
 351         */
 352        cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
 353        cpu->dcz_blocksize = 7; /*  512 bytes */
 354#endif
 355
 356        cpu->sve_max_vq = ARM_MAX_VQ;
 357        object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq,
 358                            cpu_max_set_sve_vq, NULL, NULL, &error_fatal);
 359    }
 360}
 361
 362typedef struct ARMCPUInfo {
 363    const char *name;
 364    void (*initfn)(Object *obj);
 365    void (*class_init)(ObjectClass *oc, void *data);
 366} ARMCPUInfo;
 367
 368static const ARMCPUInfo aarch64_cpus[] = {
 369    { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
 370    { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
 371    { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
 372    { .name = "max",                .initfn = aarch64_max_initfn },
 373    { .name = NULL }
 374};
 375
 376static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
 377{
 378    ARMCPU *cpu = ARM_CPU(obj);
 379
 380    return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
 381}
 382
 383static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
 384{
 385    ARMCPU *cpu = ARM_CPU(obj);
 386
 387    /* At this time, this property is only allowed if KVM is enabled.  This
 388     * restriction allows us to avoid fixing up functionality that assumes a
 389     * uniform execution state like do_interrupt.
 390     */
 391    if (!kvm_enabled()) {
 392        error_setg(errp, "'aarch64' feature cannot be disabled "
 393                         "unless KVM is enabled");
 394        return;
 395    }
 396
 397    if (value == false) {
 398        unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
 399    } else {
 400        set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 401    }
 402}
 403
 404static void aarch64_cpu_initfn(Object *obj)
 405{
 406    object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64,
 407                             aarch64_cpu_set_aarch64, NULL);
 408    object_property_set_description(obj, "aarch64",
 409                                    "Set on/off to enable/disable aarch64 "
 410                                    "execution state ",
 411                                    NULL);
 412}
 413
 414static void aarch64_cpu_finalizefn(Object *obj)
 415{
 416}
 417
 418static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
 419{
 420    ARMCPU *cpu = ARM_CPU(cs);
 421    /* It's OK to look at env for the current mode here, because it's
 422     * never possible for an AArch64 TB to chain to an AArch32 TB.
 423     * (Otherwise we would need to use synchronize_from_tb instead.)
 424     */
 425    if (is_a64(&cpu->env)) {
 426        cpu->env.pc = value;
 427    } else {
 428        cpu->env.regs[15] = value;
 429    }
 430}
 431
 432static gchar *aarch64_gdb_arch_name(CPUState *cs)
 433{
 434    return g_strdup("aarch64");
 435}
 436
 437static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
 438{
 439    CPUClass *cc = CPU_CLASS(oc);
 440
 441    cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
 442    cc->set_pc = aarch64_cpu_set_pc;
 443    cc->gdb_read_register = aarch64_cpu_gdb_read_register;
 444    cc->gdb_write_register = aarch64_cpu_gdb_write_register;
 445    cc->gdb_num_core_regs = 34;
 446    cc->gdb_core_xml_file = "aarch64-core.xml";
 447    cc->gdb_arch_name = aarch64_gdb_arch_name;
 448}
 449
 450static void aarch64_cpu_register(const ARMCPUInfo *info)
 451{
 452    TypeInfo type_info = {
 453        .parent = TYPE_AARCH64_CPU,
 454        .instance_size = sizeof(ARMCPU),
 455        .instance_init = info->initfn,
 456        .class_size = sizeof(ARMCPUClass),
 457        .class_init = info->class_init,
 458    };
 459
 460    type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
 461    type_register(&type_info);
 462    g_free((void *)type_info.name);
 463}
 464
 465static const TypeInfo aarch64_cpu_type_info = {
 466    .name = TYPE_AARCH64_CPU,
 467    .parent = TYPE_ARM_CPU,
 468    .instance_size = sizeof(ARMCPU),
 469    .instance_init = aarch64_cpu_initfn,
 470    .instance_finalize = aarch64_cpu_finalizefn,
 471    .abstract = true,
 472    .class_size = sizeof(AArch64CPUClass),
 473    .class_init = aarch64_cpu_class_init,
 474};
 475
 476static void aarch64_cpu_register_types(void)
 477{
 478    const ARMCPUInfo *info = aarch64_cpus;
 479
 480    type_register_static(&aarch64_cpu_type_info);
 481
 482    while (info->name) {
 483        aarch64_cpu_register(info);
 484        info++;
 485    }
 486}
 487
 488type_init(aarch64_cpu_register_types)
 489