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21#ifndef I386_CPU_H
22#define I386_CPU_H
23
24#include "qemu-common.h"
25#include "cpu-qom.h"
26#include "hyperv-proto.h"
27
28#ifdef TARGET_X86_64
29#define TARGET_LONG_BITS 64
30#else
31#define TARGET_LONG_BITS 32
32#endif
33
34#include "exec/cpu-defs.h"
35
36
37#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
38
39
40#define TARGET_MAX_INSN_SIZE 16
41
42
43
44#define TARGET_HAS_PRECISE_SMC
45
46#ifdef TARGET_X86_64
47#define I386_ELF_MACHINE EM_X86_64
48#define ELF_MACHINE_UNAME "x86_64"
49#else
50#define I386_ELF_MACHINE EM_386
51#define ELF_MACHINE_UNAME "i686"
52#endif
53
54#define CPUArchState struct CPUX86State
55
56enum {
57 R_EAX = 0,
58 R_ECX = 1,
59 R_EDX = 2,
60 R_EBX = 3,
61 R_ESP = 4,
62 R_EBP = 5,
63 R_ESI = 6,
64 R_EDI = 7,
65 R_R8 = 8,
66 R_R9 = 9,
67 R_R10 = 10,
68 R_R11 = 11,
69 R_R12 = 12,
70 R_R13 = 13,
71 R_R14 = 14,
72 R_R15 = 15,
73
74 R_AL = 0,
75 R_CL = 1,
76 R_DL = 2,
77 R_BL = 3,
78 R_AH = 4,
79 R_CH = 5,
80 R_DH = 6,
81 R_BH = 7,
82};
83
84typedef enum X86Seg {
85 R_ES = 0,
86 R_CS = 1,
87 R_SS = 2,
88 R_DS = 3,
89 R_FS = 4,
90 R_GS = 5,
91 R_LDTR = 6,
92 R_TR = 7,
93} X86Seg;
94
95
96#define DESC_G_SHIFT 23
97#define DESC_G_MASK (1 << DESC_G_SHIFT)
98#define DESC_B_SHIFT 22
99#define DESC_B_MASK (1 << DESC_B_SHIFT)
100#define DESC_L_SHIFT 21
101#define DESC_L_MASK (1 << DESC_L_SHIFT)
102#define DESC_AVL_SHIFT 20
103#define DESC_AVL_MASK (1 << DESC_AVL_SHIFT)
104#define DESC_P_SHIFT 15
105#define DESC_P_MASK (1 << DESC_P_SHIFT)
106#define DESC_DPL_SHIFT 13
107#define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
108#define DESC_S_SHIFT 12
109#define DESC_S_MASK (1 << DESC_S_SHIFT)
110#define DESC_TYPE_SHIFT 8
111#define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
112#define DESC_A_MASK (1 << 8)
113
114#define DESC_CS_MASK (1 << 11)
115#define DESC_C_MASK (1 << 10)
116#define DESC_R_MASK (1 << 9)
117
118#define DESC_E_MASK (1 << 10)
119#define DESC_W_MASK (1 << 9)
120
121#define DESC_TSS_BUSY_MASK (1 << 9)
122
123
124#define CC_C 0x0001
125#define CC_P 0x0004
126#define CC_A 0x0010
127#define CC_Z 0x0040
128#define CC_S 0x0080
129#define CC_O 0x0800
130
131#define TF_SHIFT 8
132#define IOPL_SHIFT 12
133#define VM_SHIFT 17
134
135#define TF_MASK 0x00000100
136#define IF_MASK 0x00000200
137#define DF_MASK 0x00000400
138#define IOPL_MASK 0x00003000
139#define NT_MASK 0x00004000
140#define RF_MASK 0x00010000
141#define VM_MASK 0x00020000
142#define AC_MASK 0x00040000
143#define VIF_MASK 0x00080000
144#define VIP_MASK 0x00100000
145#define ID_MASK 0x00200000
146
147
148
149
150
151
152#define HF_CPL_SHIFT 0
153
154#define HF_INHIBIT_IRQ_SHIFT 3
155
156#define HF_CS32_SHIFT 4
157#define HF_SS32_SHIFT 5
158
159#define HF_ADDSEG_SHIFT 6
160
161#define HF_PE_SHIFT 7
162#define HF_TF_SHIFT 8
163#define HF_MP_SHIFT 9
164#define HF_EM_SHIFT 10
165#define HF_TS_SHIFT 11
166#define HF_IOPL_SHIFT 12
167#define HF_LMA_SHIFT 14
168#define HF_CS64_SHIFT 15
169#define HF_RF_SHIFT 16
170#define HF_VM_SHIFT 17
171#define HF_AC_SHIFT 18
172#define HF_SMM_SHIFT 19
173#define HF_SVME_SHIFT 20
174#define HF_GUEST_SHIFT 21
175#define HF_OSFXSR_SHIFT 22
176#define HF_SMAP_SHIFT 23
177#define HF_IOBPT_SHIFT 24
178#define HF_MPX_EN_SHIFT 25
179#define HF_MPX_IU_SHIFT 26
180
181#define HF_CPL_MASK (3 << HF_CPL_SHIFT)
182#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
183#define HF_CS32_MASK (1 << HF_CS32_SHIFT)
184#define HF_SS32_MASK (1 << HF_SS32_SHIFT)
185#define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
186#define HF_PE_MASK (1 << HF_PE_SHIFT)
187#define HF_TF_MASK (1 << HF_TF_SHIFT)
188#define HF_MP_MASK (1 << HF_MP_SHIFT)
189#define HF_EM_MASK (1 << HF_EM_SHIFT)
190#define HF_TS_MASK (1 << HF_TS_SHIFT)
191#define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
192#define HF_LMA_MASK (1 << HF_LMA_SHIFT)
193#define HF_CS64_MASK (1 << HF_CS64_SHIFT)
194#define HF_RF_MASK (1 << HF_RF_SHIFT)
195#define HF_VM_MASK (1 << HF_VM_SHIFT)
196#define HF_AC_MASK (1 << HF_AC_SHIFT)
197#define HF_SMM_MASK (1 << HF_SMM_SHIFT)
198#define HF_SVME_MASK (1 << HF_SVME_SHIFT)
199#define HF_GUEST_MASK (1 << HF_GUEST_SHIFT)
200#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
201#define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
202#define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT)
203#define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT)
204#define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT)
205
206
207
208#define HF2_GIF_SHIFT 0
209#define HF2_HIF_SHIFT 1
210#define HF2_NMI_SHIFT 2
211#define HF2_VINTR_SHIFT 3
212#define HF2_SMM_INSIDE_NMI_SHIFT 4
213#define HF2_MPX_PR_SHIFT 5
214#define HF2_NPT_SHIFT 6
215
216#define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
217#define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
218#define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
219#define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
220#define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
221#define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
222#define HF2_NPT_MASK (1 << HF2_NPT_SHIFT)
223
224#define CR0_PE_SHIFT 0
225#define CR0_MP_SHIFT 1
226
227#define CR0_PE_MASK (1U << 0)
228#define CR0_MP_MASK (1U << 1)
229#define CR0_EM_MASK (1U << 2)
230#define CR0_TS_MASK (1U << 3)
231#define CR0_ET_MASK (1U << 4)
232#define CR0_NE_MASK (1U << 5)
233#define CR0_WP_MASK (1U << 16)
234#define CR0_AM_MASK (1U << 18)
235#define CR0_PG_MASK (1U << 31)
236
237#define CR4_VME_MASK (1U << 0)
238#define CR4_PVI_MASK (1U << 1)
239#define CR4_TSD_MASK (1U << 2)
240#define CR4_DE_MASK (1U << 3)
241#define CR4_PSE_MASK (1U << 4)
242#define CR4_PAE_MASK (1U << 5)
243#define CR4_MCE_MASK (1U << 6)
244#define CR4_PGE_MASK (1U << 7)
245#define CR4_PCE_MASK (1U << 8)
246#define CR4_OSFXSR_SHIFT 9
247#define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
248#define CR4_OSXMMEXCPT_MASK (1U << 10)
249#define CR4_LA57_MASK (1U << 12)
250#define CR4_VMXE_MASK (1U << 13)
251#define CR4_SMXE_MASK (1U << 14)
252#define CR4_FSGSBASE_MASK (1U << 16)
253#define CR4_PCIDE_MASK (1U << 17)
254#define CR4_OSXSAVE_MASK (1U << 18)
255#define CR4_SMEP_MASK (1U << 20)
256#define CR4_SMAP_MASK (1U << 21)
257#define CR4_PKE_MASK (1U << 22)
258
259#define DR6_BD (1 << 13)
260#define DR6_BS (1 << 14)
261#define DR6_BT (1 << 15)
262#define DR6_FIXED_1 0xffff0ff0
263
264#define DR7_GD (1 << 13)
265#define DR7_TYPE_SHIFT 16
266#define DR7_LEN_SHIFT 18
267#define DR7_FIXED_1 0x00000400
268#define DR7_GLOBAL_BP_MASK 0xaa
269#define DR7_LOCAL_BP_MASK 0x55
270#define DR7_MAX_BP 4
271#define DR7_TYPE_BP_INST 0x0
272#define DR7_TYPE_DATA_WR 0x1
273#define DR7_TYPE_IO_RW 0x2
274#define DR7_TYPE_DATA_RW 0x3
275
276#define PG_PRESENT_BIT 0
277#define PG_RW_BIT 1
278#define PG_USER_BIT 2
279#define PG_PWT_BIT 3
280#define PG_PCD_BIT 4
281#define PG_ACCESSED_BIT 5
282#define PG_DIRTY_BIT 6
283#define PG_PSE_BIT 7
284#define PG_GLOBAL_BIT 8
285#define PG_PSE_PAT_BIT 12
286#define PG_PKRU_BIT 59
287#define PG_NX_BIT 63
288
289#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
290#define PG_RW_MASK (1 << PG_RW_BIT)
291#define PG_USER_MASK (1 << PG_USER_BIT)
292#define PG_PWT_MASK (1 << PG_PWT_BIT)
293#define PG_PCD_MASK (1 << PG_PCD_BIT)
294#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
295#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
296#define PG_PSE_MASK (1 << PG_PSE_BIT)
297#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
298#define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
299#define PG_ADDRESS_MASK 0x000ffffffffff000LL
300#define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK)
301#define PG_HI_USER_MASK 0x7ff0000000000000LL
302#define PG_PKRU_MASK (15ULL << PG_PKRU_BIT)
303#define PG_NX_MASK (1ULL << PG_NX_BIT)
304
305#define PG_ERROR_W_BIT 1
306
307#define PG_ERROR_P_MASK 0x01
308#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
309#define PG_ERROR_U_MASK 0x04
310#define PG_ERROR_RSVD_MASK 0x08
311#define PG_ERROR_I_D_MASK 0x10
312#define PG_ERROR_PK_MASK 0x20
313
314#define MCG_CTL_P (1ULL<<8)
315#define MCG_SER_P (1ULL<<24)
316#define MCG_LMCE_P (1ULL<<27)
317
318#define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
319#define MCE_BANKS_DEF 10
320
321#define MCG_CAP_BANKS_MASK 0xff
322
323#define MCG_STATUS_RIPV (1ULL<<0)
324#define MCG_STATUS_EIPV (1ULL<<1)
325#define MCG_STATUS_MCIP (1ULL<<2)
326#define MCG_STATUS_LMCE (1ULL<<3)
327
328#define MCG_EXT_CTL_LMCE_EN (1ULL<<0)
329
330#define MCI_STATUS_VAL (1ULL<<63)
331#define MCI_STATUS_OVER (1ULL<<62)
332#define MCI_STATUS_UC (1ULL<<61)
333#define MCI_STATUS_EN (1ULL<<60)
334#define MCI_STATUS_MISCV (1ULL<<59)
335#define MCI_STATUS_ADDRV (1ULL<<58)
336#define MCI_STATUS_PCC (1ULL<<57)
337#define MCI_STATUS_S (1ULL<<56)
338#define MCI_STATUS_AR (1ULL<<55)
339
340
341#define MCM_ADDR_SEGOFF 0
342#define MCM_ADDR_LINEAR 1
343#define MCM_ADDR_PHYS 2
344#define MCM_ADDR_MEM 3
345#define MCM_ADDR_GENERIC 7
346
347#define MSR_IA32_TSC 0x10
348#define MSR_IA32_APICBASE 0x1b
349#define MSR_IA32_APICBASE_BSP (1<<8)
350#define MSR_IA32_APICBASE_ENABLE (1<<11)
351#define MSR_IA32_APICBASE_EXTD (1 << 10)
352#define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
353#define MSR_IA32_FEATURE_CONTROL 0x0000003a
354#define MSR_TSC_ADJUST 0x0000003b
355#define MSR_IA32_SPEC_CTRL 0x48
356#define MSR_VIRT_SSBD 0xc001011f
357#define MSR_IA32_PRED_CMD 0x49
358#define MSR_IA32_ARCH_CAPABILITIES 0x10a
359#define MSR_IA32_TSCDEADLINE 0x6e0
360
361#define FEATURE_CONTROL_LOCKED (1<<0)
362#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
363#define FEATURE_CONTROL_LMCE (1<<20)
364
365#define MSR_P6_PERFCTR0 0xc1
366
367#define MSR_IA32_SMBASE 0x9e
368#define MSR_SMI_COUNT 0x34
369#define MSR_MTRRcap 0xfe
370#define MSR_MTRRcap_VCNT 8
371#define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
372#define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
373
374#define MSR_IA32_SYSENTER_CS 0x174
375#define MSR_IA32_SYSENTER_ESP 0x175
376#define MSR_IA32_SYSENTER_EIP 0x176
377
378#define MSR_MCG_CAP 0x179
379#define MSR_MCG_STATUS 0x17a
380#define MSR_MCG_CTL 0x17b
381#define MSR_MCG_EXT_CTL 0x4d0
382
383#define MSR_P6_EVNTSEL0 0x186
384
385#define MSR_IA32_PERF_STATUS 0x198
386
387#define MSR_IA32_MISC_ENABLE 0x1a0
388
389#define MSR_IA32_MISC_ENABLE_DEFAULT 1
390
391#define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
392#define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
393
394#define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
395
396#define MSR_MTRRfix64K_00000 0x250
397#define MSR_MTRRfix16K_80000 0x258
398#define MSR_MTRRfix16K_A0000 0x259
399#define MSR_MTRRfix4K_C0000 0x268
400#define MSR_MTRRfix4K_C8000 0x269
401#define MSR_MTRRfix4K_D0000 0x26a
402#define MSR_MTRRfix4K_D8000 0x26b
403#define MSR_MTRRfix4K_E0000 0x26c
404#define MSR_MTRRfix4K_E8000 0x26d
405#define MSR_MTRRfix4K_F0000 0x26e
406#define MSR_MTRRfix4K_F8000 0x26f
407
408#define MSR_PAT 0x277
409
410#define MSR_MTRRdefType 0x2ff
411
412#define MSR_CORE_PERF_FIXED_CTR0 0x309
413#define MSR_CORE_PERF_FIXED_CTR1 0x30a
414#define MSR_CORE_PERF_FIXED_CTR2 0x30b
415#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
416#define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
417#define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
418#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
419
420#define MSR_MC0_CTL 0x400
421#define MSR_MC0_STATUS 0x401
422#define MSR_MC0_ADDR 0x402
423#define MSR_MC0_MISC 0x403
424
425#define MSR_IA32_RTIT_OUTPUT_BASE 0x560
426#define MSR_IA32_RTIT_OUTPUT_MASK 0x561
427#define MSR_IA32_RTIT_CTL 0x570
428#define MSR_IA32_RTIT_STATUS 0x571
429#define MSR_IA32_RTIT_CR3_MATCH 0x572
430#define MSR_IA32_RTIT_ADDR0_A 0x580
431#define MSR_IA32_RTIT_ADDR0_B 0x581
432#define MSR_IA32_RTIT_ADDR1_A 0x582
433#define MSR_IA32_RTIT_ADDR1_B 0x583
434#define MSR_IA32_RTIT_ADDR2_A 0x584
435#define MSR_IA32_RTIT_ADDR2_B 0x585
436#define MSR_IA32_RTIT_ADDR3_A 0x586
437#define MSR_IA32_RTIT_ADDR3_B 0x587
438#define MAX_RTIT_ADDRS 8
439
440#define MSR_EFER 0xc0000080
441
442#define MSR_EFER_SCE (1 << 0)
443#define MSR_EFER_LME (1 << 8)
444#define MSR_EFER_LMA (1 << 10)
445#define MSR_EFER_NXE (1 << 11)
446#define MSR_EFER_SVME (1 << 12)
447#define MSR_EFER_FFXSR (1 << 14)
448
449#define MSR_STAR 0xc0000081
450#define MSR_LSTAR 0xc0000082
451#define MSR_CSTAR 0xc0000083
452#define MSR_FMASK 0xc0000084
453#define MSR_FSBASE 0xc0000100
454#define MSR_GSBASE 0xc0000101
455#define MSR_KERNELGSBASE 0xc0000102
456#define MSR_TSC_AUX 0xc0000103
457
458#define MSR_VM_HSAVE_PA 0xc0010117
459
460#define MSR_IA32_BNDCFGS 0x00000d90
461#define MSR_IA32_XSS 0x00000da0
462
463#define XSTATE_FP_BIT 0
464#define XSTATE_SSE_BIT 1
465#define XSTATE_YMM_BIT 2
466#define XSTATE_BNDREGS_BIT 3
467#define XSTATE_BNDCSR_BIT 4
468#define XSTATE_OPMASK_BIT 5
469#define XSTATE_ZMM_Hi256_BIT 6
470#define XSTATE_Hi16_ZMM_BIT 7
471#define XSTATE_PKRU_BIT 9
472
473#define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
474#define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
475#define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT)
476#define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT)
477#define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT)
478#define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT)
479#define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
480#define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
481#define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
482
483
484typedef enum FeatureWord {
485 FEAT_1_EDX,
486 FEAT_1_ECX,
487 FEAT_7_0_EBX,
488 FEAT_7_0_ECX,
489 FEAT_7_0_EDX,
490 FEAT_8000_0001_EDX,
491 FEAT_8000_0001_ECX,
492 FEAT_8000_0007_EDX,
493 FEAT_8000_0008_EBX,
494 FEAT_C000_0001_EDX,
495 FEAT_KVM,
496 FEAT_KVM_HINTS,
497 FEAT_HYPERV_EAX,
498 FEAT_HYPERV_EBX,
499 FEAT_HYPERV_EDX,
500 FEAT_SVM,
501 FEAT_XSAVE,
502 FEAT_6_EAX,
503 FEAT_XSAVE_COMP_LO,
504 FEAT_XSAVE_COMP_HI,
505 FEAT_ARCH_CAPABILITIES,
506 FEATURE_WORDS,
507} FeatureWord;
508
509typedef uint32_t FeatureWordArray[FEATURE_WORDS];
510
511
512#define CPUID_FP87 (1U << 0)
513#define CPUID_VME (1U << 1)
514#define CPUID_DE (1U << 2)
515#define CPUID_PSE (1U << 3)
516#define CPUID_TSC (1U << 4)
517#define CPUID_MSR (1U << 5)
518#define CPUID_PAE (1U << 6)
519#define CPUID_MCE (1U << 7)
520#define CPUID_CX8 (1U << 8)
521#define CPUID_APIC (1U << 9)
522#define CPUID_SEP (1U << 11)
523#define CPUID_MTRR (1U << 12)
524#define CPUID_PGE (1U << 13)
525#define CPUID_MCA (1U << 14)
526#define CPUID_CMOV (1U << 15)
527#define CPUID_PAT (1U << 16)
528#define CPUID_PSE36 (1U << 17)
529#define CPUID_PN (1U << 18)
530#define CPUID_CLFLUSH (1U << 19)
531#define CPUID_DTS (1U << 21)
532#define CPUID_ACPI (1U << 22)
533#define CPUID_MMX (1U << 23)
534#define CPUID_FXSR (1U << 24)
535#define CPUID_SSE (1U << 25)
536#define CPUID_SSE2 (1U << 26)
537#define CPUID_SS (1U << 27)
538#define CPUID_HT (1U << 28)
539#define CPUID_TM (1U << 29)
540#define CPUID_IA64 (1U << 30)
541#define CPUID_PBE (1U << 31)
542
543#define CPUID_EXT_SSE3 (1U << 0)
544#define CPUID_EXT_PCLMULQDQ (1U << 1)
545#define CPUID_EXT_DTES64 (1U << 2)
546#define CPUID_EXT_MONITOR (1U << 3)
547#define CPUID_EXT_DSCPL (1U << 4)
548#define CPUID_EXT_VMX (1U << 5)
549#define CPUID_EXT_SMX (1U << 6)
550#define CPUID_EXT_EST (1U << 7)
551#define CPUID_EXT_TM2 (1U << 8)
552#define CPUID_EXT_SSSE3 (1U << 9)
553#define CPUID_EXT_CID (1U << 10)
554#define CPUID_EXT_FMA (1U << 12)
555#define CPUID_EXT_CX16 (1U << 13)
556#define CPUID_EXT_XTPR (1U << 14)
557#define CPUID_EXT_PDCM (1U << 15)
558#define CPUID_EXT_PCID (1U << 17)
559#define CPUID_EXT_DCA (1U << 18)
560#define CPUID_EXT_SSE41 (1U << 19)
561#define CPUID_EXT_SSE42 (1U << 20)
562#define CPUID_EXT_X2APIC (1U << 21)
563#define CPUID_EXT_MOVBE (1U << 22)
564#define CPUID_EXT_POPCNT (1U << 23)
565#define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
566#define CPUID_EXT_AES (1U << 25)
567#define CPUID_EXT_XSAVE (1U << 26)
568#define CPUID_EXT_OSXSAVE (1U << 27)
569#define CPUID_EXT_AVX (1U << 28)
570#define CPUID_EXT_F16C (1U << 29)
571#define CPUID_EXT_RDRAND (1U << 30)
572#define CPUID_EXT_HYPERVISOR (1U << 31)
573
574#define CPUID_EXT2_FPU (1U << 0)
575#define CPUID_EXT2_VME (1U << 1)
576#define CPUID_EXT2_DE (1U << 2)
577#define CPUID_EXT2_PSE (1U << 3)
578#define CPUID_EXT2_TSC (1U << 4)
579#define CPUID_EXT2_MSR (1U << 5)
580#define CPUID_EXT2_PAE (1U << 6)
581#define CPUID_EXT2_MCE (1U << 7)
582#define CPUID_EXT2_CX8 (1U << 8)
583#define CPUID_EXT2_APIC (1U << 9)
584#define CPUID_EXT2_SYSCALL (1U << 11)
585#define CPUID_EXT2_MTRR (1U << 12)
586#define CPUID_EXT2_PGE (1U << 13)
587#define CPUID_EXT2_MCA (1U << 14)
588#define CPUID_EXT2_CMOV (1U << 15)
589#define CPUID_EXT2_PAT (1U << 16)
590#define CPUID_EXT2_PSE36 (1U << 17)
591#define CPUID_EXT2_MP (1U << 19)
592#define CPUID_EXT2_NX (1U << 20)
593#define CPUID_EXT2_MMXEXT (1U << 22)
594#define CPUID_EXT2_MMX (1U << 23)
595#define CPUID_EXT2_FXSR (1U << 24)
596#define CPUID_EXT2_FFXSR (1U << 25)
597#define CPUID_EXT2_PDPE1GB (1U << 26)
598#define CPUID_EXT2_RDTSCP (1U << 27)
599#define CPUID_EXT2_LM (1U << 29)
600#define CPUID_EXT2_3DNOWEXT (1U << 30)
601#define CPUID_EXT2_3DNOW (1U << 31)
602
603
604#define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
605 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
606 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
607 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
608 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
609 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
610 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
611 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
612 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
613
614#define CPUID_EXT3_LAHF_LM (1U << 0)
615#define CPUID_EXT3_CMP_LEG (1U << 1)
616#define CPUID_EXT3_SVM (1U << 2)
617#define CPUID_EXT3_EXTAPIC (1U << 3)
618#define CPUID_EXT3_CR8LEG (1U << 4)
619#define CPUID_EXT3_ABM (1U << 5)
620#define CPUID_EXT3_SSE4A (1U << 6)
621#define CPUID_EXT3_MISALIGNSSE (1U << 7)
622#define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
623#define CPUID_EXT3_OSVW (1U << 9)
624#define CPUID_EXT3_IBS (1U << 10)
625#define CPUID_EXT3_XOP (1U << 11)
626#define CPUID_EXT3_SKINIT (1U << 12)
627#define CPUID_EXT3_WDT (1U << 13)
628#define CPUID_EXT3_LWP (1U << 15)
629#define CPUID_EXT3_FMA4 (1U << 16)
630#define CPUID_EXT3_TCE (1U << 17)
631#define CPUID_EXT3_NODEID (1U << 19)
632#define CPUID_EXT3_TBM (1U << 21)
633#define CPUID_EXT3_TOPOEXT (1U << 22)
634#define CPUID_EXT3_PERFCORE (1U << 23)
635#define CPUID_EXT3_PERFNB (1U << 24)
636
637#define CPUID_SVM_NPT (1U << 0)
638#define CPUID_SVM_LBRV (1U << 1)
639#define CPUID_SVM_SVMLOCK (1U << 2)
640#define CPUID_SVM_NRIPSAVE (1U << 3)
641#define CPUID_SVM_TSCSCALE (1U << 4)
642#define CPUID_SVM_VMCBCLEAN (1U << 5)
643#define CPUID_SVM_FLUSHASID (1U << 6)
644#define CPUID_SVM_DECODEASSIST (1U << 7)
645#define CPUID_SVM_PAUSEFILTER (1U << 10)
646#define CPUID_SVM_PFTHRESHOLD (1U << 12)
647
648#define CPUID_7_0_EBX_FSGSBASE (1U << 0)
649#define CPUID_7_0_EBX_BMI1 (1U << 3)
650#define CPUID_7_0_EBX_HLE (1U << 4)
651#define CPUID_7_0_EBX_AVX2 (1U << 5)
652#define CPUID_7_0_EBX_SMEP (1U << 7)
653#define CPUID_7_0_EBX_BMI2 (1U << 8)
654#define CPUID_7_0_EBX_ERMS (1U << 9)
655#define CPUID_7_0_EBX_INVPCID (1U << 10)
656#define CPUID_7_0_EBX_RTM (1U << 11)
657#define CPUID_7_0_EBX_MPX (1U << 14)
658#define CPUID_7_0_EBX_AVX512F (1U << 16)
659#define CPUID_7_0_EBX_AVX512DQ (1U << 17)
660#define CPUID_7_0_EBX_RDSEED (1U << 18)
661#define CPUID_7_0_EBX_ADX (1U << 19)
662#define CPUID_7_0_EBX_SMAP (1U << 20)
663#define CPUID_7_0_EBX_AVX512IFMA (1U << 21)
664#define CPUID_7_0_EBX_PCOMMIT (1U << 22)
665#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23)
666#define CPUID_7_0_EBX_CLWB (1U << 24)
667#define CPUID_7_0_EBX_INTEL_PT (1U << 25)
668#define CPUID_7_0_EBX_AVX512PF (1U << 26)
669#define CPUID_7_0_EBX_AVX512ER (1U << 27)
670#define CPUID_7_0_EBX_AVX512CD (1U << 28)
671#define CPUID_7_0_EBX_SHA_NI (1U << 29)
672#define CPUID_7_0_EBX_AVX512BW (1U << 30)
673#define CPUID_7_0_EBX_AVX512VL (1U << 31)
674
675#define CPUID_7_0_ECX_AVX512BMI (1U << 1)
676#define CPUID_7_0_ECX_VBMI (1U << 1)
677#define CPUID_7_0_ECX_UMIP (1U << 2)
678#define CPUID_7_0_ECX_PKU (1U << 3)
679#define CPUID_7_0_ECX_OSPKE (1U << 4)
680#define CPUID_7_0_ECX_VBMI2 (1U << 6)
681#define CPUID_7_0_ECX_GFNI (1U << 8)
682#define CPUID_7_0_ECX_VAES (1U << 9)
683#define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
684#define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
685#define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
686#define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14)
687#define CPUID_7_0_ECX_LA57 (1U << 16)
688#define CPUID_7_0_ECX_RDPID (1U << 22)
689#define CPUID_7_0_ECX_CLDEMOTE (1U << 25)
690
691#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
692#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
693#define CPUID_7_0_EDX_PCONFIG (1U << 18)
694#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
695#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
696#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31)
697
698#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9)
699
700#define CPUID_8000_0008_EBX_IBPB (1U << 12)
701
702#define CPUID_XSAVE_XSAVEOPT (1U << 0)
703#define CPUID_XSAVE_XSAVEC (1U << 1)
704#define CPUID_XSAVE_XGETBV1 (1U << 2)
705#define CPUID_XSAVE_XSAVES (1U << 3)
706
707#define CPUID_6_EAX_ARAT (1U << 2)
708
709
710#define CPUID_APM_INVTSC (1U << 8)
711
712#define CPUID_VENDOR_SZ 12
713
714#define CPUID_VENDOR_INTEL_1 0x756e6547
715#define CPUID_VENDOR_INTEL_2 0x49656e69
716#define CPUID_VENDOR_INTEL_3 0x6c65746e
717#define CPUID_VENDOR_INTEL "GenuineIntel"
718
719#define CPUID_VENDOR_AMD_1 0x68747541
720#define CPUID_VENDOR_AMD_2 0x69746e65
721#define CPUID_VENDOR_AMD_3 0x444d4163
722#define CPUID_VENDOR_AMD "AuthenticAMD"
723
724#define CPUID_VENDOR_VIA "CentaurHauls"
725
726#define CPUID_MWAIT_IBE (1U << 1)
727#define CPUID_MWAIT_EMX (1U << 0)
728
729
730#define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8)
731#define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
732#define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
733
734
735#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
736#define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
737#define MSR_ARCH_CAP_RSBA (1U << 2)
738#define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
739#define MSR_ARCH_CAP_SSB_NO (1U << 4)
740
741#ifndef HYPERV_SPINLOCK_NEVER_RETRY
742#define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF
743#endif
744
745#define EXCP00_DIVZ 0
746#define EXCP01_DB 1
747#define EXCP02_NMI 2
748#define EXCP03_INT3 3
749#define EXCP04_INTO 4
750#define EXCP05_BOUND 5
751#define EXCP06_ILLOP 6
752#define EXCP07_PREX 7
753#define EXCP08_DBLE 8
754#define EXCP09_XERR 9
755#define EXCP0A_TSS 10
756#define EXCP0B_NOSEG 11
757#define EXCP0C_STACK 12
758#define EXCP0D_GPF 13
759#define EXCP0E_PAGE 14
760#define EXCP10_COPR 16
761#define EXCP11_ALGN 17
762#define EXCP12_MCHK 18
763
764#define EXCP_SYSCALL 0x100
765
766#define EXCP_VMEXIT 0x100
767
768
769#define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
770#define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
771#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
772#define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
773#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
774#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
775#define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
776
777
778#define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
779
780
781
782
783
784
785
786
787typedef enum {
788 CC_OP_DYNAMIC,
789 CC_OP_EFLAGS,
790
791 CC_OP_MULB,
792 CC_OP_MULW,
793 CC_OP_MULL,
794 CC_OP_MULQ,
795
796 CC_OP_ADDB,
797 CC_OP_ADDW,
798 CC_OP_ADDL,
799 CC_OP_ADDQ,
800
801 CC_OP_ADCB,
802 CC_OP_ADCW,
803 CC_OP_ADCL,
804 CC_OP_ADCQ,
805
806 CC_OP_SUBB,
807 CC_OP_SUBW,
808 CC_OP_SUBL,
809 CC_OP_SUBQ,
810
811 CC_OP_SBBB,
812 CC_OP_SBBW,
813 CC_OP_SBBL,
814 CC_OP_SBBQ,
815
816 CC_OP_LOGICB,
817 CC_OP_LOGICW,
818 CC_OP_LOGICL,
819 CC_OP_LOGICQ,
820
821 CC_OP_INCB,
822 CC_OP_INCW,
823 CC_OP_INCL,
824 CC_OP_INCQ,
825
826 CC_OP_DECB,
827 CC_OP_DECW,
828 CC_OP_DECL,
829 CC_OP_DECQ,
830
831 CC_OP_SHLB,
832 CC_OP_SHLW,
833 CC_OP_SHLL,
834 CC_OP_SHLQ,
835
836 CC_OP_SARB,
837 CC_OP_SARW,
838 CC_OP_SARL,
839 CC_OP_SARQ,
840
841 CC_OP_BMILGB,
842 CC_OP_BMILGW,
843 CC_OP_BMILGL,
844 CC_OP_BMILGQ,
845
846 CC_OP_ADCX,
847 CC_OP_ADOX,
848 CC_OP_ADCOX,
849
850 CC_OP_CLR,
851 CC_OP_POPCNT,
852
853 CC_OP_NB,
854} CCOp;
855
856typedef struct SegmentCache {
857 uint32_t selector;
858 target_ulong base;
859 uint32_t limit;
860 uint32_t flags;
861} SegmentCache;
862
863#define MMREG_UNION(n, bits) \
864 union n { \
865 uint8_t _b_##n[(bits)/8]; \
866 uint16_t _w_##n[(bits)/16]; \
867 uint32_t _l_##n[(bits)/32]; \
868 uint64_t _q_##n[(bits)/64]; \
869 float32 _s_##n[(bits)/32]; \
870 float64 _d_##n[(bits)/64]; \
871 }
872
873typedef union {
874 uint8_t _b[16];
875 uint16_t _w[8];
876 uint32_t _l[4];
877 uint64_t _q[2];
878} XMMReg;
879
880typedef union {
881 uint8_t _b[32];
882 uint16_t _w[16];
883 uint32_t _l[8];
884 uint64_t _q[4];
885} YMMReg;
886
887typedef MMREG_UNION(ZMMReg, 512) ZMMReg;
888typedef MMREG_UNION(MMXReg, 64) MMXReg;
889
890typedef struct BNDReg {
891 uint64_t lb;
892 uint64_t ub;
893} BNDReg;
894
895typedef struct BNDCSReg {
896 uint64_t cfgu;
897 uint64_t sts;
898} BNDCSReg;
899
900#define BNDCFG_ENABLE 1ULL
901#define BNDCFG_BNDPRESERVE 2ULL
902#define BNDCFG_BDIR_MASK TARGET_PAGE_MASK
903
904#ifdef HOST_WORDS_BIGENDIAN
905#define ZMM_B(n) _b_ZMMReg[63 - (n)]
906#define ZMM_W(n) _w_ZMMReg[31 - (n)]
907#define ZMM_L(n) _l_ZMMReg[15 - (n)]
908#define ZMM_S(n) _s_ZMMReg[15 - (n)]
909#define ZMM_Q(n) _q_ZMMReg[7 - (n)]
910#define ZMM_D(n) _d_ZMMReg[7 - (n)]
911
912#define MMX_B(n) _b_MMXReg[7 - (n)]
913#define MMX_W(n) _w_MMXReg[3 - (n)]
914#define MMX_L(n) _l_MMXReg[1 - (n)]
915#define MMX_S(n) _s_MMXReg[1 - (n)]
916#else
917#define ZMM_B(n) _b_ZMMReg[n]
918#define ZMM_W(n) _w_ZMMReg[n]
919#define ZMM_L(n) _l_ZMMReg[n]
920#define ZMM_S(n) _s_ZMMReg[n]
921#define ZMM_Q(n) _q_ZMMReg[n]
922#define ZMM_D(n) _d_ZMMReg[n]
923
924#define MMX_B(n) _b_MMXReg[n]
925#define MMX_W(n) _w_MMXReg[n]
926#define MMX_L(n) _l_MMXReg[n]
927#define MMX_S(n) _s_MMXReg[n]
928#endif
929#define MMX_Q(n) _q_MMXReg[n]
930
931typedef union {
932 floatx80 d __attribute__((aligned(16)));
933 MMXReg mmx;
934} FPReg;
935
936typedef struct {
937 uint64_t base;
938 uint64_t mask;
939} MTRRVar;
940
941#define CPU_NB_REGS64 16
942#define CPU_NB_REGS32 8
943
944#ifdef TARGET_X86_64
945#define CPU_NB_REGS CPU_NB_REGS64
946#else
947#define CPU_NB_REGS CPU_NB_REGS32
948#endif
949
950#define MAX_FIXED_COUNTERS 3
951#define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
952
953#define NB_MMU_MODES 3
954#define TARGET_INSN_START_EXTRA_WORDS 1
955
956#define NB_OPMASK_REGS 8
957
958
959
960
961#define UNASSIGNED_APIC_ID 0xFFFFFFFF
962
963typedef union X86LegacyXSaveArea {
964 struct {
965 uint16_t fcw;
966 uint16_t fsw;
967 uint8_t ftw;
968 uint8_t reserved;
969 uint16_t fpop;
970 uint64_t fpip;
971 uint64_t fpdp;
972 uint32_t mxcsr;
973 uint32_t mxcsr_mask;
974 FPReg fpregs[8];
975 uint8_t xmm_regs[16][16];
976 };
977 uint8_t data[512];
978} X86LegacyXSaveArea;
979
980typedef struct X86XSaveHeader {
981 uint64_t xstate_bv;
982 uint64_t xcomp_bv;
983 uint64_t reserve0;
984 uint8_t reserved[40];
985} X86XSaveHeader;
986
987
988typedef struct XSaveAVX {
989 uint8_t ymmh[16][16];
990} XSaveAVX;
991
992
993typedef struct XSaveBNDREG {
994 BNDReg bnd_regs[4];
995} XSaveBNDREG;
996
997
998typedef union XSaveBNDCSR {
999 BNDCSReg bndcsr;
1000 uint8_t data[64];
1001} XSaveBNDCSR;
1002
1003
1004typedef struct XSaveOpmask {
1005 uint64_t opmask_regs[NB_OPMASK_REGS];
1006} XSaveOpmask;
1007
1008
1009typedef struct XSaveZMM_Hi256 {
1010 uint8_t zmm_hi256[16][32];
1011} XSaveZMM_Hi256;
1012
1013
1014typedef struct XSaveHi16_ZMM {
1015 uint8_t hi16_zmm[16][64];
1016} XSaveHi16_ZMM;
1017
1018
1019typedef struct XSavePKRU {
1020 uint32_t pkru;
1021 uint32_t padding;
1022} XSavePKRU;
1023
1024typedef struct X86XSaveArea {
1025 X86LegacyXSaveArea legacy;
1026 X86XSaveHeader header;
1027
1028
1029
1030
1031 XSaveAVX avx_state;
1032 uint8_t padding[960 - 576 - sizeof(XSaveAVX)];
1033
1034 XSaveBNDREG bndreg_state;
1035 XSaveBNDCSR bndcsr_state;
1036
1037 XSaveOpmask opmask_state;
1038 XSaveZMM_Hi256 zmm_hi256_state;
1039 XSaveHi16_ZMM hi16_zmm_state;
1040
1041 XSavePKRU pkru_state;
1042} X86XSaveArea;
1043
1044QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240);
1045QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
1046QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0);
1047QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
1048QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400);
1049QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
1050QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440);
1051QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
1052QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480);
1053QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
1054QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680);
1055QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
1056QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80);
1057QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
1058
1059typedef enum TPRAccess {
1060 TPR_ACCESS_READ,
1061 TPR_ACCESS_WRITE,
1062} TPRAccess;
1063
1064
1065
1066enum CacheType {
1067 DATA_CACHE,
1068 INSTRUCTION_CACHE,
1069 UNIFIED_CACHE
1070};
1071
1072typedef struct CPUCacheInfo {
1073 enum CacheType type;
1074 uint8_t level;
1075
1076 uint32_t size;
1077
1078 uint16_t line_size;
1079
1080
1081
1082
1083 uint8_t associativity;
1084
1085 uint8_t partitions;
1086
1087 uint32_t sets;
1088
1089
1090
1091
1092
1093 uint8_t lines_per_tag;
1094
1095
1096 bool self_init;
1097
1098
1099
1100
1101
1102 bool no_invd_sharing;
1103
1104
1105
1106
1107 bool inclusive;
1108
1109
1110
1111
1112 bool complex_indexing;
1113} CPUCacheInfo;
1114
1115
1116typedef struct CPUCaches {
1117 CPUCacheInfo *l1d_cache;
1118 CPUCacheInfo *l1i_cache;
1119 CPUCacheInfo *l2_cache;
1120 CPUCacheInfo *l3_cache;
1121} CPUCaches;
1122
1123typedef struct CPUX86State {
1124
1125 target_ulong regs[CPU_NB_REGS];
1126 target_ulong eip;
1127 target_ulong eflags;
1128
1129
1130
1131
1132 target_ulong cc_dst;
1133 target_ulong cc_src;
1134 target_ulong cc_src2;
1135 uint32_t cc_op;
1136 int32_t df;
1137 uint32_t hflags;
1138
1139 uint32_t hflags2;
1140
1141
1142 SegmentCache segs[6];
1143 SegmentCache ldt;
1144 SegmentCache tr;
1145 SegmentCache gdt;
1146 SegmentCache idt;
1147
1148 target_ulong cr[5];
1149 int32_t a20_mask;
1150
1151 BNDReg bnd_regs[4];
1152 BNDCSReg bndcs_regs;
1153 uint64_t msr_bndcfgs;
1154 uint64_t efer;
1155
1156
1157 struct {} start_init_save;
1158
1159
1160 unsigned int fpstt;
1161 uint16_t fpus;
1162 uint16_t fpuc;
1163 uint8_t fptags[8];
1164 FPReg fpregs[8];
1165
1166 uint16_t fpop;
1167 uint64_t fpip;
1168 uint64_t fpdp;
1169
1170
1171 float_status fp_status;
1172 floatx80 ft0;
1173
1174 float_status mmx_status;
1175 float_status sse_status;
1176 uint32_t mxcsr;
1177 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32];
1178 ZMMReg xmm_t0;
1179 MMXReg mmx_t0;
1180
1181 XMMReg ymmh_regs[CPU_NB_REGS];
1182
1183 uint64_t opmask_regs[NB_OPMASK_REGS];
1184 YMMReg zmmh_regs[CPU_NB_REGS];
1185 ZMMReg hi16_zmm_regs[CPU_NB_REGS];
1186
1187
1188 uint32_t sysenter_cs;
1189 target_ulong sysenter_esp;
1190 target_ulong sysenter_eip;
1191 uint64_t star;
1192
1193 uint64_t vm_hsave;
1194
1195#ifdef TARGET_X86_64
1196 target_ulong lstar;
1197 target_ulong cstar;
1198 target_ulong fmask;
1199 target_ulong kernelgsbase;
1200#endif
1201
1202 uint64_t tsc;
1203 uint64_t tsc_adjust;
1204 uint64_t tsc_deadline;
1205 uint64_t tsc_aux;
1206
1207 uint64_t xcr0;
1208
1209 uint64_t mcg_status;
1210 uint64_t msr_ia32_misc_enable;
1211 uint64_t msr_ia32_feature_control;
1212
1213 uint64_t msr_fixed_ctr_ctrl;
1214 uint64_t msr_global_ctrl;
1215 uint64_t msr_global_status;
1216 uint64_t msr_global_ovf_ctrl;
1217 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
1218 uint64_t msr_gp_counters[MAX_GP_COUNTERS];
1219 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
1220
1221 uint64_t pat;
1222 uint32_t smbase;
1223 uint64_t msr_smi_count;
1224
1225 uint32_t pkru;
1226
1227 uint64_t spec_ctrl;
1228 uint64_t virt_ssbd;
1229
1230
1231 struct {} end_init_save;
1232
1233 uint64_t system_time_msr;
1234 uint64_t wall_clock_msr;
1235 uint64_t steal_time_msr;
1236 uint64_t async_pf_en_msr;
1237 uint64_t pv_eoi_en_msr;
1238
1239
1240 uint64_t msr_hv_hypercall;
1241 uint64_t msr_hv_guest_os_id;
1242 uint64_t msr_hv_tsc;
1243
1244
1245 uint64_t msr_hv_vapic;
1246 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS];
1247 uint64_t msr_hv_runtime;
1248 uint64_t msr_hv_synic_control;
1249 uint64_t msr_hv_synic_evt_page;
1250 uint64_t msr_hv_synic_msg_page;
1251 uint64_t msr_hv_synic_sint[HV_SINT_COUNT];
1252 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT];
1253 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT];
1254 uint64_t msr_hv_reenlightenment_control;
1255 uint64_t msr_hv_tsc_emulation_control;
1256 uint64_t msr_hv_tsc_emulation_status;
1257
1258 uint64_t msr_rtit_ctrl;
1259 uint64_t msr_rtit_status;
1260 uint64_t msr_rtit_output_base;
1261 uint64_t msr_rtit_output_mask;
1262 uint64_t msr_rtit_cr3_match;
1263 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
1264
1265
1266 int error_code;
1267 int exception_is_int;
1268 target_ulong exception_next_eip;
1269 target_ulong dr[8];
1270 union {
1271 struct CPUBreakpoint *cpu_breakpoint[4];
1272 struct CPUWatchpoint *cpu_watchpoint[4];
1273 };
1274 int old_exception;
1275
1276 uint64_t vm_vmcb;
1277 uint64_t tsc_offset;
1278 uint64_t intercept;
1279 uint16_t intercept_cr_read;
1280 uint16_t intercept_cr_write;
1281 uint16_t intercept_dr_read;
1282 uint16_t intercept_dr_write;
1283 uint32_t intercept_exceptions;
1284 uint64_t nested_cr3;
1285 uint32_t nested_pg_mode;
1286 uint8_t v_tpr;
1287
1288
1289 uint8_t nmi_injected;
1290 uint8_t nmi_pending;
1291
1292 uintptr_t retaddr;
1293
1294
1295 struct {} end_reset_fields;
1296
1297 CPU_COMMON
1298
1299
1300
1301
1302
1303 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2;
1304
1305 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2;
1306
1307 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2;
1308 uint32_t cpuid_vendor1;
1309 uint32_t cpuid_vendor2;
1310 uint32_t cpuid_vendor3;
1311 uint32_t cpuid_version;
1312 FeatureWordArray features;
1313
1314 FeatureWordArray user_features;
1315 uint32_t cpuid_model[12];
1316
1317
1318
1319
1320 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd;
1321
1322
1323 uint64_t mtrr_fixed[11];
1324 uint64_t mtrr_deftype;
1325 MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
1326
1327
1328 uint32_t mp_state;
1329 int32_t exception_injected;
1330 int32_t interrupt_injected;
1331 uint8_t soft_interrupt;
1332 uint8_t has_error_code;
1333 uint32_t ins_len;
1334 uint32_t sipi_vector;
1335 bool tsc_valid;
1336 int64_t tsc_khz;
1337 int64_t user_tsc_khz;
1338#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
1339 void *xsave_buf;
1340#endif
1341#if defined(CONFIG_HVF)
1342 HVFX86EmulatorState *hvf_emul;
1343#endif
1344
1345 uint64_t mcg_cap;
1346 uint64_t mcg_ctl;
1347 uint64_t mcg_ext_ctl;
1348 uint64_t mce_banks[MCE_BANKS_DEF*4];
1349 uint64_t xstate_bv;
1350
1351
1352 uint16_t fpus_vmstate;
1353 uint16_t fptag_vmstate;
1354 uint16_t fpregs_format_vmstate;
1355
1356 uint64_t xss;
1357
1358 TPRAccess tpr_access_type;
1359} CPUX86State;
1360
1361struct kvm_msrs;
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372struct X86CPU {
1373
1374 CPUState parent_obj;
1375
1376
1377 CPUX86State env;
1378
1379 bool hyperv_vapic;
1380 bool hyperv_relaxed_timing;
1381 int hyperv_spinlock_attempts;
1382 char *hyperv_vendor_id;
1383 bool hyperv_time;
1384 bool hyperv_crash;
1385 bool hyperv_reset;
1386 bool hyperv_vpindex;
1387 bool hyperv_runtime;
1388 bool hyperv_synic;
1389 bool hyperv_synic_kvm_only;
1390 bool hyperv_stimer;
1391 bool hyperv_frequencies;
1392 bool hyperv_reenlightenment;
1393 bool hyperv_tlbflush;
1394 bool hyperv_evmcs;
1395 bool hyperv_ipi;
1396 bool check_cpuid;
1397 bool enforce_cpuid;
1398 bool expose_kvm;
1399 bool expose_tcg;
1400 bool migratable;
1401 bool migrate_smi_count;
1402 bool max_features;
1403 uint32_t apic_id;
1404
1405
1406
1407 bool vmware_cpuid_freq;
1408
1409
1410 bool cache_info_passthrough;
1411
1412
1413
1414 struct {
1415 uint32_t eax;
1416 uint32_t ebx;
1417 uint32_t ecx;
1418 uint32_t edx;
1419 } mwait;
1420
1421
1422 uint32_t filtered_features[FEATURE_WORDS];
1423
1424
1425
1426
1427
1428
1429 bool enable_pmu;
1430
1431
1432
1433
1434
1435 bool enable_lmce;
1436
1437
1438
1439
1440
1441 bool enable_l3_cache;
1442
1443
1444
1445
1446 bool legacy_cache;
1447
1448
1449 bool enable_cpuid_0xb;
1450
1451
1452 bool full_cpuid_auto_level;
1453
1454
1455 bool fill_mtrr_mask;
1456
1457
1458 bool host_phys_bits;
1459
1460
1461 bool kvm_no_smi_migration;
1462
1463
1464 uint32_t phys_bits;
1465
1466
1467
1468 struct DeviceState *apic_state;
1469 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
1470 Notifier machine_done;
1471
1472 struct kvm_msrs *kvm_msr_buf;
1473
1474 int32_t node_id;
1475 int32_t socket_id;
1476 int32_t core_id;
1477 int32_t thread_id;
1478
1479 int32_t hv_max_vps;
1480};
1481
1482static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
1483{
1484 return container_of(env, X86CPU, env);
1485}
1486
1487#define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
1488
1489#define ENV_OFFSET offsetof(X86CPU, env)
1490
1491#ifndef CONFIG_USER_ONLY
1492extern struct VMStateDescription vmstate_x86_cpu;
1493#endif
1494
1495
1496
1497
1498
1499void x86_cpu_do_interrupt(CPUState *cpu);
1500bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
1501int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
1502
1503int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
1504 int cpuid, void *opaque);
1505int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
1506 int cpuid, void *opaque);
1507int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1508 void *opaque);
1509int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1510 void *opaque);
1511
1512void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
1513 Error **errp);
1514
1515void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
1516 int flags);
1517
1518hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1519
1520int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1521int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1522
1523void x86_cpu_exec_enter(CPUState *cpu);
1524void x86_cpu_exec_exit(CPUState *cpu);
1525
1526void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1527int cpu_x86_support_mca_broadcast(CPUX86State *env);
1528
1529int cpu_get_pic_interrupt(CPUX86State *s);
1530
1531void cpu_set_ferr(CPUX86State *s);
1532
1533void cpu_sync_bndcs_hflags(CPUX86State *env);
1534
1535
1536
1537static inline void cpu_x86_load_seg_cache(CPUX86State *env,
1538 int seg_reg, unsigned int selector,
1539 target_ulong base,
1540 unsigned int limit,
1541 unsigned int flags)
1542{
1543 SegmentCache *sc;
1544 unsigned int new_hflags;
1545
1546 sc = &env->segs[seg_reg];
1547 sc->selector = selector;
1548 sc->base = base;
1549 sc->limit = limit;
1550 sc->flags = flags;
1551
1552
1553 {
1554 if (seg_reg == R_CS) {
1555#ifdef TARGET_X86_64
1556 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
1557
1558 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1559 env->hflags &= ~(HF_ADDSEG_MASK);
1560 } else
1561#endif
1562 {
1563
1564 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
1565 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
1566 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
1567 new_hflags;
1568 }
1569 }
1570 if (seg_reg == R_SS) {
1571 int cpl = (flags >> DESC_DPL_SHIFT) & 3;
1572#if HF_CPL_MASK != 3
1573#error HF_CPL_MASK is hardcoded
1574#endif
1575 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
1576
1577 cpu_sync_bndcs_hflags(env);
1578 }
1579 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
1580 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
1581 if (env->hflags & HF_CS64_MASK) {
1582
1583 } else if (!(env->cr[0] & CR0_PE_MASK) ||
1584 (env->eflags & VM_MASK) ||
1585 !(env->hflags & HF_CS32_MASK)) {
1586
1587
1588
1589
1590
1591 new_hflags |= HF_ADDSEG_MASK;
1592 } else {
1593 new_hflags |= ((env->segs[R_DS].base |
1594 env->segs[R_ES].base |
1595 env->segs[R_SS].base) != 0) <<
1596 HF_ADDSEG_SHIFT;
1597 }
1598 env->hflags = (env->hflags &
1599 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
1600 }
1601}
1602
1603static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
1604 uint8_t sipi_vector)
1605{
1606 CPUState *cs = CPU(cpu);
1607 CPUX86State *env = &cpu->env;
1608
1609 env->eip = 0;
1610 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
1611 sipi_vector << 12,
1612 env->segs[R_CS].limit,
1613 env->segs[R_CS].flags);
1614 cs->halted = 0;
1615}
1616
1617int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
1618 target_ulong *base, unsigned int *limit,
1619 unsigned int *flags);
1620
1621
1622
1623
1624
1625
1626
1627void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
1628void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
1629void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
1630void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr);
1631void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr);
1632
1633
1634
1635
1636int cpu_x86_signal_handler(int host_signum, void *pinfo,
1637 void *puc);
1638
1639
1640void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1641 uint32_t *eax, uint32_t *ebx,
1642 uint32_t *ecx, uint32_t *edx);
1643void cpu_clear_apic_feature(CPUX86State *env);
1644void host_cpuid(uint32_t function, uint32_t count,
1645 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
1646void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
1647
1648
1649int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr, int size,
1650 int is_write, int mmu_idx);
1651void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
1652
1653#ifndef CONFIG_USER_ONLY
1654static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
1655{
1656 return !!attrs.secure;
1657}
1658
1659static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs)
1660{
1661 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs));
1662}
1663
1664uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
1665uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
1666uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
1667uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
1668void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
1669void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
1670void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
1671void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
1672void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
1673#endif
1674
1675void breakpoint_handler(CPUState *cs);
1676
1677
1678void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
1679void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
1680void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
1681void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
1682
1683
1684uint64_t cpu_get_tsc(CPUX86State *env);
1685
1686#define TARGET_PAGE_BITS 12
1687
1688#ifdef TARGET_X86_64
1689#define TARGET_PHYS_ADDR_SPACE_BITS 52
1690
1691
1692
1693#define TARGET_VIRT_ADDR_SPACE_BITS 47
1694#else
1695#define TARGET_PHYS_ADDR_SPACE_BITS 36
1696#define TARGET_VIRT_ADDR_SPACE_BITS 32
1697#endif
1698
1699
1700
1701# if defined(TARGET_X86_64)
1702# define TCG_PHYS_ADDR_BITS 40
1703# else
1704# define TCG_PHYS_ADDR_BITS 36
1705# endif
1706
1707#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
1708
1709#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
1710#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
1711#define CPU_RESOLVING_TYPE TYPE_X86_CPU
1712
1713#ifdef TARGET_X86_64
1714#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
1715#else
1716#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
1717#endif
1718
1719#define cpu_signal_handler cpu_x86_signal_handler
1720#define cpu_list x86_cpu_list
1721
1722
1723#define MMU_MODE0_SUFFIX _ksmap
1724#define MMU_MODE1_SUFFIX _user
1725#define MMU_MODE2_SUFFIX _knosmap
1726#define MMU_KSMAP_IDX 0
1727#define MMU_USER_IDX 1
1728#define MMU_KNOSMAP_IDX 2
1729static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
1730{
1731 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
1732 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
1733 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1734}
1735
1736static inline int cpu_mmu_index_kernel(CPUX86State *env)
1737{
1738 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX :
1739 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK))
1740 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1741}
1742
1743#define CC_DST (env->cc_dst)
1744#define CC_SRC (env->cc_src)
1745#define CC_SRC2 (env->cc_src2)
1746#define CC_OP (env->cc_op)
1747
1748
1749static inline target_long lshift(target_long x, int n)
1750{
1751 if (n >= 0) {
1752 return x << n;
1753 } else {
1754 return x >> (-n);
1755 }
1756}
1757
1758
1759#define FT0 (env->ft0)
1760#define ST0 (env->fpregs[env->fpstt].d)
1761#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
1762#define ST1 ST(1)
1763
1764
1765void tcg_x86_init(void);
1766
1767#include "exec/cpu-all.h"
1768#include "svm.h"
1769
1770#if !defined(CONFIG_USER_ONLY)
1771#include "hw/i386/apic.h"
1772#endif
1773
1774static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
1775 target_ulong *cs_base, uint32_t *flags)
1776{
1777 *cs_base = env->segs[R_CS].base;
1778 *pc = *cs_base + env->eip;
1779 *flags = env->hflags |
1780 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
1781}
1782
1783void do_cpu_init(X86CPU *cpu);
1784void do_cpu_sipi(X86CPU *cpu);
1785
1786#define MCE_INJECT_BROADCAST 1
1787#define MCE_INJECT_UNCOND_AO 2
1788
1789void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
1790 uint64_t status, uint64_t mcg_status, uint64_t addr,
1791 uint64_t misc, int flags);
1792
1793
1794void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
1795void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
1796 uintptr_t retaddr);
1797void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
1798 int error_code);
1799void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
1800 int error_code, uintptr_t retaddr);
1801void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
1802 int error_code, int next_eip_addend);
1803
1804
1805extern const uint8_t parity_table[256];
1806uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
1807
1808static inline uint32_t cpu_compute_eflags(CPUX86State *env)
1809{
1810 uint32_t eflags = env->eflags;
1811 if (tcg_enabled()) {
1812 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK);
1813 }
1814 return eflags;
1815}
1816
1817
1818
1819
1820static inline void cpu_load_eflags(CPUX86State *env, int eflags,
1821 int update_mask)
1822{
1823 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1824 CC_OP = CC_OP_EFLAGS;
1825 env->df = 1 - (2 * ((eflags >> 10) & 1));
1826 env->eflags = (env->eflags & ~update_mask) |
1827 (eflags & update_mask) | 0x2;
1828}
1829
1830
1831
1832static inline void cpu_load_efer(CPUX86State *env, uint64_t val)
1833{
1834 env->efer = val;
1835 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
1836 if (env->efer & MSR_EFER_LMA) {
1837 env->hflags |= HF_LMA_MASK;
1838 }
1839 if (env->efer & MSR_EFER_SVME) {
1840 env->hflags |= HF_SVME_MASK;
1841 }
1842}
1843
1844static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
1845{
1846 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
1847}
1848
1849static inline int32_t x86_get_a20_mask(CPUX86State *env)
1850{
1851 if (env->hflags & HF_SMM_MASK) {
1852 return -1;
1853 } else {
1854 return env->a20_mask;
1855 }
1856}
1857
1858
1859void update_fp_status(CPUX86State *env);
1860void update_mxcsr_status(CPUX86State *env);
1861
1862static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
1863{
1864 env->mxcsr = mxcsr;
1865 if (tcg_enabled()) {
1866 update_mxcsr_status(env);
1867 }
1868}
1869
1870static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc)
1871{
1872 env->fpuc = fpuc;
1873 if (tcg_enabled()) {
1874 update_fp_status(env);
1875 }
1876}
1877
1878
1879void helper_lock_init(void);
1880
1881
1882void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
1883 uint64_t param, uintptr_t retaddr);
1884void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code,
1885 uint64_t exit_info_1, uintptr_t retaddr);
1886void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1);
1887
1888
1889void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
1890
1891
1892void do_smm_enter(X86CPU *cpu);
1893
1894
1895void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
1896void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
1897 TPRAccess access);
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908void x86_cpu_change_kvm_default(const char *prop, const char *value);
1909
1910
1911const char *get_register_name_32(unsigned int reg);
1912
1913void enable_compat_apic_id_mode(void);
1914
1915#define APIC_DEFAULT_ADDRESS 0xfee00000
1916#define APIC_SPACE_SIZE 0x100000
1917
1918void x86_cpu_dump_local_apic_state(CPUState *cs, FILE *f,
1919 fprintf_function cpu_fprintf, int flags);
1920
1921
1922bool cpu_is_bsp(X86CPU *cpu);
1923
1924void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf);
1925void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf);
1926void x86_update_hflags(CPUX86State* env);
1927
1928#endif
1929