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25#include "qemu/osdep.h"
26#include <getopt.h>
27
28#include "libqtest.h"
29#include "libqos/libqos-pc.h"
30#include "libqos/ahci.h"
31#include "libqos/pci-pc.h"
32
33#include "qemu-common.h"
34#include "qapi/qmp/qdict.h"
35#include "qemu/host-utils.h"
36
37#include "hw/pci/pci_ids.h"
38#include "hw/pci/pci_regs.h"
39
40
41#define qmp_discard_response(...) qobject_unref(qmp(__VA_ARGS__))
42
43
44#define TEST_IMAGE_SIZE_MB_LARGE (200 * 1024)
45#define TEST_IMAGE_SIZE_MB_SMALL 64
46
47
48static char tmp_path[] = "/tmp/qtest.XXXXXX";
49static char debug_path[] = "/tmp/qtest-blkdebug.XXXXXX";
50static char mig_socket[] = "/tmp/qtest-migration.XXXXXX";
51static bool ahci_pedantic;
52static const char *imgfmt;
53static unsigned test_image_size_mb;
54
55
56static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port);
57static void ahci_test_pci_spec(AHCIQState *ahci);
58static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
59 uint8_t offset);
60static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset);
61static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset);
62static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset);
63
64
65
66static uint64_t mb_to_sectors(uint64_t image_size_mb)
67{
68 return (image_size_mb * 1024 * 1024) / AHCI_SECTOR_SIZE;
69}
70
71static void string_bswap16(uint16_t *s, size_t bytes)
72{
73 g_assert_cmphex((bytes & 1), ==, 0);
74 bytes /= 2;
75
76 while (bytes--) {
77 *s = bswap16(*s);
78 s++;
79 }
80}
81
82
83
84
85static void verify_state(AHCIQState *ahci, uint64_t hba_old)
86{
87 int i, j;
88 uint32_t ahci_fingerprint;
89 uint64_t hba_base;
90 AHCICommandHeader cmd;
91
92 ahci_fingerprint = qpci_config_readl(ahci->dev, PCI_VENDOR_ID);
93 g_assert_cmphex(ahci_fingerprint, ==, ahci->fingerprint);
94
95
96 if (!ahci->enabled) {
97 return;
98 }
99
100 hba_base = (uint64_t)qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
101 g_assert_cmphex(hba_base, ==, hba_old);
102
103 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP), ==, ahci->cap);
104 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP2), ==, ahci->cap2);
105
106 for (i = 0; i < 32; i++) {
107 g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_FB), ==,
108 ahci->port[i].fb);
109 g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_CLB), ==,
110 ahci->port[i].clb);
111 for (j = 0; j < 32; j++) {
112 ahci_get_command_header(ahci, i, j, &cmd);
113 g_assert_cmphex(cmd.prdtl, ==, ahci->port[i].prdtl[j]);
114 g_assert_cmphex(cmd.ctba, ==, ahci->port[i].ctba[j]);
115 }
116 }
117}
118
119static void ahci_migrate(AHCIQState *from, AHCIQState *to, const char *uri)
120{
121 QOSState *tmp = to->parent;
122 QPCIDevice *dev = to->dev;
123 char *uri_local = NULL;
124 uint64_t hba_old;
125
126 if (uri == NULL) {
127 uri_local = g_strdup_printf("%s%s", "unix:", mig_socket);
128 uri = uri_local;
129 }
130
131 hba_old = (uint64_t)qpci_config_readl(from->dev, PCI_BASE_ADDRESS_5);
132
133
134 migrate(from->parent, to->parent, uri);
135
136
137
138
139 memcpy(to, from, sizeof(AHCIQState));
140 to->parent = tmp;
141 to->dev = dev;
142
143 tmp = from->parent;
144 dev = from->dev;
145 memset(from, 0x00, sizeof(AHCIQState));
146 from->parent = tmp;
147 from->dev = dev;
148
149 verify_state(to, hba_old);
150 g_free(uri_local);
151}
152
153
154
155
156
157
158static AHCIQState *ahci_vboot(const char *cli, va_list ap)
159{
160 AHCIQState *s;
161
162 s = g_new0(AHCIQState, 1);
163 s->parent = qtest_pc_vboot(cli, ap);
164 global_qtest = s->parent->qts;
165 alloc_set_flags(s->parent->alloc, ALLOC_LEAK_ASSERT);
166
167
168 s->dev = get_ahci_device(s->parent->qts, &s->fingerprint);
169
170 return s;
171}
172
173
174
175
176static AHCIQState *ahci_boot(const char *cli, ...)
177{
178 AHCIQState *s;
179 va_list ap;
180
181 if (cli) {
182 va_start(ap, cli);
183 s = ahci_vboot(cli, ap);
184 va_end(ap);
185 } else {
186 cli = "-drive if=none,id=drive0,file=%s,cache=writeback,format=%s"
187 " -M q35 "
188 "-device ide-hd,drive=drive0 "
189 "-global ide-hd.serial=%s "
190 "-global ide-hd.ver=%s";
191 s = ahci_boot(cli, tmp_path, imgfmt, "testdisk", "version");
192 }
193
194 return s;
195}
196
197
198
199
200static void ahci_shutdown(AHCIQState *ahci)
201{
202 QOSState *qs = ahci->parent;
203
204 set_context(qs);
205 ahci_clean_mem(ahci);
206 free_ahci_device(ahci->dev);
207 g_free(ahci);
208 qtest_shutdown(qs);
209}
210
211
212
213
214
215static AHCIQState *ahci_boot_and_enable(const char *cli, ...)
216{
217 AHCIQState *ahci;
218 va_list ap;
219 uint16_t buff[256];
220 uint8_t port;
221 uint8_t hello;
222
223 if (cli) {
224 va_start(ap, cli);
225 ahci = ahci_vboot(cli, ap);
226 va_end(ap);
227 } else {
228 ahci = ahci_boot(NULL);
229 }
230
231 ahci_pci_enable(ahci);
232 ahci_hba_enable(ahci);
233
234 port = ahci_port_select(ahci);
235 ahci_port_clear(ahci, port);
236 if (is_atapi(ahci, port)) {
237 hello = CMD_PACKET_ID;
238 } else {
239 hello = CMD_IDENTIFY;
240 }
241 ahci_io(ahci, port, hello, &buff, sizeof(buff), 0);
242
243 return ahci;
244}
245
246
247
248
249
250
251static void ahci_test_pci_spec(AHCIQState *ahci)
252{
253 uint8_t datab;
254 uint16_t data;
255 uint32_t datal;
256
257
258 data = qpci_config_readw(ahci->dev, PCI_COMMAND);
259 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MEMORY);
260 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MASTER);
261 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SPECIAL);
262 ASSERT_BIT_CLEAR(data, PCI_COMMAND_VGA_PALETTE);
263 ASSERT_BIT_CLEAR(data, PCI_COMMAND_PARITY);
264 ASSERT_BIT_CLEAR(data, PCI_COMMAND_WAIT);
265 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SERR);
266 ASSERT_BIT_CLEAR(data, PCI_COMMAND_FAST_BACK);
267 ASSERT_BIT_CLEAR(data, PCI_COMMAND_INTX_DISABLE);
268 ASSERT_BIT_CLEAR(data, 0xF800);
269
270 data = qpci_config_readw(ahci->dev, PCI_STATUS);
271 ASSERT_BIT_CLEAR(data, 0x01 | 0x02 | 0x04);
272 ASSERT_BIT_CLEAR(data, PCI_STATUS_INTERRUPT);
273 ASSERT_BIT_SET(data, PCI_STATUS_CAP_LIST);
274 ASSERT_BIT_CLEAR(data, PCI_STATUS_UDF);
275 ASSERT_BIT_CLEAR(data, PCI_STATUS_PARITY);
276 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_TARGET_ABORT);
277 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_TARGET_ABORT);
278 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_MASTER_ABORT);
279 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_SYSTEM_ERROR);
280 ASSERT_BIT_CLEAR(data, PCI_STATUS_DETECTED_PARITY);
281
282
283 datal = qpci_config_readl(ahci->dev, PCI_CLASS_REVISION);
284 if (ahci_pedantic) {
285
286
287 ASSERT_BIT_CLEAR(datal, 0xFF);
288 }
289
290
291 g_assert_cmphex(PCI_BCC(datal), ==, 0x01);
292 if (PCI_SCC(datal) == 0x01) {
293
294 ASSERT_BIT_SET(0x80000000, datal);
295 ASSERT_BIT_CLEAR(0x60000000, datal);
296 } else if (PCI_SCC(datal) == 0x04) {
297
298 g_assert_cmphex(PCI_PI(datal), ==, 0);
299 } else if (PCI_SCC(datal) == 0x06) {
300
301 g_assert_cmphex(PCI_PI(datal), ==, 0x01);
302 } else {
303 g_assert_not_reached();
304 }
305
306 datab = qpci_config_readb(ahci->dev, PCI_CACHE_LINE_SIZE);
307 g_assert_cmphex(datab, ==, 0);
308
309 datab = qpci_config_readb(ahci->dev, PCI_LATENCY_TIMER);
310 g_assert_cmphex(datab, ==, 0);
311
312
313 datab = qpci_config_readb(ahci->dev, PCI_HEADER_TYPE);
314 ASSERT_BIT_CLEAR(datab, 0x7F);
315
316
317 datab = qpci_config_readb(ahci->dev, PCI_BIST);
318 ASSERT_BIT_CLEAR(datab, 0x7F);
319
320
321 datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
322 g_assert_cmphex(datal, ==, 0);
323
324 qpci_config_writel(ahci->dev, PCI_BASE_ADDRESS_5, 0xFFFFFFFF);
325 datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
326
327
328 ASSERT_BIT_CLEAR(datal, 0xFF);
329
330
331 datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST);
332
333 ASSERT_BIT_CLEAR(datal, ~0xFF);
334 g_assert_cmphex(datal, !=, 0);
335
336
337 data = qpci_config_readw(ahci->dev, datal);
338
339 switch (ahci->fingerprint) {
340 case AHCI_INTEL_ICH9:
341
342 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_MSI);
343 break;
344 default:
345
346 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_PM);
347 }
348
349 ahci_test_pci_caps(ahci, data, (uint8_t)datal);
350
351
352 datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST + 4);
353 g_assert_cmphex(datal, ==, 0);
354
355
356 datab = qpci_config_readb(ahci->dev, PCI_INTERRUPT_LINE);
357 g_assert_cmphex(datab, ==, 0);
358}
359
360
361
362
363static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
364 uint8_t offset)
365{
366 uint8_t cid = header & 0xFF;
367 uint8_t next = header >> 8;
368
369 g_test_message("CID: %02x; next: %02x", cid, next);
370
371 switch (cid) {
372 case PCI_CAP_ID_PM:
373 ahci_test_pmcap(ahci, offset);
374 break;
375 case PCI_CAP_ID_MSI:
376 ahci_test_msicap(ahci, offset);
377 break;
378 case PCI_CAP_ID_SATA:
379 ahci_test_satacap(ahci, offset);
380 break;
381
382 default:
383 g_test_message("Unknown CAP 0x%02x", cid);
384 }
385
386 if (next) {
387 ahci_test_pci_caps(ahci, qpci_config_readw(ahci->dev, next), next);
388 }
389}
390
391
392
393
394static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset)
395{
396 uint16_t dataw;
397 uint32_t datal;
398
399 g_test_message("Verifying SATACAP");
400
401
402 dataw = qpci_config_readw(ahci->dev, offset + 2);
403 g_assert_cmphex(dataw, ==, 0x10);
404
405
406 datal = qpci_config_readw(ahci->dev, offset + 4);
407
408 switch (datal & 0x0F) {
409 case 0x04:
410 case 0x05:
411 case 0x06:
412 case 0x07:
413 case 0x08:
414 case 0x09:
415 case 0x0F:
416 break;
417 default:
418
419 g_assert_not_reached();
420 }
421
422
423 g_assert_cmphex((datal >> 24), ==, 0x00);
424}
425
426
427
428
429static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset)
430{
431 uint16_t dataw;
432 uint32_t datal;
433
434 g_test_message("Verifying MSICAP");
435
436 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_FLAGS);
437 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_ENABLE);
438 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_QSIZE);
439 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_RESERVED);
440
441 datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_LO);
442 g_assert_cmphex(datal, ==, 0);
443
444 if (dataw & PCI_MSI_FLAGS_64BIT) {
445 g_test_message("MSICAP is 64bit");
446 datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_HI);
447 g_assert_cmphex(datal, ==, 0);
448 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_64);
449 g_assert_cmphex(dataw, ==, 0);
450 } else {
451 g_test_message("MSICAP is 32bit");
452 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_32);
453 g_assert_cmphex(dataw, ==, 0);
454 }
455}
456
457
458
459
460static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset)
461{
462 uint16_t dataw;
463
464 g_test_message("Verifying PMCAP");
465
466 dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_PMC);
467 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_PME_CLOCK);
468 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_RESERVED);
469 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D1);
470 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D2);
471
472 dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_CTRL);
473 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_STATE_MASK);
474 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_RESERVED);
475 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SEL_MASK);
476 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SCALE_MASK);
477}
478
479static void ahci_test_hba_spec(AHCIQState *ahci)
480{
481 unsigned i;
482 uint32_t reg;
483 uint32_t ports;
484 uint8_t nports_impl;
485 uint8_t maxports;
486
487 g_assert(ahci != NULL);
488
489
490
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496
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508
509
510 ahci->cap = ahci_rreg(ahci, AHCI_CAP);
511 ASSERT_BIT_CLEAR(ahci->cap, AHCI_CAP_RESERVED);
512
513
514 reg = ahci_rreg(ahci, AHCI_GHC);
515 ASSERT_BIT_CLEAR(reg, AHCI_GHC_HR);
516 ASSERT_BIT_CLEAR(reg, AHCI_GHC_IE);
517 ASSERT_BIT_CLEAR(reg, AHCI_GHC_MRSM);
518 if (BITSET(ahci->cap, AHCI_CAP_SAM)) {
519 g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
520 ASSERT_BIT_SET(reg, AHCI_GHC_AE);
521 } else {
522 g_test_message("Supports AHCI/Legacy mix.");
523 ASSERT_BIT_CLEAR(reg, AHCI_GHC_AE);
524 }
525
526
527 reg = ahci_rreg(ahci, AHCI_IS);
528 g_assert_cmphex(reg, ==, 0);
529
530
531 ports = ahci_rreg(ahci, AHCI_PI);
532
533 g_assert_cmphex(ports, !=, 0);
534
535 nports_impl = ctpopl(ports);
536 g_assert_cmpuint(((AHCI_CAP_NP & ahci->cap) + 1), >=, nports_impl);
537
538
539
540
541 g_assert_cmphex(ahci->barsize, >, 0);
542 maxports = (ahci->barsize - HBA_DATA_REGION_SIZE) / HBA_PORT_DATA_SIZE;
543
544 g_assert_cmphex((reg >> maxports), ==, 0);
545
546
547 reg = ahci_rreg(ahci, AHCI_VS);
548 switch (reg) {
549 case AHCI_VERSION_0_95:
550 case AHCI_VERSION_1_0:
551 case AHCI_VERSION_1_1:
552 case AHCI_VERSION_1_2:
553 case AHCI_VERSION_1_3:
554 break;
555 default:
556 g_assert_not_reached();
557 }
558
559
560 reg = ahci_rreg(ahci, AHCI_CCCCTL);
561 if (BITSET(ahci->cap, AHCI_CAP_CCCS)) {
562 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_EN);
563 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_RESERVED);
564 ASSERT_BIT_SET(reg, AHCI_CCCCTL_CC);
565 ASSERT_BIT_SET(reg, AHCI_CCCCTL_TV);
566 } else {
567 g_assert_cmphex(reg, ==, 0);
568 }
569
570
571 reg = ahci_rreg(ahci, AHCI_CCCPORTS);
572
573 g_assert_cmphex(reg, ==, 0);
574
575
576 reg = ahci_rreg(ahci, AHCI_EMLOC);
577 if (BITCLR(ahci->cap, AHCI_CAP_EMS)) {
578 g_assert_cmphex(reg, ==, 0);
579 }
580
581
582 reg = ahci_rreg(ahci, AHCI_EMCTL);
583 if (BITSET(ahci->cap, AHCI_CAP_EMS)) {
584 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_STSMR);
585 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLTM);
586 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLRST);
587 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_RESERVED);
588 } else {
589 g_assert_cmphex(reg, ==, 0);
590 }
591
592
593 ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2);
594 ASSERT_BIT_CLEAR(ahci->cap2, AHCI_CAP2_RESERVED);
595
596
597 reg = ahci_rreg(ahci, AHCI_BOHC);
598 g_assert_cmphex(reg, ==, 0);
599
600
601 g_test_message("Verifying HBA reserved area is empty.");
602 for (i = AHCI_RESERVED; i < AHCI_NVMHCI; ++i) {
603 reg = ahci_rreg(ahci, i);
604 g_assert_cmphex(reg, ==, 0);
605 }
606
607
608 if (BITCLR(ahci->cap2, AHCI_CAP2_NVMP)) {
609 g_test_message("Verifying HBA/NVMHCI area is empty.");
610 for (i = AHCI_NVMHCI; i < AHCI_VENDOR; ++i) {
611 reg = ahci_rreg(ahci, i);
612 g_assert_cmphex(reg, ==, 0);
613 }
614 }
615
616
617 g_test_message("Verifying HBA/Vendor area is empty.");
618 for (i = AHCI_VENDOR; i < AHCI_PORTS; ++i) {
619 reg = ahci_rreg(ahci, i);
620 g_assert_cmphex(reg, ==, 0);
621 }
622
623
624 for (i = 0; ports || (i < maxports); ports >>= 1, ++i) {
625 if (BITSET(ports, 0x1)) {
626 g_test_message("Testing port %u for spec", i);
627 ahci_test_port_spec(ahci, i);
628 } else {
629 uint16_t j;
630 uint16_t low = AHCI_PORTS + (32 * i);
631 uint16_t high = AHCI_PORTS + (32 * (i + 1));
632 g_test_message("Asserting unimplemented port %u "
633 "(reg [%u-%u]) is empty.",
634 i, low, high - 1);
635 for (j = low; j < high; ++j) {
636 reg = ahci_rreg(ahci, j);
637 g_assert_cmphex(reg, ==, 0);
638 }
639 }
640 }
641}
642
643
644
645
646static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port)
647{
648 uint32_t reg;
649 unsigned i;
650
651
652 reg = ahci_px_rreg(ahci, port, AHCI_PX_CLB);
653 ASSERT_BIT_CLEAR(reg, AHCI_PX_CLB_RESERVED);
654
655
656 if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
657 reg = ahci_px_rreg(ahci, port, AHCI_PX_CLBU);
658 g_assert_cmphex(reg, ==, 0);
659 }
660
661
662 reg = ahci_px_rreg(ahci, port, AHCI_PX_FB);
663 ASSERT_BIT_CLEAR(reg, AHCI_PX_FB_RESERVED);
664
665
666 if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
667 reg = ahci_px_rreg(ahci, port, AHCI_PX_FBU);
668 g_assert_cmphex(reg, ==, 0);
669 }
670
671
672 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
673 g_assert_cmphex(reg, ==, 0);
674
675
676 reg = ahci_px_rreg(ahci, port, AHCI_PX_IE);
677 g_assert_cmphex(reg, ==, 0);
678
679
680 reg = ahci_px_rreg(ahci, port, AHCI_PX_CMD);
681 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FRE);
682 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_RESERVED);
683 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CCS);
684 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
685 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
686 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_PMA);
687 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_APSTE);
688 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ATAPI);
689 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_DLAE);
690 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ALPE);
691 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ASP);
692 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ICC);
693
694 if (BITCLR(reg, AHCI_PX_CMD_CPD)) {
695 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CPS);
696 }
697
698 if (BITCLR(reg, AHCI_PX_CMD_MPSP)) {
699 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
700 }
701
702 if (BITCLR(ahci->cap, AHCI_CAP_SMPS)) {
703 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
704 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSP);
705 }
706
707 if (BITANY(reg, AHCI_PX_CMD_CPD | AHCI_PX_CMD_MPSP)) {
708 ASSERT_BIT_SET(reg, AHCI_PX_CMD_HPCP);
709 }
710
711 g_assert(!BITSET(reg, AHCI_PX_CMD_HPCP | AHCI_PX_CMD_ESP));
712
713 if (BITCLR(ahci->cap, AHCI_CAP_FBSS)) {
714 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FBSCP);
715 }
716
717
718 reg = ahci_px_rreg(ahci, port, AHCI_PX_RES1);
719 g_assert_cmphex(reg, ==, 0);
720
721
722 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
723
724
725 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR);
726 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS1);
727 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_DRQ);
728 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS2);
729 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY);
730 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
731 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_RESERVED);
732
733
734
735
736
737
738
739
740 reg = ahci_px_rreg(ahci, port, AHCI_PX_SSTS);
741 ASSERT_BIT_CLEAR(reg, AHCI_PX_SSTS_RESERVED);
742
743
744
745
746 reg = ahci_px_rreg(ahci, port, AHCI_PX_SCTL);
747 g_assert_cmphex(reg, ==, 0);
748
749
750 reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR);
751 g_assert_cmphex(reg, ==, 0);
752
753
754 reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT);
755 g_assert_cmphex(reg, ==, 0);
756
757
758 reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
759 g_assert_cmphex(reg, ==, 0);
760
761
762 reg = ahci_px_rreg(ahci, port, AHCI_PX_SNTF);
763 g_assert_cmphex(reg, ==, 0);
764
765
766 reg = ahci_px_rreg(ahci, port, AHCI_PX_FBS);
767 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_EN);
768 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEC);
769 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_SDE);
770 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEV);
771 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DWE);
772 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_RESERVED);
773 if (BITSET(ahci->cap, AHCI_CAP_FBSS)) {
774
775 g_assert((reg & AHCI_PX_FBS_ADO) >> ctzl(AHCI_PX_FBS_ADO) >= 2);
776 }
777
778
779 for (i = AHCI_PX_RES2; i < AHCI_PX_VS; ++i) {
780 reg = ahci_px_rreg(ahci, port, i);
781 g_assert_cmphex(reg, ==, 0);
782 }
783
784
785 for (i = AHCI_PX_VS; i < 32; ++i) {
786 reg = ahci_px_rreg(ahci, port, i);
787 if (reg) {
788 g_test_message("INFO: Vendor register %u non-empty", i);
789 }
790 }
791}
792
793
794
795
796
797static void ahci_test_identify(AHCIQState *ahci)
798{
799 uint16_t buff[256];
800 unsigned px;
801 int rc;
802 uint16_t sect_size;
803 const size_t buffsize = 512;
804
805 g_assert(ahci != NULL);
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829 px = ahci_port_select(ahci);
830 g_test_message("Selected port %u for test", px);
831
832
833 ahci_port_clear(ahci, px);
834
835
836 ahci_io(ahci, px, CMD_IDENTIFY, &buff, buffsize, 0);
837
838
839
840
841
842
843 string_bswap16(&buff[10], 20);
844 rc = memcmp(&buff[10], "testdisk ", 20);
845 g_assert_cmphex(rc, ==, 0);
846
847 string_bswap16(&buff[23], 8);
848 rc = memcmp(&buff[23], "version ", 8);
849 g_assert_cmphex(rc, ==, 0);
850
851 sect_size = le16_to_cpu(*((uint16_t *)(&buff[5])));
852 g_assert_cmphex(sect_size, ==, AHCI_SECTOR_SIZE);
853}
854
855static void ahci_test_io_rw_simple(AHCIQState *ahci, unsigned bufsize,
856 uint64_t sector, uint8_t read_cmd,
857 uint8_t write_cmd)
858{
859 uint64_t ptr;
860 uint8_t port;
861 unsigned char *tx = g_malloc(bufsize);
862 unsigned char *rx = g_malloc0(bufsize);
863
864 g_assert(ahci != NULL);
865
866
867 port = ahci_port_select(ahci);
868 ahci_port_clear(ahci, port);
869
870
871
872 ptr = ahci_alloc(ahci, bufsize);
873 g_assert(ptr);
874
875
876 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
877 bufwrite(ptr, tx, bufsize);
878
879
880 ahci_guest_io(ahci, port, write_cmd, ptr, bufsize, sector);
881 qmemset(ptr, 0x00, bufsize);
882 ahci_guest_io(ahci, port, read_cmd, ptr, bufsize, sector);
883
884
885 bufread(ptr, rx, bufsize);
886 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
887
888 ahci_free(ahci, ptr);
889 g_free(tx);
890 g_free(rx);
891}
892
893static uint8_t ahci_test_nondata(AHCIQState *ahci, uint8_t ide_cmd)
894{
895 uint8_t port;
896
897
898 port = ahci_port_select(ahci);
899 ahci_port_clear(ahci, port);
900
901 ahci_io(ahci, port, ide_cmd, NULL, 0, 0);
902
903 return port;
904}
905
906static void ahci_test_flush(AHCIQState *ahci)
907{
908 ahci_test_nondata(ahci, CMD_FLUSH_CACHE);
909}
910
911static void ahci_test_max(AHCIQState *ahci)
912{
913 RegD2HFIS *d2h = g_malloc0(0x20);
914 uint64_t nsect;
915 uint8_t port;
916 uint8_t cmd;
917 uint64_t config_sect = mb_to_sectors(test_image_size_mb) - 1;
918
919 if (config_sect > 0xFFFFFF) {
920 cmd = CMD_READ_MAX_EXT;
921 } else {
922 cmd = CMD_READ_MAX;
923 }
924
925 port = ahci_test_nondata(ahci, cmd);
926 memread(ahci->port[port].fb + 0x40, d2h, 0x20);
927 nsect = (uint64_t)d2h->lba_hi[2] << 40 |
928 (uint64_t)d2h->lba_hi[1] << 32 |
929 (uint64_t)d2h->lba_hi[0] << 24 |
930 (uint64_t)d2h->lba_lo[2] << 16 |
931 (uint64_t)d2h->lba_lo[1] << 8 |
932 (uint64_t)d2h->lba_lo[0];
933
934 g_assert_cmphex(nsect, ==, config_sect);
935 g_free(d2h);
936}
937
938
939
940
941
942
943
944
945
946static void test_sanity(void)
947{
948 AHCIQState *ahci;
949 ahci = ahci_boot(NULL);
950 ahci_shutdown(ahci);
951}
952
953
954
955
956
957static void test_pci_spec(void)
958{
959 AHCIQState *ahci;
960 ahci = ahci_boot(NULL);
961 ahci_test_pci_spec(ahci);
962 ahci_shutdown(ahci);
963}
964
965
966
967
968
969static void test_pci_enable(void)
970{
971 AHCIQState *ahci;
972 ahci = ahci_boot(NULL);
973 ahci_pci_enable(ahci);
974 ahci_shutdown(ahci);
975}
976
977
978
979
980
981static void test_hba_spec(void)
982{
983 AHCIQState *ahci;
984
985 ahci = ahci_boot(NULL);
986 ahci_pci_enable(ahci);
987 ahci_test_hba_spec(ahci);
988 ahci_shutdown(ahci);
989}
990
991
992
993
994
995static void test_hba_enable(void)
996{
997 AHCIQState *ahci;
998
999 ahci = ahci_boot(NULL);
1000 ahci_pci_enable(ahci);
1001 ahci_hba_enable(ahci);
1002 ahci_shutdown(ahci);
1003}
1004
1005
1006
1007
1008
1009static void test_identify(void)
1010{
1011 AHCIQState *ahci;
1012
1013 ahci = ahci_boot_and_enable(NULL);
1014 ahci_test_identify(ahci);
1015 ahci_shutdown(ahci);
1016}
1017
1018
1019
1020
1021
1022
1023
1024static void test_dma_fragmented(void)
1025{
1026 AHCIQState *ahci;
1027 AHCICommand *cmd;
1028 uint8_t px;
1029 size_t bufsize = 4096;
1030 unsigned char *tx = g_malloc(bufsize);
1031 unsigned char *rx = g_malloc0(bufsize);
1032 uint64_t ptr;
1033
1034 ahci = ahci_boot_and_enable(NULL);
1035 px = ahci_port_select(ahci);
1036 ahci_port_clear(ahci, px);
1037
1038
1039 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1040
1041
1042 ptr = guest_alloc(ahci->parent->alloc, bufsize);
1043 g_assert(ptr);
1044 bufwrite(ptr, tx, bufsize);
1045
1046 cmd = ahci_command_create(CMD_WRITE_DMA);
1047 ahci_command_adjust(cmd, 0, ptr, bufsize, 32);
1048 ahci_command_commit(ahci, cmd, px);
1049 ahci_command_issue(ahci, cmd);
1050 ahci_command_verify(ahci, cmd);
1051 ahci_command_free(cmd);
1052
1053 cmd = ahci_command_create(CMD_READ_DMA);
1054 ahci_command_adjust(cmd, 0, ptr, bufsize, 32);
1055 ahci_command_commit(ahci, cmd, px);
1056 ahci_command_issue(ahci, cmd);
1057 ahci_command_verify(ahci, cmd);
1058 ahci_command_free(cmd);
1059
1060
1061 bufread(ptr, rx, bufsize);
1062 guest_free(ahci->parent->alloc, ptr);
1063
1064 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1065
1066 ahci_shutdown(ahci);
1067
1068 g_free(rx);
1069 g_free(tx);
1070}
1071
1072
1073
1074
1075
1076static void make_dirty(AHCIQState* ahci, uint8_t port)
1077{
1078 uint64_t ptr;
1079 unsigned bufsize = 512;
1080
1081 ptr = ahci_alloc(ahci, bufsize);
1082 g_assert(ptr);
1083
1084 ahci_guest_io(ahci, port, CMD_WRITE_DMA, ptr, bufsize, 1);
1085 ahci_free(ahci, ptr);
1086}
1087
1088static void test_flush(void)
1089{
1090 AHCIQState *ahci;
1091 uint8_t port;
1092
1093 ahci = ahci_boot_and_enable(NULL);
1094
1095 port = ahci_port_select(ahci);
1096 ahci_port_clear(ahci, port);
1097
1098 make_dirty(ahci, port);
1099
1100 ahci_test_flush(ahci);
1101 ahci_shutdown(ahci);
1102}
1103
1104static void test_flush_retry(void)
1105{
1106 AHCIQState *ahci;
1107 AHCICommand *cmd;
1108 uint8_t port;
1109
1110 prepare_blkdebug_script(debug_path, "flush_to_disk");
1111 ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1112 "format=%s,cache=writeback,"
1113 "rerror=stop,werror=stop "
1114 "-M q35 "
1115 "-device ide-hd,drive=drive0 ",
1116 debug_path,
1117 tmp_path, imgfmt);
1118
1119 port = ahci_port_select(ahci);
1120 ahci_port_clear(ahci, port);
1121
1122
1123 make_dirty(ahci, port);
1124
1125
1126 cmd = ahci_guest_io_halt(ahci, port, CMD_FLUSH_CACHE, 0, 0, 0);
1127 ahci_guest_io_resume(ahci, cmd);
1128
1129 ahci_shutdown(ahci);
1130}
1131
1132
1133
1134
1135static void test_migrate_sanity(void)
1136{
1137 AHCIQState *src, *dst;
1138 char *uri = g_strdup_printf("unix:%s", mig_socket);
1139
1140 src = ahci_boot("-m 384 -M q35 "
1141 "-drive if=ide,file=%s,format=%s ", tmp_path, imgfmt);
1142 dst = ahci_boot("-m 384 -M q35 "
1143 "-drive if=ide,file=%s,format=%s "
1144 "-incoming %s", tmp_path, imgfmt, uri);
1145
1146 ahci_migrate(src, dst, uri);
1147
1148 ahci_shutdown(src);
1149 ahci_shutdown(dst);
1150 g_free(uri);
1151}
1152
1153
1154
1155
1156static void ahci_migrate_simple(uint8_t cmd_read, uint8_t cmd_write)
1157{
1158 AHCIQState *src, *dst;
1159 uint8_t px;
1160 size_t bufsize = 4096;
1161 unsigned char *tx = g_malloc(bufsize);
1162 unsigned char *rx = g_malloc0(bufsize);
1163 char *uri = g_strdup_printf("unix:%s", mig_socket);
1164
1165 src = ahci_boot_and_enable("-m 384 -M q35 "
1166 "-drive if=ide,format=%s,file=%s ",
1167 imgfmt, tmp_path);
1168 dst = ahci_boot("-m 384 -M q35 "
1169 "-drive if=ide,format=%s,file=%s "
1170 "-incoming %s", imgfmt, tmp_path, uri);
1171
1172 set_context(src->parent);
1173
1174
1175 px = ahci_port_select(src);
1176 ahci_port_clear(src, px);
1177
1178
1179 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1180
1181
1182 ahci_io(src, px, cmd_write, tx, bufsize, 0);
1183 ahci_migrate(src, dst, uri);
1184 ahci_io(dst, px, cmd_read, rx, bufsize, 0);
1185
1186
1187 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1188
1189 ahci_shutdown(src);
1190 ahci_shutdown(dst);
1191 g_free(rx);
1192 g_free(tx);
1193 g_free(uri);
1194}
1195
1196static void test_migrate_dma(void)
1197{
1198 ahci_migrate_simple(CMD_READ_DMA, CMD_WRITE_DMA);
1199}
1200
1201static void test_migrate_ncq(void)
1202{
1203 ahci_migrate_simple(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1204}
1205
1206
1207
1208
1209
1210
1211
1212
1213static void ahci_halted_io_test(uint8_t cmd_read, uint8_t cmd_write)
1214{
1215 AHCIQState *ahci;
1216 uint8_t port;
1217 size_t bufsize = 4096;
1218 unsigned char *tx = g_malloc(bufsize);
1219 unsigned char *rx = g_malloc0(bufsize);
1220 uint64_t ptr;
1221 AHCICommand *cmd;
1222
1223 prepare_blkdebug_script(debug_path, "write_aio");
1224
1225 ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1226 "format=%s,cache=writeback,"
1227 "rerror=stop,werror=stop "
1228 "-M q35 "
1229 "-device ide-hd,drive=drive0 ",
1230 debug_path,
1231 tmp_path, imgfmt);
1232
1233
1234 port = ahci_port_select(ahci);
1235 ahci_port_clear(ahci, port);
1236
1237
1238 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1239 ptr = ahci_alloc(ahci, bufsize);
1240 g_assert(ptr);
1241 memwrite(ptr, tx, bufsize);
1242
1243
1244 cmd = ahci_guest_io_halt(ahci, port, cmd_write,
1245 ptr, bufsize, 0);
1246
1247
1248 ahci_guest_io_resume(ahci, cmd);
1249 ahci_free(ahci, ptr);
1250
1251
1252 ahci_io(ahci, port, cmd_read, rx, bufsize, 0);
1253 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1254
1255
1256 ahci_shutdown(ahci);
1257 g_free(rx);
1258 g_free(tx);
1259}
1260
1261static void test_halted_dma(void)
1262{
1263 ahci_halted_io_test(CMD_READ_DMA, CMD_WRITE_DMA);
1264}
1265
1266static void test_halted_ncq(void)
1267{
1268 ahci_halted_io_test(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1269}
1270
1271
1272
1273
1274
1275
1276
1277
1278static void ahci_migrate_halted_io(uint8_t cmd_read, uint8_t cmd_write)
1279{
1280 AHCIQState *src, *dst;
1281 uint8_t port;
1282 size_t bufsize = 4096;
1283 unsigned char *tx = g_malloc(bufsize);
1284 unsigned char *rx = g_malloc0(bufsize);
1285 uint64_t ptr;
1286 AHCICommand *cmd;
1287 char *uri = g_strdup_printf("unix:%s", mig_socket);
1288
1289 prepare_blkdebug_script(debug_path, "write_aio");
1290
1291 src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1292 "format=%s,cache=writeback,"
1293 "rerror=stop,werror=stop "
1294 "-M q35 "
1295 "-device ide-hd,drive=drive0 ",
1296 debug_path,
1297 tmp_path, imgfmt);
1298
1299 dst = ahci_boot("-drive file=%s,if=none,id=drive0,"
1300 "format=%s,cache=writeback,"
1301 "rerror=stop,werror=stop "
1302 "-M q35 "
1303 "-device ide-hd,drive=drive0 "
1304 "-incoming %s",
1305 tmp_path, imgfmt, uri);
1306
1307 set_context(src->parent);
1308
1309
1310 port = ahci_port_select(src);
1311 ahci_port_clear(src, port);
1312 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1313
1314
1315 ptr = ahci_alloc(src, bufsize);
1316 g_assert(ptr);
1317 memwrite(ptr, tx, bufsize);
1318
1319
1320 cmd = ahci_guest_io_halt(src, port, cmd_write,
1321 ptr, bufsize, 0);
1322 ahci_migrate(src, dst, uri);
1323 ahci_guest_io_resume(dst, cmd);
1324 ahci_free(dst, ptr);
1325
1326
1327 ahci_io(dst, port, cmd_read, rx, bufsize, 0);
1328
1329
1330 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1331
1332
1333 ahci_shutdown(src);
1334 ahci_shutdown(dst);
1335 g_free(rx);
1336 g_free(tx);
1337 g_free(uri);
1338}
1339
1340static void test_migrate_halted_dma(void)
1341{
1342 ahci_migrate_halted_io(CMD_READ_DMA, CMD_WRITE_DMA);
1343}
1344
1345static void test_migrate_halted_ncq(void)
1346{
1347 ahci_migrate_halted_io(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1348}
1349
1350
1351
1352
1353static void test_flush_migrate(void)
1354{
1355 AHCIQState *src, *dst;
1356 AHCICommand *cmd;
1357 uint8_t px;
1358 char *uri = g_strdup_printf("unix:%s", mig_socket);
1359
1360 prepare_blkdebug_script(debug_path, "flush_to_disk");
1361
1362 src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1363 "cache=writeback,rerror=stop,werror=stop,"
1364 "format=%s "
1365 "-M q35 "
1366 "-device ide-hd,drive=drive0 ",
1367 debug_path, tmp_path, imgfmt);
1368 dst = ahci_boot("-drive file=%s,if=none,id=drive0,"
1369 "cache=writeback,rerror=stop,werror=stop,"
1370 "format=%s "
1371 "-M q35 "
1372 "-device ide-hd,drive=drive0 "
1373 "-incoming %s", tmp_path, imgfmt, uri);
1374
1375 set_context(src->parent);
1376
1377 px = ahci_port_select(src);
1378 ahci_port_clear(src, px);
1379
1380
1381 make_dirty(src, px);
1382
1383
1384 cmd = ahci_command_create(CMD_FLUSH_CACHE);
1385 ahci_command_commit(src, cmd, px);
1386 ahci_command_issue_async(src, cmd);
1387 qmp_eventwait("STOP");
1388
1389
1390 ahci_migrate(src, dst, uri);
1391
1392
1393 qmp_send("{'execute':'cont' }");
1394 qmp_eventwait("RESUME");
1395 ahci_command_wait(dst, cmd);
1396 ahci_command_verify(dst, cmd);
1397
1398 ahci_command_free(cmd);
1399 ahci_shutdown(src);
1400 ahci_shutdown(dst);
1401 g_free(uri);
1402}
1403
1404static void test_max(void)
1405{
1406 AHCIQState *ahci;
1407
1408 ahci = ahci_boot_and_enable(NULL);
1409 ahci_test_max(ahci);
1410 ahci_shutdown(ahci);
1411}
1412
1413static void test_reset(void)
1414{
1415 AHCIQState *ahci;
1416 int i;
1417
1418 ahci = ahci_boot(NULL);
1419 ahci_test_pci_spec(ahci);
1420 ahci_pci_enable(ahci);
1421
1422 for (i = 0; i < 2; i++) {
1423 ahci_test_hba_spec(ahci);
1424 ahci_hba_enable(ahci);
1425 ahci_test_identify(ahci);
1426 ahci_test_io_rw_simple(ahci, 4096, 0,
1427 CMD_READ_DMA_EXT,
1428 CMD_WRITE_DMA_EXT);
1429 ahci_set(ahci, AHCI_GHC, AHCI_GHC_HR);
1430 ahci_clean_mem(ahci);
1431 }
1432
1433 ahci_shutdown(ahci);
1434}
1435
1436static void test_ncq_simple(void)
1437{
1438 AHCIQState *ahci;
1439
1440 ahci = ahci_boot_and_enable(NULL);
1441 ahci_test_io_rw_simple(ahci, 4096, 0,
1442 READ_FPDMA_QUEUED,
1443 WRITE_FPDMA_QUEUED);
1444 ahci_shutdown(ahci);
1445}
1446
1447static int prepare_iso(size_t size, unsigned char **buf, char **name)
1448{
1449 char cdrom_path[] = "/tmp/qtest.iso.XXXXXX";
1450 unsigned char *patt;
1451 ssize_t ret;
1452 int fd = mkstemp(cdrom_path);
1453
1454 g_assert(buf);
1455 g_assert(name);
1456 patt = g_malloc(size);
1457
1458
1459 generate_pattern(patt, size, ATAPI_SECTOR_SIZE);
1460 ret = write(fd, patt, size);
1461 g_assert(ret == size);
1462
1463 *name = g_strdup(cdrom_path);
1464 *buf = patt;
1465 return fd;
1466}
1467
1468static void remove_iso(int fd, char *name)
1469{
1470 unlink(name);
1471 g_free(name);
1472 close(fd);
1473}
1474
1475static int ahci_cb_cmp_buff(AHCIQState *ahci, AHCICommand *cmd,
1476 const AHCIOpts *opts)
1477{
1478 unsigned char *tx = opts->opaque;
1479 unsigned char *rx;
1480
1481 if (!opts->size) {
1482 return 0;
1483 }
1484
1485 rx = g_malloc0(opts->size);
1486 bufread(opts->buffer, rx, opts->size);
1487 g_assert_cmphex(memcmp(tx, rx, opts->size), ==, 0);
1488 g_free(rx);
1489
1490 return 0;
1491}
1492
1493static void ahci_test_cdrom(int nsectors, bool dma, uint8_t cmd,
1494 bool override_bcl, uint16_t bcl)
1495{
1496 AHCIQState *ahci;
1497 unsigned char *tx;
1498 char *iso;
1499 int fd;
1500 AHCIOpts opts = {
1501 .size = (ATAPI_SECTOR_SIZE * nsectors),
1502 .atapi = true,
1503 .atapi_dma = dma,
1504 .post_cb = ahci_cb_cmp_buff,
1505 .set_bcl = override_bcl,
1506 .bcl = bcl,
1507 };
1508 uint64_t iso_size = ATAPI_SECTOR_SIZE * (nsectors + 1);
1509
1510
1511 fd = prepare_iso(iso_size, &tx, &iso);
1512 opts.opaque = tx;
1513
1514
1515 ahci = ahci_boot_and_enable("-drive if=none,id=drive0,file=%s,format=raw "
1516 "-M q35 "
1517 "-device ide-cd,drive=drive0 ", iso);
1518
1519
1520 ahci_exec(ahci, ahci_port_select(ahci), cmd, &opts);
1521
1522
1523 g_free(tx);
1524 ahci_shutdown(ahci);
1525 remove_iso(fd, iso);
1526}
1527
1528static void ahci_test_cdrom_read10(int nsectors, bool dma)
1529{
1530 ahci_test_cdrom(nsectors, dma, CMD_ATAPI_READ_10, false, 0);
1531}
1532
1533static void test_cdrom_dma(void)
1534{
1535 ahci_test_cdrom_read10(1, true);
1536}
1537
1538static void test_cdrom_dma_multi(void)
1539{
1540 ahci_test_cdrom_read10(3, true);
1541}
1542
1543static void test_cdrom_pio(void)
1544{
1545 ahci_test_cdrom_read10(1, false);
1546}
1547
1548static void test_cdrom_pio_multi(void)
1549{
1550 ahci_test_cdrom_read10(3, false);
1551}
1552
1553
1554
1555static void test_atapi_bcl(void)
1556{
1557 ahci_test_cdrom(0, false, CMD_ATAPI_READ_CD, true, 0);
1558}
1559
1560
1561static void atapi_wait_tray(bool open)
1562{
1563 QDict *rsp = qmp_eventwait_ref("DEVICE_TRAY_MOVED");
1564 QDict *data = qdict_get_qdict(rsp, "data");
1565 if (open) {
1566 g_assert(qdict_get_bool(data, "tray-open"));
1567 } else {
1568 g_assert(!qdict_get_bool(data, "tray-open"));
1569 }
1570 qobject_unref(rsp);
1571}
1572
1573static void test_atapi_tray(void)
1574{
1575 AHCIQState *ahci;
1576 unsigned char *tx;
1577 char *iso;
1578 int fd;
1579 uint8_t port, sense, asc;
1580 uint64_t iso_size = ATAPI_SECTOR_SIZE;
1581 QDict *rsp;
1582
1583 fd = prepare_iso(iso_size, &tx, &iso);
1584 ahci = ahci_boot_and_enable("-blockdev node-name=drive0,driver=file,filename=%s "
1585 "-M q35 "
1586 "-device ide-cd,id=cd0,drive=drive0 ", iso);
1587 port = ahci_port_select(ahci);
1588
1589 ahci_atapi_eject(ahci, port);
1590 atapi_wait_tray(true);
1591
1592 ahci_atapi_load(ahci, port);
1593 atapi_wait_tray(false);
1594
1595
1596 qmp_send("{'execute': 'blockdev-open-tray',"
1597 " 'arguments': {'id': 'cd0'}}");
1598 atapi_wait_tray(true);
1599 rsp = qmp_receive();
1600 qobject_unref(rsp);
1601
1602 qmp_discard_response("{'execute': 'blockdev-remove-medium', "
1603 "'arguments': {'id': 'cd0'}}");
1604
1605
1606 ahci_atapi_load(ahci, port);
1607 atapi_wait_tray(false);
1608
1609 ahci_atapi_eject(ahci, port);
1610 atapi_wait_tray(true);
1611
1612
1613 qmp_discard_response("{'execute': 'blockdev-add', "
1614 "'arguments': {'node-name': 'node0', "
1615 "'driver': 'raw', "
1616 "'file': { 'driver': 'file', "
1617 "'filename': %s }}}", iso);
1618 qmp_discard_response("{'execute': 'blockdev-insert-medium',"
1619 "'arguments': { 'id': 'cd0', "
1620 "'node-name': 'node0' }}");
1621
1622
1623 qmp_send("{'execute': 'blockdev-close-tray',"
1624 " 'arguments': {'id': 'cd0'}}");
1625 atapi_wait_tray(false);
1626 rsp = qmp_receive();
1627 qobject_unref(rsp);
1628
1629
1630 ahci_atapi_test_ready(ahci, port, false, SENSE_NOT_READY);
1631 ahci_atapi_get_sense(ahci, port, &sense, &asc);
1632 g_assert_cmpuint(sense, ==, SENSE_NOT_READY);
1633 g_assert_cmpuint(asc, ==, ASC_MEDIUM_NOT_PRESENT);
1634
1635 ahci_atapi_test_ready(ahci, port, false, SENSE_UNIT_ATTENTION);
1636 ahci_atapi_get_sense(ahci, port, &sense, &asc);
1637 g_assert_cmpuint(sense, ==, SENSE_UNIT_ATTENTION);
1638 g_assert_cmpuint(asc, ==, ASC_MEDIUM_MAY_HAVE_CHANGED);
1639
1640 ahci_atapi_test_ready(ahci, port, true, SENSE_NO_SENSE);
1641 ahci_atapi_get_sense(ahci, port, &sense, &asc);
1642 g_assert_cmpuint(sense, ==, SENSE_NO_SENSE);
1643
1644
1645 ahci_atapi_eject(ahci, port);
1646 atapi_wait_tray(true);
1647
1648 ahci_atapi_load(ahci, port);
1649 atapi_wait_tray(false);
1650
1651
1652 g_free(tx);
1653 ahci_shutdown(ahci);
1654 remove_iso(fd, iso);
1655}
1656
1657
1658
1659
1660enum BuffLen {
1661 LEN_BEGIN = 0,
1662 LEN_SIMPLE = LEN_BEGIN,
1663 LEN_DOUBLE,
1664 LEN_LONG,
1665 LEN_SHORT,
1666 NUM_LENGTHS
1667};
1668
1669static const char *buff_len_str[NUM_LENGTHS] = { "simple", "double",
1670 "long", "short" };
1671
1672enum AddrMode {
1673 ADDR_MODE_BEGIN = 0,
1674 ADDR_MODE_LBA28 = ADDR_MODE_BEGIN,
1675 ADDR_MODE_LBA48,
1676 NUM_ADDR_MODES
1677};
1678
1679static const char *addr_mode_str[NUM_ADDR_MODES] = { "lba28", "lba48" };
1680
1681enum IOMode {
1682 MODE_BEGIN = 0,
1683 MODE_PIO = MODE_BEGIN,
1684 MODE_DMA,
1685 NUM_MODES
1686};
1687
1688static const char *io_mode_str[NUM_MODES] = { "pio", "dma" };
1689
1690enum IOOps {
1691 IO_BEGIN = 0,
1692 IO_READ = IO_BEGIN,
1693 IO_WRITE,
1694 NUM_IO_OPS
1695};
1696
1697enum OffsetType {
1698 OFFSET_BEGIN = 0,
1699 OFFSET_ZERO = OFFSET_BEGIN,
1700 OFFSET_LOW,
1701 OFFSET_HIGH,
1702 NUM_OFFSETS
1703};
1704
1705static const char *offset_str[NUM_OFFSETS] = { "zero", "low", "high" };
1706
1707typedef struct AHCIIOTestOptions {
1708 enum BuffLen length;
1709 enum AddrMode address_type;
1710 enum IOMode io_type;
1711 enum OffsetType offset;
1712} AHCIIOTestOptions;
1713
1714static uint64_t offset_sector(enum OffsetType ofst,
1715 enum AddrMode addr_type,
1716 uint64_t buffsize)
1717{
1718 uint64_t ceil;
1719 uint64_t nsectors;
1720
1721 switch (ofst) {
1722 case OFFSET_ZERO:
1723 return 0;
1724 case OFFSET_LOW:
1725 return 1;
1726 case OFFSET_HIGH:
1727 ceil = (addr_type == ADDR_MODE_LBA28) ? 0xfffffff : 0xffffffffffff;
1728 ceil = MIN(ceil, mb_to_sectors(test_image_size_mb) - 1);
1729 nsectors = buffsize / AHCI_SECTOR_SIZE;
1730 return ceil - nsectors + 1;
1731 default:
1732 g_assert_not_reached();
1733 }
1734}
1735
1736
1737
1738
1739static const uint8_t io_cmds[NUM_MODES][NUM_ADDR_MODES][NUM_IO_OPS] = {
1740 [MODE_PIO] = {
1741 [ADDR_MODE_LBA28] = {
1742 [IO_READ] = CMD_READ_PIO,
1743 [IO_WRITE] = CMD_WRITE_PIO },
1744 [ADDR_MODE_LBA48] = {
1745 [IO_READ] = CMD_READ_PIO_EXT,
1746 [IO_WRITE] = CMD_WRITE_PIO_EXT }
1747 },
1748 [MODE_DMA] = {
1749 [ADDR_MODE_LBA28] = {
1750 [IO_READ] = CMD_READ_DMA,
1751 [IO_WRITE] = CMD_WRITE_DMA },
1752 [ADDR_MODE_LBA48] = {
1753 [IO_READ] = CMD_READ_DMA_EXT,
1754 [IO_WRITE] = CMD_WRITE_DMA_EXT }
1755 }
1756};
1757
1758
1759
1760
1761
1762static void test_io_rw_interface(enum AddrMode lba48, enum IOMode dma,
1763 unsigned bufsize, uint64_t sector)
1764{
1765 AHCIQState *ahci;
1766
1767 ahci = ahci_boot_and_enable(NULL);
1768 ahci_test_io_rw_simple(ahci, bufsize, sector,
1769 io_cmds[dma][lba48][IO_READ],
1770 io_cmds[dma][lba48][IO_WRITE]);
1771 ahci_shutdown(ahci);
1772}
1773
1774
1775
1776
1777static void test_io_interface(gconstpointer opaque)
1778{
1779 AHCIIOTestOptions *opts = (AHCIIOTestOptions *)opaque;
1780 unsigned bufsize;
1781 uint64_t sector;
1782
1783 switch (opts->length) {
1784 case LEN_SIMPLE:
1785 bufsize = 4096;
1786 break;
1787 case LEN_DOUBLE:
1788 bufsize = 8192;
1789 break;
1790 case LEN_LONG:
1791 bufsize = 4096 * 64;
1792 break;
1793 case LEN_SHORT:
1794 bufsize = 512;
1795 break;
1796 default:
1797 g_assert_not_reached();
1798 }
1799
1800 sector = offset_sector(opts->offset, opts->address_type, bufsize);
1801 test_io_rw_interface(opts->address_type, opts->io_type, bufsize, sector);
1802 g_free(opts);
1803 return;
1804}
1805
1806static void create_ahci_io_test(enum IOMode type, enum AddrMode addr,
1807 enum BuffLen len, enum OffsetType offset)
1808{
1809 char *name;
1810 AHCIIOTestOptions *opts;
1811
1812 opts = g_new(AHCIIOTestOptions, 1);
1813 opts->length = len;
1814 opts->address_type = addr;
1815 opts->io_type = type;
1816 opts->offset = offset;
1817
1818 name = g_strdup_printf("ahci/io/%s/%s/%s/%s",
1819 io_mode_str[type],
1820 addr_mode_str[addr],
1821 buff_len_str[len],
1822 offset_str[offset]);
1823
1824 if ((addr == ADDR_MODE_LBA48) && (offset == OFFSET_HIGH) &&
1825 (mb_to_sectors(test_image_size_mb) <= 0xFFFFFFF)) {
1826 g_test_message("%s: skipped; test image too small", name);
1827 g_free(opts);
1828 g_free(name);
1829 return;
1830 }
1831
1832 qtest_add_data_func(name, opts, test_io_interface);
1833 g_free(name);
1834}
1835
1836
1837
1838int main(int argc, char **argv)
1839{
1840 const char *arch;
1841 int ret;
1842 int fd;
1843 int c;
1844 int i, j, k, m;
1845
1846 static struct option long_options[] = {
1847 {"pedantic", no_argument, 0, 'p' },
1848 {0, 0, 0, 0},
1849 };
1850
1851
1852 g_test_init(&argc, &argv, NULL);
1853
1854 while (1) {
1855 c = getopt_long(argc, argv, "", long_options, NULL);
1856 if (c == -1) {
1857 break;
1858 }
1859 switch (c) {
1860 case -1:
1861 break;
1862 case 'p':
1863 ahci_pedantic = 1;
1864 break;
1865 default:
1866 fprintf(stderr, "Unrecognized ahci_test option.\n");
1867 g_assert_not_reached();
1868 }
1869 }
1870
1871
1872 arch = qtest_get_arch();
1873 if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
1874 g_test_message("Skipping test for non-x86");
1875 return 0;
1876 }
1877
1878
1879 fd = mkstemp(tmp_path);
1880 g_assert(fd >= 0);
1881 if (have_qemu_img()) {
1882 imgfmt = "qcow2";
1883 test_image_size_mb = TEST_IMAGE_SIZE_MB_LARGE;
1884 mkqcow2(tmp_path, TEST_IMAGE_SIZE_MB_LARGE);
1885 } else {
1886 g_test_message("QTEST_QEMU_IMG not set or qemu-img missing; "
1887 "skipping LBA48 high-sector tests");
1888 imgfmt = "raw";
1889 test_image_size_mb = TEST_IMAGE_SIZE_MB_SMALL;
1890 ret = ftruncate(fd, test_image_size_mb * 1024 * 1024);
1891 g_assert(ret == 0);
1892 }
1893 close(fd);
1894
1895
1896 fd = mkstemp(debug_path);
1897 g_assert(fd >= 0);
1898 close(fd);
1899
1900
1901 fd = mkstemp(mig_socket);
1902 g_assert(fd >= 0);
1903 close(fd);
1904
1905
1906 qtest_add_func("/ahci/sanity", test_sanity);
1907 qtest_add_func("/ahci/pci_spec", test_pci_spec);
1908 qtest_add_func("/ahci/pci_enable", test_pci_enable);
1909 qtest_add_func("/ahci/hba_spec", test_hba_spec);
1910 qtest_add_func("/ahci/hba_enable", test_hba_enable);
1911 qtest_add_func("/ahci/identify", test_identify);
1912
1913 for (i = MODE_BEGIN; i < NUM_MODES; i++) {
1914 for (j = ADDR_MODE_BEGIN; j < NUM_ADDR_MODES; j++) {
1915 for (k = LEN_BEGIN; k < NUM_LENGTHS; k++) {
1916 for (m = OFFSET_BEGIN; m < NUM_OFFSETS; m++) {
1917 create_ahci_io_test(i, j, k, m);
1918 }
1919 }
1920 }
1921 }
1922
1923 qtest_add_func("/ahci/io/dma/lba28/fragmented", test_dma_fragmented);
1924
1925 qtest_add_func("/ahci/flush/simple", test_flush);
1926 qtest_add_func("/ahci/flush/retry", test_flush_retry);
1927 qtest_add_func("/ahci/flush/migrate", test_flush_migrate);
1928
1929 qtest_add_func("/ahci/migrate/sanity", test_migrate_sanity);
1930 qtest_add_func("/ahci/migrate/dma/simple", test_migrate_dma);
1931 qtest_add_func("/ahci/io/dma/lba28/retry", test_halted_dma);
1932 qtest_add_func("/ahci/migrate/dma/halted", test_migrate_halted_dma);
1933
1934 qtest_add_func("/ahci/max", test_max);
1935 qtest_add_func("/ahci/reset", test_reset);
1936
1937 qtest_add_func("/ahci/io/ncq/simple", test_ncq_simple);
1938 qtest_add_func("/ahci/migrate/ncq/simple", test_migrate_ncq);
1939 qtest_add_func("/ahci/io/ncq/retry", test_halted_ncq);
1940 qtest_add_func("/ahci/migrate/ncq/halted", test_migrate_halted_ncq);
1941
1942 qtest_add_func("/ahci/cdrom/dma/single", test_cdrom_dma);
1943 qtest_add_func("/ahci/cdrom/dma/multi", test_cdrom_dma_multi);
1944 qtest_add_func("/ahci/cdrom/pio/single", test_cdrom_pio);
1945 qtest_add_func("/ahci/cdrom/pio/multi", test_cdrom_pio_multi);
1946
1947 qtest_add_func("/ahci/cdrom/pio/bcl", test_atapi_bcl);
1948 qtest_add_func("/ahci/cdrom/eject", test_atapi_tray);
1949
1950 ret = g_test_run();
1951
1952
1953 unlink(tmp_path);
1954 unlink(debug_path);
1955 unlink(mig_socket);
1956
1957 return ret;
1958}
1959