qemu/hw/acpi/piix4.c
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   1/*
   2 * ACPI implementation
   3 *
   4 * Copyright (c) 2006 Fabrice Bellard
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License version 2 as published by the Free Software Foundation.
   9 *
  10 * This library is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13 * Lesser General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU Lesser General Public
  16 * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17 *
  18 * Contributions after 2012-01-13 are licensed under the terms of the
  19 * GNU GPL, version 2 or (at your option) any later version.
  20 */
  21#include "qemu/osdep.h"
  22#include "hw/hw.h"
  23#include "hw/i386/pc.h"
  24#include "hw/isa/apm.h"
  25#include "hw/i2c/pm_smbus.h"
  26#include "hw/pci/pci.h"
  27#include "hw/acpi/acpi.h"
  28#include "sysemu/sysemu.h"
  29#include "qapi/error.h"
  30#include "qemu/range.h"
  31#include "hw/nvram/fw_cfg.h"
  32#include "exec/address-spaces.h"
  33#include "hw/acpi/piix4.h"
  34#include "hw/acpi/pcihp.h"
  35#include "hw/acpi/cpu_hotplug.h"
  36#include "hw/acpi/cpu.h"
  37#include "hw/hotplug.h"
  38#include "hw/mem/pc-dimm.h"
  39#include "hw/acpi/memory_hotplug.h"
  40#include "hw/acpi/acpi_dev_interface.h"
  41#include "hw/xen/xen.h"
  42#include "qom/cpu.h"
  43
  44//#define DEBUG
  45
  46#ifdef DEBUG
  47# define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  48#else
  49# define PIIX4_DPRINTF(format, ...)     do { } while (0)
  50#endif
  51
  52#define GPE_BASE 0xafe0
  53#define GPE_LEN 4
  54
  55struct pci_status {
  56    uint32_t up; /* deprecated, maintained for migration compatibility */
  57    uint32_t down;
  58};
  59
  60typedef struct PIIX4PMState {
  61    /*< private >*/
  62    PCIDevice parent_obj;
  63    /*< public >*/
  64
  65    MemoryRegion io;
  66    uint32_t io_base;
  67
  68    MemoryRegion io_gpe;
  69    ACPIREGS ar;
  70
  71    APMState apm;
  72
  73    PMSMBus smb;
  74    uint32_t smb_io_base;
  75
  76    qemu_irq irq;
  77    qemu_irq smi_irq;
  78    int smm_enabled;
  79    Notifier machine_ready;
  80    Notifier powerdown_notifier;
  81
  82    AcpiPciHpState acpi_pci_hotplug;
  83    bool use_acpi_pci_hotplug;
  84
  85    uint8_t disable_s3;
  86    uint8_t disable_s4;
  87    uint8_t s4_val;
  88
  89    bool cpu_hotplug_legacy;
  90    AcpiCpuHotplug gpe_cpu;
  91    CPUHotplugState cpuhp_state;
  92
  93    MemHotplugState acpi_memory_hotplug;
  94} PIIX4PMState;
  95
  96#define TYPE_PIIX4_PM "PIIX4_PM"
  97
  98#define PIIX4_PM(obj) \
  99    OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM)
 100
 101static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
 102                                           PCIBus *bus, PIIX4PMState *s);
 103
 104#define ACPI_ENABLE 0xf1
 105#define ACPI_DISABLE 0xf0
 106
 107static void pm_tmr_timer(ACPIREGS *ar)
 108{
 109    PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
 110    acpi_update_sci(&s->ar, s->irq);
 111}
 112
 113static void apm_ctrl_changed(uint32_t val, void *arg)
 114{
 115    PIIX4PMState *s = arg;
 116    PCIDevice *d = PCI_DEVICE(s);
 117
 118    /* ACPI specs 3.0, 4.7.2.5 */
 119    acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
 120    if (val == ACPI_ENABLE || val == ACPI_DISABLE) {
 121        return;
 122    }
 123
 124    if (d->config[0x5b] & (1 << 1)) {
 125        if (s->smi_irq) {
 126            qemu_irq_raise(s->smi_irq);
 127        }
 128    }
 129}
 130
 131static void pm_io_space_update(PIIX4PMState *s)
 132{
 133    PCIDevice *d = PCI_DEVICE(s);
 134
 135    s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40));
 136    s->io_base &= 0xffc0;
 137
 138    memory_region_transaction_begin();
 139    memory_region_set_enabled(&s->io, d->config[0x80] & 1);
 140    memory_region_set_address(&s->io, s->io_base);
 141    memory_region_transaction_commit();
 142}
 143
 144static void smbus_io_space_update(PIIX4PMState *s)
 145{
 146    PCIDevice *d = PCI_DEVICE(s);
 147
 148    s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90));
 149    s->smb_io_base &= 0xffc0;
 150
 151    memory_region_transaction_begin();
 152    memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1);
 153    memory_region_set_address(&s->smb.io, s->smb_io_base);
 154    memory_region_transaction_commit();
 155}
 156
 157static void pm_write_config(PCIDevice *d,
 158                            uint32_t address, uint32_t val, int len)
 159{
 160    pci_default_write_config(d, address, val, len);
 161    if (range_covers_byte(address, len, 0x80) ||
 162        ranges_overlap(address, len, 0x40, 4)) {
 163        pm_io_space_update((PIIX4PMState *)d);
 164    }
 165    if (range_covers_byte(address, len, 0xd2) ||
 166        ranges_overlap(address, len, 0x90, 4)) {
 167        smbus_io_space_update((PIIX4PMState *)d);
 168    }
 169}
 170
 171static int vmstate_acpi_post_load(void *opaque, int version_id)
 172{
 173    PIIX4PMState *s = opaque;
 174
 175    pm_io_space_update(s);
 176    smbus_io_space_update(s);
 177    return 0;
 178}
 179
 180#define VMSTATE_GPE_ARRAY(_field, _state)                            \
 181 {                                                                   \
 182     .name       = (stringify(_field)),                              \
 183     .version_id = 0,                                                \
 184     .info       = &vmstate_info_uint16,                             \
 185     .size       = sizeof(uint16_t),                                 \
 186     .flags      = VMS_SINGLE | VMS_POINTER,                         \
 187     .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 188 }
 189
 190static const VMStateDescription vmstate_gpe = {
 191    .name = "gpe",
 192    .version_id = 1,
 193    .minimum_version_id = 1,
 194    .fields = (VMStateField[]) {
 195        VMSTATE_GPE_ARRAY(sts, ACPIGPE),
 196        VMSTATE_GPE_ARRAY(en, ACPIGPE),
 197        VMSTATE_END_OF_LIST()
 198    }
 199};
 200
 201static const VMStateDescription vmstate_pci_status = {
 202    .name = "pci_status",
 203    .version_id = 1,
 204    .minimum_version_id = 1,
 205    .fields = (VMStateField[]) {
 206        VMSTATE_UINT32(up, struct AcpiPciHpPciStatus),
 207        VMSTATE_UINT32(down, struct AcpiPciHpPciStatus),
 208        VMSTATE_END_OF_LIST()
 209    }
 210};
 211
 212static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
 213{
 214    PIIX4PMState *s = opaque;
 215    int ret, i;
 216    uint16_t temp;
 217
 218    ret = pci_device_load(PCI_DEVICE(s), f);
 219    if (ret < 0) {
 220        return ret;
 221    }
 222    qemu_get_be16s(f, &s->ar.pm1.evt.sts);
 223    qemu_get_be16s(f, &s->ar.pm1.evt.en);
 224    qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
 225
 226    ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
 227    if (ret) {
 228        return ret;
 229    }
 230
 231    timer_get(f, s->ar.tmr.timer);
 232    qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
 233
 234    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
 235    for (i = 0; i < 3; i++) {
 236        qemu_get_be16s(f, &temp);
 237    }
 238
 239    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
 240    for (i = 0; i < 3; i++) {
 241        qemu_get_be16s(f, &temp);
 242    }
 243
 244    ret = vmstate_load_state(f, &vmstate_pci_status,
 245        &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
 246    return ret;
 247}
 248
 249static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
 250{
 251    PIIX4PMState *s = opaque;
 252    return s->use_acpi_pci_hotplug;
 253}
 254
 255static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id)
 256{
 257    PIIX4PMState *s = opaque;
 258    return !s->use_acpi_pci_hotplug;
 259}
 260
 261static bool vmstate_test_use_memhp(void *opaque)
 262{
 263    PIIX4PMState *s = opaque;
 264    return s->acpi_memory_hotplug.is_enabled;
 265}
 266
 267static const VMStateDescription vmstate_memhp_state = {
 268    .name = "piix4_pm/memhp",
 269    .version_id = 1,
 270    .minimum_version_id = 1,
 271    .minimum_version_id_old = 1,
 272    .needed = vmstate_test_use_memhp,
 273    .fields      = (VMStateField[]) {
 274        VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState),
 275        VMSTATE_END_OF_LIST()
 276    }
 277};
 278
 279static bool vmstate_test_use_cpuhp(void *opaque)
 280{
 281    PIIX4PMState *s = opaque;
 282    return !s->cpu_hotplug_legacy;
 283}
 284
 285static int vmstate_cpuhp_pre_load(void *opaque)
 286{
 287    Object *obj = OBJECT(opaque);
 288    object_property_set_bool(obj, false, "cpu-hotplug-legacy", &error_abort);
 289    return 0;
 290}
 291
 292static const VMStateDescription vmstate_cpuhp_state = {
 293    .name = "piix4_pm/cpuhp",
 294    .version_id = 1,
 295    .minimum_version_id = 1,
 296    .minimum_version_id_old = 1,
 297    .needed = vmstate_test_use_cpuhp,
 298    .pre_load = vmstate_cpuhp_pre_load,
 299    .fields      = (VMStateField[]) {
 300        VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState),
 301        VMSTATE_END_OF_LIST()
 302    }
 303};
 304
 305/* qemu-kvm 1.2 uses version 3 but advertised as 2
 306 * To support incoming qemu-kvm 1.2 migration, change version_id
 307 * and minimum_version_id to 2 below (which breaks migration from
 308 * qemu 1.2).
 309 *
 310 */
 311static const VMStateDescription vmstate_acpi = {
 312    .name = "piix4_pm",
 313    .version_id = 3,
 314    .minimum_version_id = 3,
 315    .minimum_version_id_old = 1,
 316    .load_state_old = acpi_load_old,
 317    .post_load = vmstate_acpi_post_load,
 318    .fields = (VMStateField[]) {
 319        VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
 320        VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
 321        VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
 322        VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
 323        VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 324        VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState),
 325        VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
 326        VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
 327        VMSTATE_STRUCT_TEST(
 328            acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT],
 329            PIIX4PMState,
 330            vmstate_test_no_use_acpi_pci_hotplug,
 331            2, vmstate_pci_status,
 332            struct AcpiPciHpPciStatus),
 333        VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
 334                            vmstate_test_use_acpi_pci_hotplug),
 335        VMSTATE_END_OF_LIST()
 336    },
 337    .subsections = (const VMStateDescription*[]) {
 338         &vmstate_memhp_state,
 339         &vmstate_cpuhp_state,
 340         NULL
 341    }
 342};
 343
 344static void piix4_reset(void *opaque)
 345{
 346    PIIX4PMState *s = opaque;
 347    PCIDevice *d = PCI_DEVICE(s);
 348    uint8_t *pci_conf = d->config;
 349
 350    pci_conf[0x58] = 0;
 351    pci_conf[0x59] = 0;
 352    pci_conf[0x5a] = 0;
 353    pci_conf[0x5b] = 0;
 354
 355    pci_conf[0x40] = 0x01; /* PM io base read only bit */
 356    pci_conf[0x80] = 0;
 357
 358    if (!s->smm_enabled) {
 359        /* Mark SMM as already inited (until KVM supports SMM). */
 360        pci_conf[0x5B] = 0x02;
 361    }
 362    pm_io_space_update(s);
 363    acpi_pcihp_reset(&s->acpi_pci_hotplug);
 364}
 365
 366static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
 367{
 368    PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier);
 369
 370    assert(s != NULL);
 371    acpi_pm1_evt_power_down(&s->ar);
 372}
 373
 374static void piix4_device_plug_cb(HotplugHandler *hotplug_dev,
 375                                 DeviceState *dev, Error **errp)
 376{
 377    PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 378
 379    if (s->acpi_memory_hotplug.is_enabled &&
 380        object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 381        if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
 382            nvdimm_acpi_plug_cb(hotplug_dev, dev);
 383        } else {
 384            acpi_memory_plug_cb(hotplug_dev, &s->acpi_memory_hotplug,
 385                                dev, errp);
 386        }
 387    } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 388        acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp);
 389    } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
 390        if (s->cpu_hotplug_legacy) {
 391            legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp);
 392        } else {
 393            acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
 394        }
 395    } else {
 396        error_setg(errp, "acpi: device plug request for not supported device"
 397                   " type: %s", object_get_typename(OBJECT(dev)));
 398    }
 399}
 400
 401static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev,
 402                                           DeviceState *dev, Error **errp)
 403{
 404    PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 405
 406    if (s->acpi_memory_hotplug.is_enabled &&
 407        object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 408        acpi_memory_unplug_request_cb(hotplug_dev, &s->acpi_memory_hotplug,
 409                                      dev, errp);
 410    } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 411        acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev,
 412                                    errp);
 413    } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
 414               !s->cpu_hotplug_legacy) {
 415        acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
 416    } else {
 417        error_setg(errp, "acpi: device unplug request for not supported device"
 418                   " type: %s", object_get_typename(OBJECT(dev)));
 419    }
 420}
 421
 422static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev,
 423                                   DeviceState *dev, Error **errp)
 424{
 425    PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 426
 427    if (s->acpi_memory_hotplug.is_enabled &&
 428        object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 429        acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp);
 430    } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
 431               !s->cpu_hotplug_legacy) {
 432        acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp);
 433    } else {
 434        error_setg(errp, "acpi: device unplug for not supported device"
 435                   " type: %s", object_get_typename(OBJECT(dev)));
 436    }
 437}
 438
 439static void piix4_update_bus_hotplug(PCIBus *pci_bus, void *opaque)
 440{
 441    PIIX4PMState *s = opaque;
 442
 443    /* pci_bus cannot outlive PIIX4PMState, because /machine keeps it alive
 444     * and it's not hot-unpluggable */
 445    qbus_set_hotplug_handler(BUS(pci_bus), DEVICE(s), &error_abort);
 446}
 447
 448static void piix4_pm_machine_ready(Notifier *n, void *opaque)
 449{
 450    PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
 451    PCIDevice *d = PCI_DEVICE(s);
 452    MemoryRegion *io_as = pci_address_space_io(d);
 453    uint8_t *pci_conf;
 454
 455    pci_conf = d->config;
 456    pci_conf[0x5f] = 0x10 |
 457        (memory_region_present(io_as, 0x378) ? 0x80 : 0);
 458    pci_conf[0x63] = 0x60;
 459    pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) |
 460        (memory_region_present(io_as, 0x2f8) ? 0x90 : 0);
 461
 462    if (s->use_acpi_pci_hotplug) {
 463        pci_for_each_bus(pci_get_bus(d), piix4_update_bus_hotplug, s);
 464    } else {
 465        piix4_update_bus_hotplug(pci_get_bus(d), s);
 466    }
 467}
 468
 469static void piix4_pm_add_propeties(PIIX4PMState *s)
 470{
 471    static const uint8_t acpi_enable_cmd = ACPI_ENABLE;
 472    static const uint8_t acpi_disable_cmd = ACPI_DISABLE;
 473    static const uint32_t gpe0_blk = GPE_BASE;
 474    static const uint32_t gpe0_blk_len = GPE_LEN;
 475    static const uint16_t sci_int = 9;
 476
 477    object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD,
 478                                  &acpi_enable_cmd, NULL);
 479    object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD,
 480                                  &acpi_disable_cmd, NULL);
 481    object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK,
 482                                  &gpe0_blk, NULL);
 483    object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN,
 484                                  &gpe0_blk_len, NULL);
 485    object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT,
 486                                  &sci_int, NULL);
 487    object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE,
 488                                  &s->io_base, NULL);
 489}
 490
 491static void piix4_pm_realize(PCIDevice *dev, Error **errp)
 492{
 493    PIIX4PMState *s = PIIX4_PM(dev);
 494    uint8_t *pci_conf;
 495
 496    pci_conf = dev->config;
 497    pci_conf[0x06] = 0x80;
 498    pci_conf[0x07] = 0x02;
 499    pci_conf[0x09] = 0x00;
 500    pci_conf[0x3d] = 0x01; // interrupt pin 1
 501
 502    /* APM */
 503    apm_init(dev, &s->apm, apm_ctrl_changed, s);
 504
 505    if (!s->smm_enabled) {
 506        /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 507         * support SMM mode. */
 508        pci_conf[0x5B] = 0x02;
 509    }
 510
 511    /* XXX: which specification is used ? The i82731AB has different
 512       mappings */
 513    pci_conf[0x90] = s->smb_io_base | 1;
 514    pci_conf[0x91] = s->smb_io_base >> 8;
 515    pci_conf[0xd2] = 0x09;
 516    pm_smbus_init(DEVICE(dev), &s->smb, true);
 517    memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1);
 518    memory_region_add_subregion(pci_address_space_io(dev),
 519                                s->smb_io_base, &s->smb.io);
 520
 521    memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64);
 522    memory_region_set_enabled(&s->io, false);
 523    memory_region_add_subregion(pci_address_space_io(dev),
 524                                0, &s->io);
 525
 526    acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
 527    acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
 528    acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val);
 529    acpi_gpe_init(&s->ar, GPE_LEN);
 530
 531    s->powerdown_notifier.notify = piix4_pm_powerdown_req;
 532    qemu_register_powerdown_notifier(&s->powerdown_notifier);
 533
 534    s->machine_ready.notify = piix4_pm_machine_ready;
 535    qemu_add_machine_init_done_notifier(&s->machine_ready);
 536    qemu_register_reset(piix4_reset, s);
 537
 538    piix4_acpi_system_hot_add_init(pci_address_space_io(dev),
 539                                   pci_get_bus(dev), s);
 540
 541    piix4_pm_add_propeties(s);
 542}
 543
 544Object *piix4_pm_find(void)
 545{
 546    bool ambig;
 547    Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig);
 548
 549    if (ambig || !o) {
 550        return NULL;
 551    }
 552    return o;
 553}
 554
 555I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 556                      qemu_irq sci_irq, qemu_irq smi_irq,
 557                      int smm_enabled, DeviceState **piix4_pm)
 558{
 559    DeviceState *dev;
 560    PIIX4PMState *s;
 561
 562    dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM));
 563    qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
 564    if (piix4_pm) {
 565        *piix4_pm = dev;
 566    }
 567
 568    s = PIIX4_PM(dev);
 569    s->irq = sci_irq;
 570    s->smi_irq = smi_irq;
 571    s->smm_enabled = smm_enabled;
 572    if (xen_enabled()) {
 573        s->use_acpi_pci_hotplug = false;
 574    }
 575
 576    qdev_init_nofail(dev);
 577
 578    return s->smb.smbus;
 579}
 580
 581static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
 582{
 583    PIIX4PMState *s = opaque;
 584    uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
 585
 586    PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val);
 587    return val;
 588}
 589
 590static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
 591                       unsigned width)
 592{
 593    PIIX4PMState *s = opaque;
 594
 595    acpi_gpe_ioport_writeb(&s->ar, addr, val);
 596    acpi_update_sci(&s->ar, s->irq);
 597
 598    PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val);
 599}
 600
 601static const MemoryRegionOps piix4_gpe_ops = {
 602    .read = gpe_readb,
 603    .write = gpe_writeb,
 604    .valid.min_access_size = 1,
 605    .valid.max_access_size = 4,
 606    .impl.min_access_size = 1,
 607    .impl.max_access_size = 1,
 608    .endianness = DEVICE_LITTLE_ENDIAN,
 609};
 610
 611
 612static bool piix4_get_cpu_hotplug_legacy(Object *obj, Error **errp)
 613{
 614    PIIX4PMState *s = PIIX4_PM(obj);
 615
 616    return s->cpu_hotplug_legacy;
 617}
 618
 619static void piix4_set_cpu_hotplug_legacy(Object *obj, bool value, Error **errp)
 620{
 621    PIIX4PMState *s = PIIX4_PM(obj);
 622
 623    assert(!value);
 624    if (s->cpu_hotplug_legacy && value == false) {
 625        acpi_switch_to_modern_cphp(&s->gpe_cpu, &s->cpuhp_state,
 626                                   PIIX4_CPU_HOTPLUG_IO_BASE);
 627    }
 628    s->cpu_hotplug_legacy = value;
 629}
 630
 631static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
 632                                           PCIBus *bus, PIIX4PMState *s)
 633{
 634    memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s,
 635                          "acpi-gpe0", GPE_LEN);
 636    memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
 637
 638    acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent,
 639                    s->use_acpi_pci_hotplug);
 640
 641    s->cpu_hotplug_legacy = true;
 642    object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy",
 643                             piix4_get_cpu_hotplug_legacy,
 644                             piix4_set_cpu_hotplug_legacy,
 645                             NULL);
 646    legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu,
 647                                 PIIX4_CPU_HOTPLUG_IO_BASE);
 648
 649    if (s->acpi_memory_hotplug.is_enabled) {
 650        acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug,
 651                                 ACPI_MEMORY_HOTPLUG_BASE);
 652    }
 653}
 654
 655static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
 656{
 657    PIIX4PMState *s = PIIX4_PM(adev);
 658
 659    acpi_memory_ospm_status(&s->acpi_memory_hotplug, list);
 660    if (!s->cpu_hotplug_legacy) {
 661        acpi_cpu_ospm_status(&s->cpuhp_state, list);
 662    }
 663}
 664
 665static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
 666{
 667    PIIX4PMState *s = PIIX4_PM(adev);
 668
 669    acpi_send_gpe_event(&s->ar, s->irq, ev);
 670}
 671
 672static Property piix4_pm_properties[] = {
 673    DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 674    DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
 675    DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
 676    DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
 677    DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState,
 678                     use_acpi_pci_hotplug, true),
 679    DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState,
 680                     acpi_memory_hotplug.is_enabled, true),
 681    DEFINE_PROP_END_OF_LIST(),
 682};
 683
 684static void piix4_pm_class_init(ObjectClass *klass, void *data)
 685{
 686    DeviceClass *dc = DEVICE_CLASS(klass);
 687    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 688    HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
 689    AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
 690
 691    k->realize = piix4_pm_realize;
 692    k->config_write = pm_write_config;
 693    k->vendor_id = PCI_VENDOR_ID_INTEL;
 694    k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
 695    k->revision = 0x03;
 696    k->class_id = PCI_CLASS_BRIDGE_OTHER;
 697    dc->desc = "PM";
 698    dc->vmsd = &vmstate_acpi;
 699    dc->props = piix4_pm_properties;
 700    /*
 701     * Reason: part of PIIX4 southbridge, needs to be wired up,
 702     * e.g. by mips_malta_init()
 703     */
 704    dc->user_creatable = false;
 705    dc->hotpluggable = false;
 706    hc->plug = piix4_device_plug_cb;
 707    hc->unplug_request = piix4_device_unplug_request_cb;
 708    hc->unplug = piix4_device_unplug_cb;
 709    adevc->ospm_status = piix4_ospm_status;
 710    adevc->send_event = piix4_send_gpe;
 711    adevc->madt_cpu = pc_madt_cpu_entry;
 712}
 713
 714static const TypeInfo piix4_pm_info = {
 715    .name          = TYPE_PIIX4_PM,
 716    .parent        = TYPE_PCI_DEVICE,
 717    .instance_size = sizeof(PIIX4PMState),
 718    .class_init    = piix4_pm_class_init,
 719    .interfaces = (InterfaceInfo[]) {
 720        { TYPE_HOTPLUG_HANDLER },
 721        { TYPE_ACPI_DEVICE_IF },
 722        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 723        { }
 724    }
 725};
 726
 727static void piix4_pm_register_types(void)
 728{
 729    type_register_static(&piix4_pm_info);
 730}
 731
 732type_init(piix4_pm_register_types)
 733