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11#include "qemu/osdep.h"
12#include "qapi/error.h"
13#include "qemu-common.h"
14#include "hw/arm/arm.h"
15#include "hw/sysbus.h"
16#include "hw/boards.h"
17#include "hw/devices.h"
18#include "hw/misc/unimp.h"
19#include "exec/address-spaces.h"
20#include "sysemu/sysemu.h"
21#include "qemu/log.h"
22#include "cpu.h"
23
24#include "hw/arm/nrf51_soc.h"
25
26#define IOMEM_BASE 0x40000000
27#define IOMEM_SIZE 0x20000000
28
29#define FICR_BASE 0x10000000
30#define FICR_SIZE 0x000000fc
31
32#define FLASH_BASE 0x00000000
33#define SRAM_BASE 0x20000000
34
35#define PRIVATE_BASE 0xF0000000
36#define PRIVATE_SIZE 0x10000000
37
38
39
40
41
42
43#define NRF51822_FLASH_SIZE (256 * 1024)
44#define NRF51822_SRAM_SIZE (16 * 1024)
45
46#define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)
47
48static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
49{
50 NRF51State *s = NRF51_SOC(dev_soc);
51 MemoryRegion *mr;
52 Error *err = NULL;
53
54 if (!s->board_memory) {
55 error_setg(errp, "memory property was not set");
56 return;
57 }
58
59 object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory",
60 &err);
61 if (err) {
62 error_propagate(errp, err);
63 return;
64 }
65 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
66 if (err) {
67 error_propagate(errp, err);
68 return;
69 }
70
71 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
72
73 memory_region_init_rom(&s->flash, OBJECT(s), "nrf51.flash", s->flash_size,
74 &err);
75 if (err) {
76 error_propagate(errp, err);
77 return;
78 }
79 memory_region_add_subregion(&s->container, FLASH_BASE, &s->flash);
80
81 memory_region_init_ram(&s->sram, NULL, "nrf51.sram", s->sram_size, &err);
82 if (err) {
83 error_propagate(errp, err);
84 return;
85 }
86 memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram);
87
88
89 object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);
90 if (err) {
91 error_propagate(errp, err);
92 return;
93 }
94 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
95 memory_region_add_subregion_overlap(&s->container, UART_BASE, mr, 0);
96 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,
97 qdev_get_gpio_in(DEVICE(&s->cpu),
98 BASE_TO_IRQ(UART_BASE)));
99
100 create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE);
101 create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE);
102 create_unimplemented_device("nrf51_soc.private",
103 PRIVATE_BASE, PRIVATE_SIZE);
104}
105
106static void nrf51_soc_init(Object *obj)
107{
108 NRF51State *s = NRF51_SOC(obj);
109
110 memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);
111
112 sysbus_init_child_obj(OBJECT(s), "armv6m", OBJECT(&s->cpu), sizeof(s->cpu),
113 TYPE_ARMV7M);
114 qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
115 ARM_CPU_TYPE_NAME("cortex-m0"));
116 qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
117
118 sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart),
119 TYPE_NRF51_UART);
120 object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev",
121 &error_abort);
122}
123
124static Property nrf51_soc_properties[] = {
125 DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION,
126 MemoryRegion *),
127 DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE),
128 DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size,
129 NRF51822_FLASH_SIZE),
130 DEFINE_PROP_END_OF_LIST(),
131};
132
133static void nrf51_soc_class_init(ObjectClass *klass, void *data)
134{
135 DeviceClass *dc = DEVICE_CLASS(klass);
136
137 dc->realize = nrf51_soc_realize;
138 dc->props = nrf51_soc_properties;
139}
140
141static const TypeInfo nrf51_soc_info = {
142 .name = TYPE_NRF51_SOC,
143 .parent = TYPE_SYS_BUS_DEVICE,
144 .instance_size = sizeof(NRF51State),
145 .instance_init = nrf51_soc_init,
146 .class_init = nrf51_soc_class_init,
147};
148
149static void nrf51_soc_types(void)
150{
151 type_register_static(&nrf51_soc_info);
152}
153type_init(nrf51_soc_types)
154