1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31#include "qemu/osdep.h"
32#include "qapi/error.h"
33#include "hw/sysbus.h"
34#include "hw/arm/arm.h"
35#include "hw/arm/primecell.h"
36#include "hw/arm/virt.h"
37#include "hw/block/flash.h"
38#include "hw/vfio/vfio-calxeda-xgmac.h"
39#include "hw/vfio/vfio-amd-xgbe.h"
40#include "hw/display/ramfb.h"
41#include "hw/devices.h"
42#include "net/net.h"
43#include "sysemu/device_tree.h"
44#include "sysemu/numa.h"
45#include "sysemu/sysemu.h"
46#include "sysemu/kvm.h"
47#include "hw/compat.h"
48#include "hw/loader.h"
49#include "exec/address-spaces.h"
50#include "qemu/bitops.h"
51#include "qemu/error-report.h"
52#include "hw/pci-host/gpex.h"
53#include "hw/arm/sysbus-fdt.h"
54#include "hw/platform-bus.h"
55#include "hw/arm/fdt.h"
56#include "hw/intc/arm_gic.h"
57#include "hw/intc/arm_gicv3_common.h"
58#include "kvm_arm.h"
59#include "hw/smbios/smbios.h"
60#include "qapi/visitor.h"
61#include "standard-headers/linux/input.h"
62#include "hw/arm/smmuv3.h"
63
64#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
65 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
66 void *data) \
67 { \
68 MachineClass *mc = MACHINE_CLASS(oc); \
69 virt_machine_##major##_##minor##_options(mc); \
70 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
71 if (latest) { \
72 mc->alias = "virt"; \
73 } \
74 } \
75 static const TypeInfo machvirt_##major##_##minor##_info = { \
76 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
77 .parent = TYPE_VIRT_MACHINE, \
78 .instance_init = virt_##major##_##minor##_instance_init, \
79 .class_init = virt_##major##_##minor##_class_init, \
80 }; \
81 static void machvirt_machine_##major##_##minor##_init(void) \
82 { \
83 type_register_static(&machvirt_##major##_##minor##_info); \
84 } \
85 type_init(machvirt_machine_##major##_##minor##_init);
86
87#define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
88 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
89#define DEFINE_VIRT_MACHINE(major, minor) \
90 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
91
92
93
94#define NUM_IRQS 256
95
96#define PLATFORM_BUS_NUM_IRQS 64
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112#define RAMLIMIT_GB 255
113#define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024)
114
115
116
117
118
119
120
121
122
123
124
125
126
127static const MemMapEntry a15memmap[] = {
128
129 [VIRT_FLASH] = { 0, 0x08000000 },
130 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
131
132 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
133 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
134 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
135 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 },
136 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 },
137
138 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
139
140 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
141 [VIRT_UART] = { 0x09000000, 0x00001000 },
142 [VIRT_RTC] = { 0x09010000, 0x00001000 },
143 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
144 [VIRT_GPIO] = { 0x09030000, 0x00001000 },
145 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 },
146 [VIRT_SMMU] = { 0x09050000, 0x00020000 },
147 [VIRT_MMIO] = { 0x0a000000, 0x00000200 },
148
149 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
150 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 },
151 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
152 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
153 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
154 [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES },
155
156 [VIRT_GIC_REDIST2] = { 0x4000000000ULL, 0x4000000 },
157 [VIRT_PCIE_ECAM_HIGH] = { 0x4010000000ULL, 0x10000000 },
158
159 [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL },
160};
161
162static const int a15irqmap[] = {
163 [VIRT_UART] = 1,
164 [VIRT_RTC] = 2,
165 [VIRT_PCIE] = 3,
166 [VIRT_GPIO] = 7,
167 [VIRT_SECURE_UART] = 8,
168 [VIRT_MMIO] = 16,
169 [VIRT_GIC_V2M] = 48,
170 [VIRT_SMMU] = 74,
171 [VIRT_PLATFORM_BUS] = 112,
172};
173
174static const char *valid_cpus[] = {
175 ARM_CPU_TYPE_NAME("cortex-a15"),
176 ARM_CPU_TYPE_NAME("cortex-a53"),
177 ARM_CPU_TYPE_NAME("cortex-a57"),
178 ARM_CPU_TYPE_NAME("cortex-a72"),
179 ARM_CPU_TYPE_NAME("host"),
180 ARM_CPU_TYPE_NAME("max"),
181};
182
183static bool cpu_type_valid(const char *cpu)
184{
185 int i;
186
187 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
188 if (strcmp(cpu, valid_cpus[i]) == 0) {
189 return true;
190 }
191 }
192 return false;
193}
194
195static void create_fdt(VirtMachineState *vms)
196{
197 void *fdt = create_device_tree(&vms->fdt_size);
198
199 if (!fdt) {
200 error_report("create_device_tree() failed");
201 exit(1);
202 }
203
204 vms->fdt = fdt;
205
206
207 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
208 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
209 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
210
211
212 qemu_fdt_add_subnode(fdt, "/chosen");
213
214
215
216
217
218
219 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
220 qemu_fdt_add_subnode(fdt, "/apb-pclk");
221 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
222 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
223 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
224 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
225 "clk24mhz");
226 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
227
228 if (have_numa_distance) {
229 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
230 uint32_t *matrix = g_malloc0(size);
231 int idx, i, j;
232
233 for (i = 0; i < nb_numa_nodes; i++) {
234 for (j = 0; j < nb_numa_nodes; j++) {
235 idx = (i * nb_numa_nodes + j) * 3;
236 matrix[idx + 0] = cpu_to_be32(i);
237 matrix[idx + 1] = cpu_to_be32(j);
238 matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]);
239 }
240 }
241
242 qemu_fdt_add_subnode(fdt, "/distance-map");
243 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
244 "numa-distance-map-v1");
245 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
246 matrix, size);
247 g_free(matrix);
248 }
249}
250
251static void fdt_add_timer_nodes(const VirtMachineState *vms)
252{
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271 ARMCPU *armcpu;
272 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
273 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
274
275 if (vmc->claim_edge_triggered_timers) {
276 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
277 }
278
279 if (vms->gic_version == 2) {
280 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
281 GIC_FDT_IRQ_PPI_CPU_WIDTH,
282 (1 << vms->smp_cpus) - 1);
283 }
284
285 qemu_fdt_add_subnode(vms->fdt, "/timer");
286
287 armcpu = ARM_CPU(qemu_get_cpu(0));
288 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
289 const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
290 qemu_fdt_setprop(vms->fdt, "/timer", "compatible",
291 compat, sizeof(compat));
292 } else {
293 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible",
294 "arm,armv7-timer");
295 }
296 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0);
297 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts",
298 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
299 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
300 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
301 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
302}
303
304static void fdt_add_cpu_nodes(const VirtMachineState *vms)
305{
306 int cpu;
307 int addr_cells = 1;
308 const MachineState *ms = MACHINE(vms);
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323 for (cpu = 0; cpu < vms->smp_cpus; cpu++) {
324 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
325
326 if (armcpu->mp_affinity & ARM_AFF3_MASK) {
327 addr_cells = 2;
328 break;
329 }
330 }
331
332 qemu_fdt_add_subnode(vms->fdt, "/cpus");
333 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells);
334 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0);
335
336 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) {
337 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
338 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
339 CPUState *cs = CPU(armcpu);
340
341 qemu_fdt_add_subnode(vms->fdt, nodename);
342 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu");
343 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
344 armcpu->dtb_compatible);
345
346 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED
347 && vms->smp_cpus > 1) {
348 qemu_fdt_setprop_string(vms->fdt, nodename,
349 "enable-method", "psci");
350 }
351
352 if (addr_cells == 2) {
353 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg",
354 armcpu->mp_affinity);
355 } else {
356 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg",
357 armcpu->mp_affinity);
358 }
359
360 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
361 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id",
362 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
363 }
364
365 g_free(nodename);
366 }
367}
368
369static void fdt_add_its_gic_node(VirtMachineState *vms)
370{
371 char *nodename;
372
373 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt);
374 nodename = g_strdup_printf("/intc/its@%" PRIx64,
375 vms->memmap[VIRT_GIC_ITS].base);
376 qemu_fdt_add_subnode(vms->fdt, nodename);
377 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
378 "arm,gic-v3-its");
379 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0);
380 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
381 2, vms->memmap[VIRT_GIC_ITS].base,
382 2, vms->memmap[VIRT_GIC_ITS].size);
383 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle);
384 g_free(nodename);
385}
386
387static void fdt_add_v2m_gic_node(VirtMachineState *vms)
388{
389 char *nodename;
390
391 nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
392 vms->memmap[VIRT_GIC_V2M].base);
393 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt);
394 qemu_fdt_add_subnode(vms->fdt, nodename);
395 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
396 "arm,gic-v2m-frame");
397 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0);
398 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
399 2, vms->memmap[VIRT_GIC_V2M].base,
400 2, vms->memmap[VIRT_GIC_V2M].size);
401 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle);
402 g_free(nodename);
403}
404
405static void fdt_add_gic_node(VirtMachineState *vms)
406{
407 char *nodename;
408
409 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt);
410 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle);
411
412 nodename = g_strdup_printf("/intc@%" PRIx64,
413 vms->memmap[VIRT_GIC_DIST].base);
414 qemu_fdt_add_subnode(vms->fdt, nodename);
415 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 3);
416 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-controller", NULL, 0);
417 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2);
418 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2);
419 qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0);
420 if (vms->gic_version == 3) {
421 int nb_redist_regions = virt_gicv3_redist_region_count(vms);
422
423 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
424 "arm,gic-v3");
425
426 qemu_fdt_setprop_cell(vms->fdt, nodename,
427 "#redistributor-regions", nb_redist_regions);
428
429 if (nb_redist_regions == 1) {
430 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
431 2, vms->memmap[VIRT_GIC_DIST].base,
432 2, vms->memmap[VIRT_GIC_DIST].size,
433 2, vms->memmap[VIRT_GIC_REDIST].base,
434 2, vms->memmap[VIRT_GIC_REDIST].size);
435 } else {
436 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
437 2, vms->memmap[VIRT_GIC_DIST].base,
438 2, vms->memmap[VIRT_GIC_DIST].size,
439 2, vms->memmap[VIRT_GIC_REDIST].base,
440 2, vms->memmap[VIRT_GIC_REDIST].size,
441 2, vms->memmap[VIRT_GIC_REDIST2].base,
442 2, vms->memmap[VIRT_GIC_REDIST2].size);
443 }
444
445 if (vms->virt) {
446 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
447 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
448 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
449 }
450 } else {
451
452 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
453 "arm,cortex-a15-gic");
454 if (!vms->virt) {
455 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
456 2, vms->memmap[VIRT_GIC_DIST].base,
457 2, vms->memmap[VIRT_GIC_DIST].size,
458 2, vms->memmap[VIRT_GIC_CPU].base,
459 2, vms->memmap[VIRT_GIC_CPU].size);
460 } else {
461 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
462 2, vms->memmap[VIRT_GIC_DIST].base,
463 2, vms->memmap[VIRT_GIC_DIST].size,
464 2, vms->memmap[VIRT_GIC_CPU].base,
465 2, vms->memmap[VIRT_GIC_CPU].size,
466 2, vms->memmap[VIRT_GIC_HYP].base,
467 2, vms->memmap[VIRT_GIC_HYP].size,
468 2, vms->memmap[VIRT_GIC_VCPU].base,
469 2, vms->memmap[VIRT_GIC_VCPU].size);
470 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
471 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
472 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
473 }
474 }
475
476 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->gic_phandle);
477 g_free(nodename);
478}
479
480static void fdt_add_pmu_nodes(const VirtMachineState *vms)
481{
482 CPUState *cpu;
483 ARMCPU *armcpu;
484 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
485
486 CPU_FOREACH(cpu) {
487 armcpu = ARM_CPU(cpu);
488 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
489 return;
490 }
491 if (kvm_enabled()) {
492 if (kvm_irqchip_in_kernel()) {
493 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
494 }
495 kvm_arm_pmu_init(cpu);
496 }
497 }
498
499 if (vms->gic_version == 2) {
500 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
501 GIC_FDT_IRQ_PPI_CPU_WIDTH,
502 (1 << vms->smp_cpus) - 1);
503 }
504
505 armcpu = ARM_CPU(qemu_get_cpu(0));
506 qemu_fdt_add_subnode(vms->fdt, "/pmu");
507 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
508 const char compat[] = "arm,armv8-pmuv3";
509 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible",
510 compat, sizeof(compat));
511 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts",
512 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags);
513 }
514}
515
516static void create_its(VirtMachineState *vms, DeviceState *gicdev)
517{
518 const char *itsclass = its_class_name();
519 DeviceState *dev;
520
521 if (!itsclass) {
522
523 return;
524 }
525
526 dev = qdev_create(NULL, itsclass);
527
528 object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3",
529 &error_abort);
530 qdev_init_nofail(dev);
531 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
532
533 fdt_add_its_gic_node(vms);
534}
535
536static void create_v2m(VirtMachineState *vms, qemu_irq *pic)
537{
538 int i;
539 int irq = vms->irqmap[VIRT_GIC_V2M];
540 DeviceState *dev;
541
542 dev = qdev_create(NULL, "arm-gicv2m");
543 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
544 qdev_prop_set_uint32(dev, "base-spi", irq);
545 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
546 qdev_init_nofail(dev);
547
548 for (i = 0; i < NUM_GICV2M_SPIS; i++) {
549 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
550 }
551
552 fdt_add_v2m_gic_node(vms);
553}
554
555static void create_gic(VirtMachineState *vms, qemu_irq *pic)
556{
557
558 DeviceState *gicdev;
559 SysBusDevice *gicbusdev;
560 const char *gictype;
561 int type = vms->gic_version, i;
562 uint32_t nb_redist_regions = 0;
563
564 gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
565
566 gicdev = qdev_create(NULL, gictype);
567 qdev_prop_set_uint32(gicdev, "revision", type);
568 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus);
569
570
571
572 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32);
573 if (!kvm_irqchip_in_kernel()) {
574 qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure);
575 }
576
577 if (type == 3) {
578 uint32_t redist0_capacity =
579 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
580 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
581
582 nb_redist_regions = virt_gicv3_redist_region_count(vms);
583
584 qdev_prop_set_uint32(gicdev, "len-redist-region-count",
585 nb_redist_regions);
586 qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count);
587
588 if (nb_redist_regions == 2) {
589 uint32_t redist1_capacity =
590 vms->memmap[VIRT_GIC_REDIST2].size / GICV3_REDIST_SIZE;
591
592 qdev_prop_set_uint32(gicdev, "redist-region-count[1]",
593 MIN(smp_cpus - redist0_count, redist1_capacity));
594 }
595 } else {
596 if (!kvm_irqchip_in_kernel()) {
597 qdev_prop_set_bit(gicdev, "has-virtualization-extensions",
598 vms->virt);
599 }
600 }
601 qdev_init_nofail(gicdev);
602 gicbusdev = SYS_BUS_DEVICE(gicdev);
603 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
604 if (type == 3) {
605 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
606 if (nb_redist_regions == 2) {
607 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_REDIST2].base);
608 }
609 } else {
610 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
611 if (vms->virt) {
612 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
613 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
614 }
615 }
616
617
618
619
620
621 for (i = 0; i < smp_cpus; i++) {
622 DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
623 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
624 int irq;
625
626
627
628 const int timer_irq[] = {
629 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
630 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
631 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
632 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
633 };
634
635 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
636 qdev_connect_gpio_out(cpudev, irq,
637 qdev_get_gpio_in(gicdev,
638 ppibase + timer_irq[irq]));
639 }
640
641 if (type == 3) {
642 qemu_irq irq = qdev_get_gpio_in(gicdev,
643 ppibase + ARCH_GIC_MAINT_IRQ);
644 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
645 0, irq);
646 } else if (vms->virt) {
647 qemu_irq irq = qdev_get_gpio_in(gicdev,
648 ppibase + ARCH_GIC_MAINT_IRQ);
649 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
650 }
651
652 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
653 qdev_get_gpio_in(gicdev, ppibase
654 + VIRTUAL_PMU_IRQ));
655
656 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
657 sysbus_connect_irq(gicbusdev, i + smp_cpus,
658 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
659 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
660 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
661 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
662 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
663 }
664
665 for (i = 0; i < NUM_IRQS; i++) {
666 pic[i] = qdev_get_gpio_in(gicdev, i);
667 }
668
669 fdt_add_gic_node(vms);
670
671 if (type == 3 && vms->its) {
672 create_its(vms, gicdev);
673 } else if (type == 2) {
674 create_v2m(vms, pic);
675 }
676}
677
678static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart,
679 MemoryRegion *mem, Chardev *chr)
680{
681 char *nodename;
682 hwaddr base = vms->memmap[uart].base;
683 hwaddr size = vms->memmap[uart].size;
684 int irq = vms->irqmap[uart];
685 const char compat[] = "arm,pl011\0arm,primecell";
686 const char clocknames[] = "uartclk\0apb_pclk";
687 DeviceState *dev = qdev_create(NULL, "pl011");
688 SysBusDevice *s = SYS_BUS_DEVICE(dev);
689
690 qdev_prop_set_chr(dev, "chardev", chr);
691 qdev_init_nofail(dev);
692 memory_region_add_subregion(mem, base,
693 sysbus_mmio_get_region(s, 0));
694 sysbus_connect_irq(s, 0, pic[irq]);
695
696 nodename = g_strdup_printf("/pl011@%" PRIx64, base);
697 qemu_fdt_add_subnode(vms->fdt, nodename);
698
699 qemu_fdt_setprop(vms->fdt, nodename, "compatible",
700 compat, sizeof(compat));
701 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
702 2, base, 2, size);
703 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
704 GIC_FDT_IRQ_TYPE_SPI, irq,
705 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
706 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks",
707 vms->clock_phandle, vms->clock_phandle);
708 qemu_fdt_setprop(vms->fdt, nodename, "clock-names",
709 clocknames, sizeof(clocknames));
710
711 if (uart == VIRT_UART) {
712 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename);
713 } else {
714
715 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
716 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
717
718 qemu_fdt_add_subnode(vms->fdt, "/secure-chosen");
719 qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path",
720 nodename);
721 }
722
723 g_free(nodename);
724}
725
726static void create_rtc(const VirtMachineState *vms, qemu_irq *pic)
727{
728 char *nodename;
729 hwaddr base = vms->memmap[VIRT_RTC].base;
730 hwaddr size = vms->memmap[VIRT_RTC].size;
731 int irq = vms->irqmap[VIRT_RTC];
732 const char compat[] = "arm,pl031\0arm,primecell";
733
734 sysbus_create_simple("pl031", base, pic[irq]);
735
736 nodename = g_strdup_printf("/pl031@%" PRIx64, base);
737 qemu_fdt_add_subnode(vms->fdt, nodename);
738 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat));
739 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
740 2, base, 2, size);
741 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
742 GIC_FDT_IRQ_TYPE_SPI, irq,
743 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
744 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle);
745 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
746 g_free(nodename);
747}
748
749static DeviceState *gpio_key_dev;
750static void virt_powerdown_req(Notifier *n, void *opaque)
751{
752
753 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
754}
755
756static Notifier virt_system_powerdown_notifier = {
757 .notify = virt_powerdown_req
758};
759
760static void create_gpio(const VirtMachineState *vms, qemu_irq *pic)
761{
762 char *nodename;
763 DeviceState *pl061_dev;
764 hwaddr base = vms->memmap[VIRT_GPIO].base;
765 hwaddr size = vms->memmap[VIRT_GPIO].size;
766 int irq = vms->irqmap[VIRT_GPIO];
767 const char compat[] = "arm,pl061\0arm,primecell";
768
769 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]);
770
771 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt);
772 nodename = g_strdup_printf("/pl061@%" PRIx64, base);
773 qemu_fdt_add_subnode(vms->fdt, nodename);
774 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
775 2, base, 2, size);
776 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat));
777 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2);
778 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0);
779 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
780 GIC_FDT_IRQ_TYPE_SPI, irq,
781 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
782 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle);
783 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
784 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle);
785
786 gpio_key_dev = sysbus_create_simple("gpio-key", -1,
787 qdev_get_gpio_in(pl061_dev, 3));
788 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys");
789 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys");
790 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0);
791 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1);
792
793 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff");
794 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff",
795 "label", "GPIO Key Poweroff");
796 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code",
797 KEY_POWER);
798 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff",
799 "gpios", phandle, 3, 0);
800
801
802 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier);
803
804 g_free(nodename);
805}
806
807static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic)
808{
809 int i;
810 hwaddr size = vms->memmap[VIRT_MMIO].size;
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
840 int irq = vms->irqmap[VIRT_MMIO] + i;
841 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
842
843 sysbus_create_simple("virtio-mmio", base, pic[irq]);
844 }
845
846
847
848
849
850
851
852
853 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
854 char *nodename;
855 int irq = vms->irqmap[VIRT_MMIO] + i;
856 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
857
858 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
859 qemu_fdt_add_subnode(vms->fdt, nodename);
860 qemu_fdt_setprop_string(vms->fdt, nodename,
861 "compatible", "virtio,mmio");
862 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
863 2, base, 2, size);
864 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
865 GIC_FDT_IRQ_TYPE_SPI, irq,
866 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
867 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
868 g_free(nodename);
869 }
870}
871
872static void create_one_flash(const char *name, hwaddr flashbase,
873 hwaddr flashsize, const char *file,
874 MemoryRegion *sysmem)
875{
876
877
878
879 DriveInfo *dinfo = drive_get_next(IF_PFLASH);
880 DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
881 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
882 const uint64_t sectorlength = 256 * 1024;
883
884 if (dinfo) {
885 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
886 &error_abort);
887 }
888
889 qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength);
890 qdev_prop_set_uint64(dev, "sector-length", sectorlength);
891 qdev_prop_set_uint8(dev, "width", 4);
892 qdev_prop_set_uint8(dev, "device-width", 2);
893 qdev_prop_set_bit(dev, "big-endian", false);
894 qdev_prop_set_uint16(dev, "id0", 0x89);
895 qdev_prop_set_uint16(dev, "id1", 0x18);
896 qdev_prop_set_uint16(dev, "id2", 0x00);
897 qdev_prop_set_uint16(dev, "id3", 0x00);
898 qdev_prop_set_string(dev, "name", name);
899 qdev_init_nofail(dev);
900
901 memory_region_add_subregion(sysmem, flashbase,
902 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
903
904 if (file) {
905 char *fn;
906 int image_size;
907
908 if (drive_get(IF_PFLASH, 0, 0)) {
909 error_report("The contents of the first flash device may be "
910 "specified with -bios or with -drive if=pflash... "
911 "but you cannot use both options at once");
912 exit(1);
913 }
914 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file);
915 if (!fn) {
916 error_report("Could not find ROM image '%s'", file);
917 exit(1);
918 }
919 image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0));
920 g_free(fn);
921 if (image_size < 0) {
922 error_report("Could not load ROM image '%s'", file);
923 exit(1);
924 }
925 }
926}
927
928static void create_flash(const VirtMachineState *vms,
929 MemoryRegion *sysmem,
930 MemoryRegion *secure_sysmem)
931{
932
933
934
935
936
937
938
939
940 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
941 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
942 char *nodename;
943
944 create_one_flash("virt.flash0", flashbase, flashsize,
945 bios_name, secure_sysmem);
946 create_one_flash("virt.flash1", flashbase + flashsize, flashsize,
947 NULL, sysmem);
948
949 if (sysmem == secure_sysmem) {
950
951 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
952 qemu_fdt_add_subnode(vms->fdt, nodename);
953 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
954 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
955 2, flashbase, 2, flashsize,
956 2, flashbase + flashsize, 2, flashsize);
957 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
958 g_free(nodename);
959 } else {
960
961
962
963 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
964 qemu_fdt_add_subnode(vms->fdt, nodename);
965 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
966 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
967 2, flashbase, 2, flashsize);
968 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
969 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
970 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
971 g_free(nodename);
972
973 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
974 qemu_fdt_add_subnode(vms->fdt, nodename);
975 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
976 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
977 2, flashbase + flashsize, 2, flashsize);
978 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
979 g_free(nodename);
980 }
981}
982
983static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
984{
985 hwaddr base = vms->memmap[VIRT_FW_CFG].base;
986 hwaddr size = vms->memmap[VIRT_FW_CFG].size;
987 FWCfgState *fw_cfg;
988 char *nodename;
989
990 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
991 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
992
993 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
994 qemu_fdt_add_subnode(vms->fdt, nodename);
995 qemu_fdt_setprop_string(vms->fdt, nodename,
996 "compatible", "qemu,fw-cfg-mmio");
997 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
998 2, base, 2, size);
999 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
1000 g_free(nodename);
1001 return fw_cfg;
1002}
1003
1004static void create_pcie_irq_map(const VirtMachineState *vms,
1005 uint32_t gic_phandle,
1006 int first_irq, const char *nodename)
1007{
1008 int devfn, pin;
1009 uint32_t full_irq_map[4 * 4 * 10] = { 0 };
1010 uint32_t *irq_map = full_irq_map;
1011
1012 for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
1013 for (pin = 0; pin < 4; pin++) {
1014 int irq_type = GIC_FDT_IRQ_TYPE_SPI;
1015 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
1016 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1017 int i;
1018
1019 uint32_t map[] = {
1020 devfn << 8, 0, 0,
1021 pin + 1,
1022 gic_phandle, 0, 0, irq_type, irq_nr, irq_level };
1023
1024
1025 for (i = 0; i < 10; i++) {
1026 irq_map[i] = cpu_to_be32(map[i]);
1027 }
1028 irq_map += 10;
1029 }
1030 }
1031
1032 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map",
1033 full_irq_map, sizeof(full_irq_map));
1034
1035 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask",
1036 0x1800, 0, 0,
1037 0x7 );
1038}
1039
1040static void create_smmu(const VirtMachineState *vms, qemu_irq *pic,
1041 PCIBus *bus)
1042{
1043 char *node;
1044 const char compat[] = "arm,smmu-v3";
1045 int irq = vms->irqmap[VIRT_SMMU];
1046 int i;
1047 hwaddr base = vms->memmap[VIRT_SMMU].base;
1048 hwaddr size = vms->memmap[VIRT_SMMU].size;
1049 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1050 DeviceState *dev;
1051
1052 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1053 return;
1054 }
1055
1056 dev = qdev_create(NULL, "arm-smmuv3");
1057
1058 object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus",
1059 &error_abort);
1060 qdev_init_nofail(dev);
1061 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1062 for (i = 0; i < NUM_SMMU_IRQS; i++) {
1063 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
1064 }
1065
1066 node = g_strdup_printf("/smmuv3@%" PRIx64, base);
1067 qemu_fdt_add_subnode(vms->fdt, node);
1068 qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat));
1069 qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size);
1070
1071 qemu_fdt_setprop_cells(vms->fdt, node, "interrupts",
1072 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1073 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1074 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1075 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1076
1077 qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names,
1078 sizeof(irq_names));
1079
1080 qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle);
1081 qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk");
1082 qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0);
1083
1084 qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1);
1085
1086 qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle);
1087 g_free(node);
1088}
1089
1090static void create_pcie(VirtMachineState *vms, qemu_irq *pic)
1091{
1092 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1093 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1094 hwaddr base_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].base;
1095 hwaddr size_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].size;
1096 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1097 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1098 hwaddr base_ecam, size_ecam;
1099 hwaddr base = base_mmio;
1100 int nr_pcie_buses;
1101 int irq = vms->irqmap[VIRT_PCIE];
1102 MemoryRegion *mmio_alias;
1103 MemoryRegion *mmio_reg;
1104 MemoryRegion *ecam_alias;
1105 MemoryRegion *ecam_reg;
1106 DeviceState *dev;
1107 char *nodename;
1108 int i, ecam_id;
1109 PCIHostState *pci;
1110
1111 dev = qdev_create(NULL, TYPE_GPEX_HOST);
1112 qdev_init_nofail(dev);
1113
1114 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1115 base_ecam = vms->memmap[ecam_id].base;
1116 size_ecam = vms->memmap[ecam_id].size;
1117 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
1118
1119 ecam_alias = g_new0(MemoryRegion, 1);
1120 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1121 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1122 ecam_reg, 0, size_ecam);
1123 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1124
1125
1126
1127
1128
1129
1130 mmio_alias = g_new0(MemoryRegion, 1);
1131 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1132 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1133 mmio_reg, base_mmio, size_mmio);
1134 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1135
1136 if (vms->highmem) {
1137
1138 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1139
1140 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1141 mmio_reg, base_mmio_high, size_mmio_high);
1142 memory_region_add_subregion(get_system_memory(), base_mmio_high,
1143 high_mmio_alias);
1144 }
1145
1146
1147 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
1148
1149 for (i = 0; i < GPEX_NUM_IRQS; i++) {
1150 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
1151 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
1152 }
1153
1154 pci = PCI_HOST_BRIDGE(dev);
1155 if (pci->bus) {
1156 for (i = 0; i < nb_nics; i++) {
1157 NICInfo *nd = &nd_table[i];
1158
1159 if (!nd->model) {
1160 nd->model = g_strdup("virtio");
1161 }
1162
1163 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
1164 }
1165 }
1166
1167 nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1168 qemu_fdt_add_subnode(vms->fdt, nodename);
1169 qemu_fdt_setprop_string(vms->fdt, nodename,
1170 "compatible", "pci-host-ecam-generic");
1171 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci");
1172 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3);
1173 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2);
1174 qemu_fdt_setprop_cell(vms->fdt, nodename, "linux,pci-domain", 0);
1175 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0,
1176 nr_pcie_buses - 1);
1177 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
1178
1179 if (vms->msi_phandle) {
1180 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent",
1181 vms->msi_phandle);
1182 }
1183
1184 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
1185 2, base_ecam, 2, size_ecam);
1186
1187 if (vms->highmem) {
1188 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges",
1189 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1190 2, base_pio, 2, size_pio,
1191 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1192 2, base_mmio, 2, size_mmio,
1193 1, FDT_PCI_RANGE_MMIO_64BIT,
1194 2, base_mmio_high,
1195 2, base_mmio_high, 2, size_mmio_high);
1196 } else {
1197 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges",
1198 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1199 2, base_pio, 2, size_pio,
1200 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1201 2, base_mmio, 2, size_mmio);
1202 }
1203
1204 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1);
1205 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename);
1206
1207 if (vms->iommu) {
1208 vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt);
1209
1210 create_smmu(vms, pic, pci->bus);
1211
1212 qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map",
1213 0x0, vms->iommu_phandle, 0x0, 0x10000);
1214 }
1215
1216 g_free(nodename);
1217}
1218
1219static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic)
1220{
1221 DeviceState *dev;
1222 SysBusDevice *s;
1223 int i;
1224 MemoryRegion *sysmem = get_system_memory();
1225
1226 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
1227 dev->id = TYPE_PLATFORM_BUS_DEVICE;
1228 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1229 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1230 qdev_init_nofail(dev);
1231 vms->platform_bus_dev = dev;
1232
1233 s = SYS_BUS_DEVICE(dev);
1234 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
1235 int irqn = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1236 sysbus_connect_irq(s, i, pic[irqn]);
1237 }
1238
1239 memory_region_add_subregion(sysmem,
1240 vms->memmap[VIRT_PLATFORM_BUS].base,
1241 sysbus_mmio_get_region(s, 0));
1242}
1243
1244static void create_secure_ram(VirtMachineState *vms,
1245 MemoryRegion *secure_sysmem)
1246{
1247 MemoryRegion *secram = g_new(MemoryRegion, 1);
1248 char *nodename;
1249 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1250 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1251
1252 memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1253 &error_fatal);
1254 memory_region_add_subregion(secure_sysmem, base, secram);
1255
1256 nodename = g_strdup_printf("/secram@%" PRIx64, base);
1257 qemu_fdt_add_subnode(vms->fdt, nodename);
1258 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory");
1259 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size);
1260 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
1261 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
1262
1263 g_free(nodename);
1264}
1265
1266static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1267{
1268 const VirtMachineState *board = container_of(binfo, VirtMachineState,
1269 bootinfo);
1270
1271 *fdt_size = board->fdt_size;
1272 return board->fdt;
1273}
1274
1275static void virt_build_smbios(VirtMachineState *vms)
1276{
1277 MachineClass *mc = MACHINE_GET_CLASS(vms);
1278 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1279 uint8_t *smbios_tables, *smbios_anchor;
1280 size_t smbios_tables_len, smbios_anchor_len;
1281 const char *product = "QEMU Virtual Machine";
1282
1283 if (!vms->fw_cfg) {
1284 return;
1285 }
1286
1287 if (kvm_enabled()) {
1288 product = "KVM Virtual Machine";
1289 }
1290
1291 smbios_set_defaults("QEMU", product,
1292 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
1293 true, SMBIOS_ENTRY_POINT_30);
1294
1295 smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len,
1296 &smbios_anchor, &smbios_anchor_len);
1297
1298 if (smbios_anchor) {
1299 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1300 smbios_tables, smbios_tables_len);
1301 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1302 smbios_anchor, smbios_anchor_len);
1303 }
1304}
1305
1306static
1307void virt_machine_done(Notifier *notifier, void *data)
1308{
1309 VirtMachineState *vms = container_of(notifier, VirtMachineState,
1310 machine_done);
1311 ARMCPU *cpu = ARM_CPU(first_cpu);
1312 struct arm_boot_info *info = &vms->bootinfo;
1313 AddressSpace *as = arm_boot_address_space(cpu, info);
1314
1315
1316
1317
1318
1319
1320
1321
1322 if (info->dtb_filename == NULL) {
1323 platform_bus_add_all_fdt_nodes(vms->fdt, "/intc",
1324 vms->memmap[VIRT_PLATFORM_BUS].base,
1325 vms->memmap[VIRT_PLATFORM_BUS].size,
1326 vms->irqmap[VIRT_PLATFORM_BUS]);
1327 }
1328 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) {
1329 exit(1);
1330 }
1331
1332 virt_acpi_setup(vms);
1333 virt_build_smbios(vms);
1334}
1335
1336static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1337{
1338 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
1339 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1340
1341 if (!vmc->disallow_affinity_adjustment) {
1342
1343
1344
1345
1346
1347
1348
1349
1350 if (vms->gic_version == 3) {
1351 clustersz = GICV3_TARGETLIST_BITS;
1352 } else {
1353 clustersz = GIC_TARGETLIST_BITS;
1354 }
1355 }
1356 return arm_cpu_mp_affinity(idx, clustersz);
1357}
1358
1359static void machvirt_init(MachineState *machine)
1360{
1361 VirtMachineState *vms = VIRT_MACHINE(machine);
1362 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
1363 MachineClass *mc = MACHINE_GET_CLASS(machine);
1364 const CPUArchIdList *possible_cpus;
1365 qemu_irq pic[NUM_IRQS];
1366 MemoryRegion *sysmem = get_system_memory();
1367 MemoryRegion *secure_sysmem = NULL;
1368 int n, virt_max_cpus;
1369 MemoryRegion *ram = g_new(MemoryRegion, 1);
1370 bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);
1371 bool aarch64 = true;
1372
1373
1374
1375
1376 if (vms->gic_version <= 0) {
1377
1378 if (!kvm_enabled()) {
1379 if (vms->gic_version == 0) {
1380 error_report("gic-version=host requires KVM");
1381 exit(1);
1382 } else {
1383
1384 vms->gic_version = 3;
1385 }
1386 } else {
1387 vms->gic_version = kvm_arm_vgic_probe();
1388 if (!vms->gic_version) {
1389 error_report(
1390 "Unable to determine GIC version supported by host");
1391 exit(1);
1392 }
1393 }
1394 }
1395
1396 if (!cpu_type_valid(machine->cpu_type)) {
1397 error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
1398 exit(1);
1399 }
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411 if (vms->secure && firmware_loaded) {
1412 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
1413 } else if (vms->virt) {
1414 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
1415 } else {
1416 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
1417 }
1418
1419
1420
1421
1422 if (vms->gic_version == 3) {
1423 virt_max_cpus = vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
1424 virt_max_cpus += vms->memmap[VIRT_GIC_REDIST2].size / GICV3_REDIST_SIZE;
1425 } else {
1426 virt_max_cpus = GIC_NCPU;
1427 }
1428
1429 if (max_cpus > virt_max_cpus) {
1430 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1431 "supported by machine 'mach-virt' (%d)",
1432 max_cpus, virt_max_cpus);
1433 exit(1);
1434 }
1435
1436 vms->smp_cpus = smp_cpus;
1437
1438 if (machine->ram_size > vms->memmap[VIRT_MEM].size) {
1439 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB);
1440 exit(1);
1441 }
1442
1443 if (vms->virt && kvm_enabled()) {
1444 error_report("mach-virt: KVM does not support providing "
1445 "Virtualization extensions to the guest CPU");
1446 exit(1);
1447 }
1448
1449 if (vms->secure) {
1450 if (kvm_enabled()) {
1451 error_report("mach-virt: KVM does not support Security extensions");
1452 exit(1);
1453 }
1454
1455
1456
1457
1458
1459
1460 secure_sysmem = g_new(MemoryRegion, 1);
1461 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
1462 UINT64_MAX);
1463 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
1464 }
1465
1466 create_fdt(vms);
1467
1468 possible_cpus = mc->possible_cpu_arch_ids(machine);
1469 for (n = 0; n < possible_cpus->len; n++) {
1470 Object *cpuobj;
1471 CPUState *cs;
1472
1473 if (n >= smp_cpus) {
1474 break;
1475 }
1476
1477 cpuobj = object_new(possible_cpus->cpus[n].type);
1478 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id,
1479 "mp-affinity", NULL);
1480
1481 cs = CPU(cpuobj);
1482 cs->cpu_index = n;
1483
1484 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
1485 &error_fatal);
1486
1487 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
1488
1489 if (!vms->secure) {
1490 object_property_set_bool(cpuobj, false, "has_el3", NULL);
1491 }
1492
1493 if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) {
1494 object_property_set_bool(cpuobj, false, "has_el2", NULL);
1495 }
1496
1497 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
1498 object_property_set_int(cpuobj, vms->psci_conduit,
1499 "psci-conduit", NULL);
1500
1501
1502 if (n > 0) {
1503 object_property_set_bool(cpuobj, true,
1504 "start-powered-off", NULL);
1505 }
1506 }
1507
1508 if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) {
1509 object_property_set_bool(cpuobj, false, "pmu", NULL);
1510 }
1511
1512 if (object_property_find(cpuobj, "reset-cbar", NULL)) {
1513 object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base,
1514 "reset-cbar", &error_abort);
1515 }
1516
1517 object_property_set_link(cpuobj, OBJECT(sysmem), "memory",
1518 &error_abort);
1519 if (vms->secure) {
1520 object_property_set_link(cpuobj, OBJECT(secure_sysmem),
1521 "secure-memory", &error_abort);
1522 }
1523
1524 object_property_set_bool(cpuobj, true, "realized", &error_fatal);
1525 object_unref(cpuobj);
1526 }
1527 fdt_add_timer_nodes(vms);
1528 fdt_add_cpu_nodes(vms);
1529
1530 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram",
1531 machine->ram_size);
1532 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram);
1533
1534 create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem);
1535
1536 create_gic(vms, pic);
1537
1538 fdt_add_pmu_nodes(vms);
1539
1540 create_uart(vms, pic, VIRT_UART, sysmem, serial_hd(0));
1541
1542 if (vms->secure) {
1543 create_secure_ram(vms, secure_sysmem);
1544 create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1));
1545 }
1546
1547 vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64);
1548
1549 create_rtc(vms, pic);
1550
1551 create_pcie(vms, pic);
1552
1553 create_gpio(vms, pic);
1554
1555
1556
1557
1558
1559 create_virtio_devices(vms, pic);
1560
1561 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
1562 rom_set_fw(vms->fw_cfg);
1563
1564 create_platform_bus(vms, pic);
1565
1566 vms->bootinfo.ram_size = machine->ram_size;
1567 vms->bootinfo.kernel_filename = machine->kernel_filename;
1568 vms->bootinfo.kernel_cmdline = machine->kernel_cmdline;
1569 vms->bootinfo.initrd_filename = machine->initrd_filename;
1570 vms->bootinfo.nb_cpus = smp_cpus;
1571 vms->bootinfo.board_id = -1;
1572 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
1573 vms->bootinfo.get_dtb = machvirt_dtb;
1574 vms->bootinfo.skip_dtb_autoload = true;
1575 vms->bootinfo.firmware_loaded = firmware_loaded;
1576 arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo);
1577
1578 vms->machine_done.notify = virt_machine_done;
1579 qemu_add_machine_init_done_notifier(&vms->machine_done);
1580}
1581
1582static bool virt_get_secure(Object *obj, Error **errp)
1583{
1584 VirtMachineState *vms = VIRT_MACHINE(obj);
1585
1586 return vms->secure;
1587}
1588
1589static void virt_set_secure(Object *obj, bool value, Error **errp)
1590{
1591 VirtMachineState *vms = VIRT_MACHINE(obj);
1592
1593 vms->secure = value;
1594}
1595
1596static bool virt_get_virt(Object *obj, Error **errp)
1597{
1598 VirtMachineState *vms = VIRT_MACHINE(obj);
1599
1600 return vms->virt;
1601}
1602
1603static void virt_set_virt(Object *obj, bool value, Error **errp)
1604{
1605 VirtMachineState *vms = VIRT_MACHINE(obj);
1606
1607 vms->virt = value;
1608}
1609
1610static bool virt_get_highmem(Object *obj, Error **errp)
1611{
1612 VirtMachineState *vms = VIRT_MACHINE(obj);
1613
1614 return vms->highmem;
1615}
1616
1617static void virt_set_highmem(Object *obj, bool value, Error **errp)
1618{
1619 VirtMachineState *vms = VIRT_MACHINE(obj);
1620
1621 vms->highmem = value;
1622}
1623
1624static bool virt_get_its(Object *obj, Error **errp)
1625{
1626 VirtMachineState *vms = VIRT_MACHINE(obj);
1627
1628 return vms->its;
1629}
1630
1631static void virt_set_its(Object *obj, bool value, Error **errp)
1632{
1633 VirtMachineState *vms = VIRT_MACHINE(obj);
1634
1635 vms->its = value;
1636}
1637
1638static char *virt_get_gic_version(Object *obj, Error **errp)
1639{
1640 VirtMachineState *vms = VIRT_MACHINE(obj);
1641 const char *val = vms->gic_version == 3 ? "3" : "2";
1642
1643 return g_strdup(val);
1644}
1645
1646static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
1647{
1648 VirtMachineState *vms = VIRT_MACHINE(obj);
1649
1650 if (!strcmp(value, "3")) {
1651 vms->gic_version = 3;
1652 } else if (!strcmp(value, "2")) {
1653 vms->gic_version = 2;
1654 } else if (!strcmp(value, "host")) {
1655 vms->gic_version = 0;
1656 } else if (!strcmp(value, "max")) {
1657 vms->gic_version = -1;
1658 } else {
1659 error_setg(errp, "Invalid gic-version value");
1660 error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
1661 }
1662}
1663
1664static char *virt_get_iommu(Object *obj, Error **errp)
1665{
1666 VirtMachineState *vms = VIRT_MACHINE(obj);
1667
1668 switch (vms->iommu) {
1669 case VIRT_IOMMU_NONE:
1670 return g_strdup("none");
1671 case VIRT_IOMMU_SMMUV3:
1672 return g_strdup("smmuv3");
1673 default:
1674 g_assert_not_reached();
1675 }
1676}
1677
1678static void virt_set_iommu(Object *obj, const char *value, Error **errp)
1679{
1680 VirtMachineState *vms = VIRT_MACHINE(obj);
1681
1682 if (!strcmp(value, "smmuv3")) {
1683 vms->iommu = VIRT_IOMMU_SMMUV3;
1684 } else if (!strcmp(value, "none")) {
1685 vms->iommu = VIRT_IOMMU_NONE;
1686 } else {
1687 error_setg(errp, "Invalid iommu value");
1688 error_append_hint(errp, "Valid values are none, smmuv3.\n");
1689 }
1690}
1691
1692static CpuInstanceProperties
1693virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
1694{
1695 MachineClass *mc = MACHINE_GET_CLASS(ms);
1696 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
1697
1698 assert(cpu_index < possible_cpus->len);
1699 return possible_cpus->cpus[cpu_index].props;
1700}
1701
1702static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
1703{
1704 return idx % nb_numa_nodes;
1705}
1706
1707static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
1708{
1709 int n;
1710 VirtMachineState *vms = VIRT_MACHINE(ms);
1711
1712 if (ms->possible_cpus) {
1713 assert(ms->possible_cpus->len == max_cpus);
1714 return ms->possible_cpus;
1715 }
1716
1717 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
1718 sizeof(CPUArchId) * max_cpus);
1719 ms->possible_cpus->len = max_cpus;
1720 for (n = 0; n < ms->possible_cpus->len; n++) {
1721 ms->possible_cpus->cpus[n].type = ms->cpu_type;
1722 ms->possible_cpus->cpus[n].arch_id =
1723 virt_cpu_mp_affinity(vms, n);
1724 ms->possible_cpus->cpus[n].props.has_thread_id = true;
1725 ms->possible_cpus->cpus[n].props.thread_id = n;
1726 }
1727 return ms->possible_cpus;
1728}
1729
1730static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1731 DeviceState *dev, Error **errp)
1732{
1733 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
1734
1735 if (vms->platform_bus_dev) {
1736 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
1737 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
1738 SYS_BUS_DEVICE(dev));
1739 }
1740 }
1741}
1742
1743static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
1744 DeviceState *dev)
1745{
1746 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
1747 return HOTPLUG_HANDLER(machine);
1748 }
1749
1750 return NULL;
1751}
1752
1753static void virt_machine_class_init(ObjectClass *oc, void *data)
1754{
1755 MachineClass *mc = MACHINE_CLASS(oc);
1756 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1757
1758 mc->init = machvirt_init;
1759
1760
1761
1762
1763 mc->max_cpus = 512;
1764 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
1765 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
1766 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
1767 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM);
1768 mc->block_default_type = IF_VIRTIO;
1769 mc->no_cdrom = 1;
1770 mc->pci_allow_0_address = true;
1771
1772 mc->minimum_page_bits = 12;
1773 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
1774 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
1775 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
1776 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
1777 assert(!mc->get_hotplug_handler);
1778 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
1779 hc->plug = virt_machine_device_plug_cb;
1780}
1781
1782static const TypeInfo virt_machine_info = {
1783 .name = TYPE_VIRT_MACHINE,
1784 .parent = TYPE_MACHINE,
1785 .abstract = true,
1786 .instance_size = sizeof(VirtMachineState),
1787 .class_size = sizeof(VirtMachineClass),
1788 .class_init = virt_machine_class_init,
1789 .interfaces = (InterfaceInfo[]) {
1790 { TYPE_HOTPLUG_HANDLER },
1791 { }
1792 },
1793};
1794
1795static void machvirt_machine_init(void)
1796{
1797 type_register_static(&virt_machine_info);
1798}
1799type_init(machvirt_machine_init);
1800
1801static void virt_3_1_instance_init(Object *obj)
1802{
1803 VirtMachineState *vms = VIRT_MACHINE(obj);
1804 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1805
1806
1807
1808
1809
1810 vms->secure = false;
1811 object_property_add_bool(obj, "secure", virt_get_secure,
1812 virt_set_secure, NULL);
1813 object_property_set_description(obj, "secure",
1814 "Set on/off to enable/disable the ARM "
1815 "Security Extensions (TrustZone)",
1816 NULL);
1817
1818
1819 vms->virt = false;
1820 object_property_add_bool(obj, "virtualization", virt_get_virt,
1821 virt_set_virt, NULL);
1822 object_property_set_description(obj, "virtualization",
1823 "Set on/off to enable/disable emulating a "
1824 "guest CPU which implements the ARM "
1825 "Virtualization Extensions",
1826 NULL);
1827
1828
1829 vms->highmem = true;
1830 object_property_add_bool(obj, "highmem", virt_get_highmem,
1831 virt_set_highmem, NULL);
1832 object_property_set_description(obj, "highmem",
1833 "Set on/off to enable/disable using "
1834 "physical address space above 32 bits",
1835 NULL);
1836
1837 vms->gic_version = 2;
1838 object_property_add_str(obj, "gic-version", virt_get_gic_version,
1839 virt_set_gic_version, NULL);
1840 object_property_set_description(obj, "gic-version",
1841 "Set GIC version. "
1842 "Valid values are 2, 3 and host", NULL);
1843
1844 vms->highmem_ecam = !vmc->no_highmem_ecam;
1845
1846 if (vmc->no_its) {
1847 vms->its = false;
1848 } else {
1849
1850 vms->its = true;
1851 object_property_add_bool(obj, "its", virt_get_its,
1852 virt_set_its, NULL);
1853 object_property_set_description(obj, "its",
1854 "Set on/off to enable/disable "
1855 "ITS instantiation",
1856 NULL);
1857 }
1858
1859
1860 vms->iommu = VIRT_IOMMU_NONE;
1861 object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu, NULL);
1862 object_property_set_description(obj, "iommu",
1863 "Set the IOMMU type. "
1864 "Valid values are none and smmuv3",
1865 NULL);
1866
1867 vms->memmap = a15memmap;
1868 vms->irqmap = a15irqmap;
1869}
1870
1871static void virt_machine_3_1_options(MachineClass *mc)
1872{
1873}
1874DEFINE_VIRT_MACHINE_AS_LATEST(3, 1)
1875
1876#define VIRT_COMPAT_3_0 \
1877 HW_COMPAT_3_0
1878
1879static void virt_3_0_instance_init(Object *obj)
1880{
1881 virt_3_1_instance_init(obj);
1882}
1883
1884static void virt_machine_3_0_options(MachineClass *mc)
1885{
1886 virt_machine_3_1_options(mc);
1887 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_3_0);
1888}
1889DEFINE_VIRT_MACHINE(3, 0)
1890
1891#define VIRT_COMPAT_2_12 \
1892 HW_COMPAT_2_12
1893
1894static void virt_2_12_instance_init(Object *obj)
1895{
1896 virt_3_0_instance_init(obj);
1897}
1898
1899static void virt_machine_2_12_options(MachineClass *mc)
1900{
1901 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
1902
1903 virt_machine_3_0_options(mc);
1904 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_12);
1905 vmc->no_highmem_ecam = true;
1906 mc->max_cpus = 255;
1907}
1908DEFINE_VIRT_MACHINE(2, 12)
1909
1910#define VIRT_COMPAT_2_11 \
1911 HW_COMPAT_2_11
1912
1913static void virt_2_11_instance_init(Object *obj)
1914{
1915 virt_2_12_instance_init(obj);
1916}
1917
1918static void virt_machine_2_11_options(MachineClass *mc)
1919{
1920 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
1921
1922 virt_machine_2_12_options(mc);
1923 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_11);
1924 vmc->smbios_old_sys_ver = true;
1925}
1926DEFINE_VIRT_MACHINE(2, 11)
1927
1928#define VIRT_COMPAT_2_10 \
1929 HW_COMPAT_2_10
1930
1931static void virt_2_10_instance_init(Object *obj)
1932{
1933 virt_2_11_instance_init(obj);
1934}
1935
1936static void virt_machine_2_10_options(MachineClass *mc)
1937{
1938 virt_machine_2_11_options(mc);
1939 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_10);
1940
1941 mc->ignore_memory_transaction_failures = true;
1942}
1943DEFINE_VIRT_MACHINE(2, 10)
1944
1945#define VIRT_COMPAT_2_9 \
1946 HW_COMPAT_2_9
1947
1948static void virt_2_9_instance_init(Object *obj)
1949{
1950 virt_2_10_instance_init(obj);
1951}
1952
1953static void virt_machine_2_9_options(MachineClass *mc)
1954{
1955 virt_machine_2_10_options(mc);
1956 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_9);
1957}
1958DEFINE_VIRT_MACHINE(2, 9)
1959
1960#define VIRT_COMPAT_2_8 \
1961 HW_COMPAT_2_8
1962
1963static void virt_2_8_instance_init(Object *obj)
1964{
1965 virt_2_9_instance_init(obj);
1966}
1967
1968static void virt_machine_2_8_options(MachineClass *mc)
1969{
1970 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
1971
1972 virt_machine_2_9_options(mc);
1973 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_8);
1974
1975
1976
1977 vmc->claim_edge_triggered_timers = true;
1978}
1979DEFINE_VIRT_MACHINE(2, 8)
1980
1981#define VIRT_COMPAT_2_7 \
1982 HW_COMPAT_2_7
1983
1984static void virt_2_7_instance_init(Object *obj)
1985{
1986 virt_2_8_instance_init(obj);
1987}
1988
1989static void virt_machine_2_7_options(MachineClass *mc)
1990{
1991 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
1992
1993 virt_machine_2_8_options(mc);
1994 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_7);
1995
1996 vmc->no_its = true;
1997
1998 mc->minimum_page_bits = 0;
1999}
2000DEFINE_VIRT_MACHINE(2, 7)
2001
2002#define VIRT_COMPAT_2_6 \
2003 HW_COMPAT_2_6
2004
2005static void virt_2_6_instance_init(Object *obj)
2006{
2007 virt_2_7_instance_init(obj);
2008}
2009
2010static void virt_machine_2_6_options(MachineClass *mc)
2011{
2012 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2013
2014 virt_machine_2_7_options(mc);
2015 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6);
2016 vmc->disallow_affinity_adjustment = true;
2017
2018 vmc->no_pmu = true;
2019}
2020DEFINE_VIRT_MACHINE(2, 6)
2021