LXR qemu/hw/cpu/a15mpcore.c

   1/*
   2 * Cortex-A15MPCore internal peripheral emulation.
   3 *
   4 * Copyright (c) 2012 Linaro Limited.
   5 * Written by Peter Maydell.
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; either version 2 of the License, or
  10 * (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License along
  18 * with this program; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "qapi/error.h"
  23#include "hw/cpu/a15mpcore.h"
  24#include "sysemu/kvm.h"
  25#include "kvm_arm.h"
  26
  27static void a15mp_priv_set_irq(void *opaque, int irq, int level)
  28{
  29    A15MPPrivState *s = (A15MPPrivState *)opaque;
  30
  31    qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
  32}
  33
  34static void a15mp_priv_initfn(Object *obj)
  35{
  36    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
  37    A15MPPrivState *s = A15MPCORE_PRIV(obj);
  38
  39    memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000);
  40    sysbus_init_mmio(sbd, &s->container);
  41
  42    sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
  43                          gic_class_name());
  44    qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
  45}
  46
  47static void a15mp_priv_realize(DeviceState *dev, Error **errp)
  48{
  49    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
  50    A15MPPrivState *s = A15MPCORE_PRIV(dev);
  51    DeviceState *gicdev;
  52    SysBusDevice *busdev;
  53    int i;
  54    Error *err = NULL;
  55    bool has_el3;
  56    bool has_el2 = false;
  57    Object *cpuobj;
  58
  59    gicdev = DEVICE(&s->gic);
  60    qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
  61    qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
  62
  63    if (!kvm_irqchip_in_kernel()) {
  64        /* Make the GIC's TZ support match the CPUs. We assume that
  65         * either all the CPUs have TZ, or none do.
  66         */
  67        cpuobj = OBJECT(qemu_get_cpu(0));
  68        has_el3 = object_property_find(cpuobj, "has_el3", NULL) &&
  69            object_property_get_bool(cpuobj, "has_el3", &error_abort);
  70        qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
  71        /* Similarly for virtualization support */
  72        has_el2 = object_property_find(cpuobj, "has_el2", NULL) &&
  73            object_property_get_bool(cpuobj, "has_el2", &error_abort);
  74        qdev_prop_set_bit(gicdev, "has-virtualization-extensions", has_el2);
  75    }
  76
  77    object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
  78    if (err != NULL) {
  79        error_propagate(errp, err);
  80        return;
  81    }
  82    busdev = SYS_BUS_DEVICE(&s->gic);
  83
  84    /* Pass through outbound IRQ lines from the GIC */
  85    sysbus_pass_irq(sbd, busdev);
  86
  87    /* Pass through inbound GPIO lines to the GIC */
  88    qdev_init_gpio_in(dev, a15mp_priv_set_irq, s->num_irq - 32);
  89
  90    /* Wire the outputs from each CPU's generic timer to the
  91     * appropriate GIC PPI inputs
  92     */
  93    for (i = 0; i < s->num_cpu; i++) {
  94        DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
  95        int ppibase = s->num_irq - 32 + i * 32;
  96        int irq;
  97        /* Mapping from the output timer irq lines from the CPU to the
  98         * GIC PPI inputs used on the A15:
  99         */
 100        const int timer_irq[] = {
 101            [GTIMER_PHYS] = 30,
 102            [GTIMER_VIRT] = 27,
 103            [GTIMER_HYP]  = 26,
 104            [GTIMER_SEC]  = 29,
 105        };
 106        for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
 107            qdev_connect_gpio_out(cpudev, irq,
 108                                  qdev_get_gpio_in(gicdev,
 109                                                   ppibase + timer_irq[irq]));
 110        }
 111        if (has_el2) {
 112            /* Connect the GIC maintenance interrupt to PPI ID 25 */
 113            sysbus_connect_irq(SYS_BUS_DEVICE(gicdev), i + 4 * s->num_cpu,
 114                               qdev_get_gpio_in(gicdev, ppibase + 25));
 115        }
 116    }
 117
 118    /* Memory map (addresses are offsets from PERIPHBASE):
 119     *  0x0000-0x0fff -- reserved
 120     *  0x1000-0x1fff -- GIC Distributor
 121     *  0x2000-0x3fff -- GIC CPU interface
 122     *  0x4000-0x4fff -- GIC virtual interface control for this CPU
 123     *  0x5000-0x51ff -- GIC virtual interface control for CPU 0
 124     *  0x5200-0x53ff -- GIC virtual interface control for CPU 1
 125     *  0x5400-0x55ff -- GIC virtual interface control for CPU 2
 126     *  0x5600-0x57ff -- GIC virtual interface control for CPU 3
 127     *  0x6000-0x7fff -- GIC virtual CPU interface
 128     */
 129    memory_region_add_subregion(&s->container, 0x1000,
 130                                sysbus_mmio_get_region(busdev, 0));
 131    memory_region_add_subregion(&s->container, 0x2000,
 132                                sysbus_mmio_get_region(busdev, 1));
 133    if (has_el2) {
 134        memory_region_add_subregion(&s->container, 0x4000,
 135                                    sysbus_mmio_get_region(busdev, 2));
 136        memory_region_add_subregion(&s->container, 0x6000,
 137                                    sysbus_mmio_get_region(busdev, 3));
 138        for (i = 0; i < s->num_cpu; i++) {
 139            hwaddr base = 0x5000 + i * 0x200;
 140            MemoryRegion *mr = sysbus_mmio_get_region(busdev,
 141                                                      4 + s->num_cpu + i);
 142            memory_region_add_subregion(&s->container, base, mr);
 143        }
 144    }
 145}
 146
 147static Property a15mp_priv_properties[] = {
 148    DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1),
 149    /* The Cortex-A15MP may have anything from 0 to 224 external interrupt
 150     * IRQ lines (with another 32 internal). We default to 128+32, which
 151     * is the number provided by the Cortex-A15MP test chip in the
 152     * Versatile Express A15 development board.
 153     * Other boards may differ and should set this property appropriately.
 154     */
 155    DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160),
 156    DEFINE_PROP_END_OF_LIST(),
 157};
 158
 159static void a15mp_priv_class_init(ObjectClass *klass, void *data)
 160{
 161    DeviceClass *dc = DEVICE_CLASS(klass);
 162
 163    dc->realize = a15mp_priv_realize;
 164    dc->props = a15mp_priv_properties;
 165    /* We currently have no savable state */
 166}
 167
 168static const TypeInfo a15mp_priv_info = {
 169    .name  = TYPE_A15MPCORE_PRIV,
 170    .parent = TYPE_SYS_BUS_DEVICE,
 171    .instance_size  = sizeof(A15MPPrivState),
 172    .instance_init = a15mp_priv_initfn,
 173    .class_init = a15mp_priv_class_init,
 174};
 175
 176static void a15mp_register_types(void)
 177{
 178    type_register_static(&a15mp_priv_info);
 179}
 180
 181type_init(a15mp_register_types)
 182