1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23#include "qemu/osdep.h"
24#include "qapi/error.h"
25#include "qapi/qmp/qnum.h"
26#include "acpi-build.h"
27#include "qemu-common.h"
28#include "qemu/bitmap.h"
29#include "qemu/error-report.h"
30#include "hw/pci/pci.h"
31#include "qom/cpu.h"
32#include "target/i386/cpu.h"
33#include "hw/misc/pvpanic.h"
34#include "hw/timer/hpet.h"
35#include "hw/acpi/acpi-defs.h"
36#include "hw/acpi/acpi.h"
37#include "hw/acpi/cpu.h"
38#include "hw/nvram/fw_cfg.h"
39#include "hw/acpi/bios-linker-loader.h"
40#include "hw/loader.h"
41#include "hw/isa/isa.h"
42#include "hw/block/fdc.h"
43#include "hw/acpi/memory_hotplug.h"
44#include "sysemu/tpm.h"
45#include "hw/acpi/tpm.h"
46#include "hw/acpi/vmgenid.h"
47#include "sysemu/tpm_backend.h"
48#include "hw/timer/mc146818rtc_regs.h"
49#include "hw/mem/memory-device.h"
50#include "sysemu/numa.h"
51
52
53#include "hw/acpi/piix4.h"
54#include "hw/acpi/pcihp.h"
55#include "hw/i386/ich9.h"
56#include "hw/pci/pci_bus.h"
57#include "hw/pci-host/q35.h"
58#include "hw/i386/x86-iommu.h"
59
60#include "hw/acpi/aml-build.h"
61
62#include "qom/qom-qobject.h"
63#include "hw/i386/amd_iommu.h"
64#include "hw/i386/intel_iommu.h"
65
66#include "hw/acpi/ipmi.h"
67
68
69
70
71
72
73#define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
74#define ACPI_BUILD_ALIGN_SIZE 0x1000
75
76#define ACPI_BUILD_TABLE_SIZE 0x20000
77
78
79#ifdef DEBUG_ACPI_BUILD
80#define ACPI_BUILD_DPRINTF(fmt, ...) \
81 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
82#else
83#define ACPI_BUILD_DPRINTF(fmt, ...)
84#endif
85
86
87#define ACPI_BUILD_IOAPIC_ID 0x0
88
89typedef struct AcpiMcfgInfo {
90 uint64_t mcfg_base;
91 uint32_t mcfg_size;
92} AcpiMcfgInfo;
93
94typedef struct AcpiPmInfo {
95 bool s3_disabled;
96 bool s4_disabled;
97 bool pcihp_bridge_en;
98 uint8_t s4_val;
99 AcpiFadtData fadt;
100 uint16_t cpu_hp_io_base;
101 uint16_t pcihp_io_base;
102 uint16_t pcihp_io_len;
103} AcpiPmInfo;
104
105typedef struct AcpiMiscInfo {
106 bool is_piix4;
107 bool has_hpet;
108 TPMVersion tpm_version;
109 const unsigned char *dsdt_code;
110 unsigned dsdt_size;
111 uint16_t pvpanic_port;
112 uint16_t applesmc_io_base;
113} AcpiMiscInfo;
114
115typedef struct AcpiBuildPciBusHotplugState {
116 GArray *device_table;
117 GArray *notify_table;
118 struct AcpiBuildPciBusHotplugState *parent;
119 bool pcihp_bridge_en;
120} AcpiBuildPciBusHotplugState;
121
122static void init_common_fadt_data(Object *o, AcpiFadtData *data)
123{
124 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
125 AmlAddressSpace as = AML_AS_SYSTEM_IO;
126 AcpiFadtData fadt = {
127 .rev = 3,
128 .flags =
129 (1 << ACPI_FADT_F_WBINVD) |
130 (1 << ACPI_FADT_F_PROC_C1) |
131 (1 << ACPI_FADT_F_SLP_BUTTON) |
132 (1 << ACPI_FADT_F_RTC_S4) |
133 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
134
135
136
137
138 ((max_cpus > 8) ? (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
139 .int_model = 1 ,
140 .rtc_century = RTC_CENTURY,
141 .plvl2_lat = 0xfff ,
142 .plvl3_lat = 0xfff ,
143 .smi_cmd = ACPI_PORT_SMI_CMD,
144 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
145 .acpi_enable_cmd =
146 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL),
147 .acpi_disable_cmd =
148 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL),
149 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
150 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
151 .address = io + 0x04 },
152 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
153 .gpe0_blk = { .space_id = as, .bit_width =
154 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
155 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
156 },
157 };
158 *data = fadt;
159}
160
161static void acpi_get_pm_info(AcpiPmInfo *pm)
162{
163 Object *piix = piix4_pm_find();
164 Object *lpc = ich9_lpc_find();
165 Object *obj = piix ? piix : lpc;
166 QObject *o;
167 pm->cpu_hp_io_base = 0;
168 pm->pcihp_io_base = 0;
169 pm->pcihp_io_len = 0;
170
171 init_common_fadt_data(obj, &pm->fadt);
172 if (piix) {
173
174 pm->fadt.rev = 1;
175 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
176 pm->pcihp_io_base =
177 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
178 pm->pcihp_io_len =
179 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
180 }
181 if (lpc) {
182 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
183 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
184 pm->fadt.reset_reg = r;
185 pm->fadt.reset_val = 0xf;
186 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
187 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
188 }
189 assert(obj);
190
191
192
193 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT);
194
195
196 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
197 if (o) {
198 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
199 } else {
200 pm->s3_disabled = false;
201 }
202 qobject_unref(o);
203 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
204 if (o) {
205 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
206 } else {
207 pm->s4_disabled = false;
208 }
209 qobject_unref(o);
210 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
211 if (o) {
212 pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
213 } else {
214 pm->s4_val = false;
215 }
216 qobject_unref(o);
217
218 pm->pcihp_bridge_en =
219 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
220 NULL);
221}
222
223static void acpi_get_misc_info(AcpiMiscInfo *info)
224{
225 Object *piix = piix4_pm_find();
226 Object *lpc = ich9_lpc_find();
227 assert(!!piix != !!lpc);
228
229 if (piix) {
230 info->is_piix4 = true;
231 }
232 if (lpc) {
233 info->is_piix4 = false;
234 }
235
236 info->has_hpet = hpet_find();
237 info->tpm_version = tpm_get_version(tpm_find());
238 info->pvpanic_port = pvpanic_port();
239 info->applesmc_io_base = applesmc_port();
240}
241
242
243
244
245
246static Object *acpi_get_i386_pci_host(void)
247{
248 PCIHostState *host;
249
250 host = OBJECT_CHECK(PCIHostState,
251 object_resolve_path("/machine/i440fx", NULL),
252 TYPE_PCI_HOST_BRIDGE);
253 if (!host) {
254 host = OBJECT_CHECK(PCIHostState,
255 object_resolve_path("/machine/q35", NULL),
256 TYPE_PCI_HOST_BRIDGE);
257 }
258
259 return OBJECT(host);
260}
261
262static void acpi_get_pci_holes(Range *hole, Range *hole64)
263{
264 Object *pci_host;
265
266 pci_host = acpi_get_i386_pci_host();
267 g_assert(pci_host);
268
269 range_set_bounds1(hole,
270 object_property_get_uint(pci_host,
271 PCI_HOST_PROP_PCI_HOLE_START,
272 NULL),
273 object_property_get_uint(pci_host,
274 PCI_HOST_PROP_PCI_HOLE_END,
275 NULL));
276 range_set_bounds1(hole64,
277 object_property_get_uint(pci_host,
278 PCI_HOST_PROP_PCI_HOLE64_START,
279 NULL),
280 object_property_get_uint(pci_host,
281 PCI_HOST_PROP_PCI_HOLE64_END,
282 NULL));
283}
284
285static void acpi_align_size(GArray *blob, unsigned align)
286{
287
288
289
290 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
291}
292
293
294static void
295build_facs(GArray *table_data, BIOSLinker *linker)
296{
297 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
298 memcpy(&facs->signature, "FACS", 4);
299 facs->length = cpu_to_le32(sizeof(*facs));
300}
301
302void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
303 const CPUArchIdList *apic_ids, GArray *entry)
304{
305 uint32_t apic_id = apic_ids->cpus[uid].arch_id;
306
307
308
309
310
311
312
313 if (apic_id < 255) {
314 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic);
315
316 apic->type = ACPI_APIC_PROCESSOR;
317 apic->length = sizeof(*apic);
318 apic->processor_id = uid;
319 apic->local_apic_id = apic_id;
320 if (apic_ids->cpus[uid].cpu != NULL) {
321 apic->flags = cpu_to_le32(1);
322 } else {
323 apic->flags = cpu_to_le32(0);
324 }
325 } else {
326 AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic);
327
328 apic->type = ACPI_APIC_LOCAL_X2APIC;
329 apic->length = sizeof(*apic);
330 apic->uid = cpu_to_le32(uid);
331 apic->x2apic_id = cpu_to_le32(apic_id);
332 if (apic_ids->cpus[uid].cpu != NULL) {
333 apic->flags = cpu_to_le32(1);
334 } else {
335 apic->flags = cpu_to_le32(0);
336 }
337 }
338}
339
340static void
341build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
342{
343 MachineClass *mc = MACHINE_GET_CLASS(pcms);
344 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
345 int madt_start = table_data->len;
346 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev);
347 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev);
348 bool x2apic_mode = false;
349
350 AcpiMultipleApicTable *madt;
351 AcpiMadtIoApic *io_apic;
352 AcpiMadtIntsrcovr *intsrcovr;
353 int i;
354
355 madt = acpi_data_push(table_data, sizeof *madt);
356 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
357 madt->flags = cpu_to_le32(1);
358
359 for (i = 0; i < apic_ids->len; i++) {
360 adevc->madt_cpu(adev, i, apic_ids, table_data);
361 if (apic_ids->cpus[i].arch_id > 254) {
362 x2apic_mode = true;
363 }
364 }
365
366 io_apic = acpi_data_push(table_data, sizeof *io_apic);
367 io_apic->type = ACPI_APIC_IO;
368 io_apic->length = sizeof(*io_apic);
369 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
370 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
371 io_apic->interrupt = cpu_to_le32(0);
372
373 if (pcms->apic_xrupt_override) {
374 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
375 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
376 intsrcovr->length = sizeof(*intsrcovr);
377 intsrcovr->source = 0;
378 intsrcovr->gsi = cpu_to_le32(2);
379 intsrcovr->flags = cpu_to_le16(0);
380 }
381 for (i = 1; i < 16; i++) {
382#define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
383 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
384
385 continue;
386 }
387 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
388 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
389 intsrcovr->length = sizeof(*intsrcovr);
390 intsrcovr->source = i;
391 intsrcovr->gsi = cpu_to_le32(i);
392 intsrcovr->flags = cpu_to_le16(0xd);
393 }
394
395 if (x2apic_mode) {
396 AcpiMadtLocalX2ApicNmi *local_nmi;
397
398 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
399 local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI;
400 local_nmi->length = sizeof(*local_nmi);
401 local_nmi->uid = 0xFFFFFFFF;
402 local_nmi->flags = cpu_to_le16(0);
403 local_nmi->lint = 1;
404 } else {
405 AcpiMadtLocalNmi *local_nmi;
406
407 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
408 local_nmi->type = ACPI_APIC_LOCAL_NMI;
409 local_nmi->length = sizeof(*local_nmi);
410 local_nmi->processor_id = 0xff;
411 local_nmi->flags = cpu_to_le16(0);
412 local_nmi->lint = 1;
413 }
414
415 build_header(linker, table_data,
416 (void *)(table_data->data + madt_start), "APIC",
417 table_data->len - madt_start, 1, NULL, NULL);
418}
419
420static void build_append_pcihp_notify_entry(Aml *method, int slot)
421{
422 Aml *if_ctx;
423 int32_t devfn = PCI_DEVFN(slot, 0);
424
425 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
426 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
427 aml_append(method, if_ctx);
428}
429
430static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
431 bool pcihp_bridge_en)
432{
433 Aml *dev, *notify_method = NULL, *method;
434 QObject *bsel;
435 PCIBus *sec;
436 int i;
437
438 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
439 if (bsel) {
440 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
441
442 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
443 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
444 }
445
446 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
447 DeviceClass *dc;
448 PCIDeviceClass *pc;
449 PCIDevice *pdev = bus->devices[i];
450 int slot = PCI_SLOT(i);
451 bool hotplug_enabled_dev;
452 bool bridge_in_acpi;
453
454 if (!pdev) {
455 if (bsel) {
456 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
457 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
458 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
459 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
460 aml_append(method,
461 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
462 );
463 aml_append(dev, method);
464 aml_append(parent_scope, dev);
465
466 build_append_pcihp_notify_entry(notify_method, slot);
467 }
468 continue;
469 }
470
471 pc = PCI_DEVICE_GET_CLASS(pdev);
472 dc = DEVICE_GET_CLASS(pdev);
473
474
475
476
477
478
479 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
480 !DEVICE(pdev)->hotplugged;
481
482 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
483
484 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
485 continue;
486 }
487
488
489 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
490 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
491
492 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
493
494 int s3d;
495
496 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
497 s3d = 3;
498 } else {
499 s3d = 0;
500 }
501
502 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
503 aml_append(method, aml_return(aml_int(0)));
504 aml_append(dev, method);
505
506 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
507 aml_append(method, aml_return(aml_int(0)));
508 aml_append(dev, method);
509
510 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
511 aml_append(method, aml_return(aml_int(s3d)));
512 aml_append(dev, method);
513 } else if (hotplug_enabled_dev) {
514
515 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
516
517 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
518 aml_append(method,
519 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
520 );
521 aml_append(dev, method);
522
523 if (bsel) {
524 build_append_pcihp_notify_entry(notify_method, slot);
525 }
526 } else if (bridge_in_acpi) {
527
528
529
530
531 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
532
533 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
534 }
535
536 aml_append(parent_scope, dev);
537 }
538
539 if (bsel) {
540 aml_append(parent_scope, notify_method);
541 }
542
543
544
545
546 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
547
548
549 if (bsel) {
550 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
551
552 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
553 aml_append(method,
554 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) )
555 );
556 aml_append(method,
557 aml_call2("DVNT", aml_name("PCID"), aml_int(3))
558 );
559 }
560
561
562 if (pcihp_bridge_en) {
563 QLIST_FOREACH(sec, &bus->child, sibling) {
564 int32_t devfn = sec->parent_dev->devfn;
565
566 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
567 continue;
568 }
569
570 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
571 }
572 }
573 aml_append(parent_scope, method);
574 qobject_unref(bsel);
575}
576
577
578
579
580
581
582
583static Aml *build_prt_entry(const char *link_name)
584{
585 Aml *a_zero = aml_int(0);
586 Aml *pkg = aml_package(4);
587 aml_append(pkg, a_zero);
588 aml_append(pkg, a_zero);
589 aml_append(pkg, aml_name("%s", link_name));
590 aml_append(pkg, a_zero);
591 return pkg;
592}
593
594
595
596
597
598
599
600static Aml *initialize_route(Aml *route, const char *link_name,
601 Aml *lnk_idx, int idx)
602{
603 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
604 Aml *pkg = build_prt_entry(link_name);
605
606 aml_append(if_ctx, aml_store(pkg, route));
607
608 return if_ctx;
609}
610
611
612
613
614
615
616
617
618
619
620
621static Aml *build_prt(bool is_pci0_prt)
622{
623 Aml *method, *while_ctx, *pin, *res;
624
625 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
626 res = aml_local(0);
627 pin = aml_local(1);
628 aml_append(method, aml_store(aml_package(128), res));
629 aml_append(method, aml_store(aml_int(0), pin));
630
631
632 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
633 {
634 Aml *slot = aml_local(2);
635 Aml *lnk_idx = aml_local(3);
636 Aml *route = aml_local(4);
637
638
639 aml_append(while_ctx,
640 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
641
642 aml_append(while_ctx,
643 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
644 lnk_idx));
645
646
647 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
648 if (is_pci0_prt) {
649 Aml *if_device_1, *if_pin_4, *else_pin_4;
650
651
652 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
653 {
654 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
655 {
656 aml_append(if_pin_4,
657 aml_store(build_prt_entry("LNKS"), route));
658 }
659 aml_append(if_device_1, if_pin_4);
660 else_pin_4 = aml_else();
661 {
662 aml_append(else_pin_4,
663 aml_store(build_prt_entry("LNKA"), route));
664 }
665 aml_append(if_device_1, else_pin_4);
666 }
667 aml_append(while_ctx, if_device_1);
668 } else {
669 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
670 }
671 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
672 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
673
674
675 aml_append(while_ctx,
676 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
677 NULL),
678 aml_index(route, aml_int(0))));
679
680 aml_append(while_ctx,
681 aml_store(aml_and(pin, aml_int(3), NULL),
682 aml_index(route, aml_int(1))));
683
684 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
685
686 aml_append(while_ctx, aml_increment(pin));
687 }
688 aml_append(method, while_ctx);
689
690 aml_append(method, aml_return(res));
691
692 return method;
693}
694
695typedef struct CrsRangeEntry {
696 uint64_t base;
697 uint64_t limit;
698} CrsRangeEntry;
699
700static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
701{
702 CrsRangeEntry *entry;
703
704 entry = g_malloc(sizeof(*entry));
705 entry->base = base;
706 entry->limit = limit;
707
708 g_ptr_array_add(ranges, entry);
709}
710
711static void crs_range_free(gpointer data)
712{
713 CrsRangeEntry *entry = (CrsRangeEntry *)data;
714 g_free(entry);
715}
716
717typedef struct CrsRangeSet {
718 GPtrArray *io_ranges;
719 GPtrArray *mem_ranges;
720 GPtrArray *mem_64bit_ranges;
721 } CrsRangeSet;
722
723static void crs_range_set_init(CrsRangeSet *range_set)
724{
725 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
726 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
727 range_set->mem_64bit_ranges =
728 g_ptr_array_new_with_free_func(crs_range_free);
729}
730
731static void crs_range_set_free(CrsRangeSet *range_set)
732{
733 g_ptr_array_free(range_set->io_ranges, true);
734 g_ptr_array_free(range_set->mem_ranges, true);
735 g_ptr_array_free(range_set->mem_64bit_ranges, true);
736}
737
738static gint crs_range_compare(gconstpointer a, gconstpointer b)
739{
740 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
741 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
742
743 if (entry_a->base < entry_b->base) {
744 return -1;
745 } else if (entry_a->base > entry_b->base) {
746 return 1;
747 } else {
748 return 0;
749 }
750}
751
752
753
754
755
756
757
758static void crs_replace_with_free_ranges(GPtrArray *ranges,
759 uint64_t start, uint64_t end)
760{
761 GPtrArray *free_ranges = g_ptr_array_new();
762 uint64_t free_base = start;
763 int i;
764
765 g_ptr_array_sort(ranges, crs_range_compare);
766 for (i = 0; i < ranges->len; i++) {
767 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
768
769 if (free_base < used->base) {
770 crs_range_insert(free_ranges, free_base, used->base - 1);
771 }
772
773 free_base = used->limit + 1;
774 }
775
776 if (free_base < end) {
777 crs_range_insert(free_ranges, free_base, end);
778 }
779
780 g_ptr_array_set_size(ranges, 0);
781 for (i = 0; i < free_ranges->len; i++) {
782 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
783 }
784
785 g_ptr_array_free(free_ranges, true);
786}
787
788
789
790
791
792static void crs_range_merge(GPtrArray *range)
793{
794 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
795 CrsRangeEntry *entry;
796 uint64_t range_base, range_limit;
797 int i;
798
799 if (!range->len) {
800 return;
801 }
802
803 g_ptr_array_sort(range, crs_range_compare);
804
805 entry = g_ptr_array_index(range, 0);
806 range_base = entry->base;
807 range_limit = entry->limit;
808 for (i = 1; i < range->len; i++) {
809 entry = g_ptr_array_index(range, i);
810 if (entry->base - 1 == range_limit) {
811 range_limit = entry->limit;
812 } else {
813 crs_range_insert(tmp, range_base, range_limit);
814 range_base = entry->base;
815 range_limit = entry->limit;
816 }
817 }
818 crs_range_insert(tmp, range_base, range_limit);
819
820 g_ptr_array_set_size(range, 0);
821 for (i = 0; i < tmp->len; i++) {
822 entry = g_ptr_array_index(tmp, i);
823 crs_range_insert(range, entry->base, entry->limit);
824 }
825 g_ptr_array_free(tmp, true);
826}
827
828static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
829{
830 Aml *crs = aml_resource_template();
831 CrsRangeSet temp_range_set;
832 CrsRangeEntry *entry;
833 uint8_t max_bus = pci_bus_num(host->bus);
834 uint8_t type;
835 int devfn;
836 int i;
837
838 crs_range_set_init(&temp_range_set);
839 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
840 uint64_t range_base, range_limit;
841 PCIDevice *dev = host->bus->devices[devfn];
842
843 if (!dev) {
844 continue;
845 }
846
847 for (i = 0; i < PCI_NUM_REGIONS; i++) {
848 PCIIORegion *r = &dev->io_regions[i];
849
850 range_base = r->addr;
851 range_limit = r->addr + r->size - 1;
852
853
854
855
856
857 if (!range_base || range_base > range_limit) {
858 continue;
859 }
860
861 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
862 crs_range_insert(temp_range_set.io_ranges,
863 range_base, range_limit);
864 } else {
865 crs_range_insert(temp_range_set.mem_ranges,
866 range_base, range_limit);
867 }
868 }
869
870 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
871 if (type == PCI_HEADER_TYPE_BRIDGE) {
872 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
873 if (subordinate > max_bus) {
874 max_bus = subordinate;
875 }
876
877 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
878 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
879
880
881
882
883
884 if (range_base && range_base <= range_limit) {
885 crs_range_insert(temp_range_set.io_ranges,
886 range_base, range_limit);
887 }
888
889 range_base =
890 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
891 range_limit =
892 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
893
894
895
896
897
898 if (range_base && range_base <= range_limit) {
899 uint64_t length = range_limit - range_base + 1;
900 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
901 crs_range_insert(temp_range_set.mem_ranges,
902 range_base, range_limit);
903 } else {
904 crs_range_insert(temp_range_set.mem_64bit_ranges,
905 range_base, range_limit);
906 }
907 }
908
909 range_base =
910 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
911 range_limit =
912 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
913
914
915
916
917
918 if (range_base && range_base <= range_limit) {
919 uint64_t length = range_limit - range_base + 1;
920 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
921 crs_range_insert(temp_range_set.mem_ranges,
922 range_base, range_limit);
923 } else {
924 crs_range_insert(temp_range_set.mem_64bit_ranges,
925 range_base, range_limit);
926 }
927 }
928 }
929 }
930
931 crs_range_merge(temp_range_set.io_ranges);
932 for (i = 0; i < temp_range_set.io_ranges->len; i++) {
933 entry = g_ptr_array_index(temp_range_set.io_ranges, i);
934 aml_append(crs,
935 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
936 AML_POS_DECODE, AML_ENTIRE_RANGE,
937 0, entry->base, entry->limit, 0,
938 entry->limit - entry->base + 1));
939 crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
940 }
941
942 crs_range_merge(temp_range_set.mem_ranges);
943 for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
944 entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
945 aml_append(crs,
946 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
947 AML_MAX_FIXED, AML_NON_CACHEABLE,
948 AML_READ_WRITE,
949 0, entry->base, entry->limit, 0,
950 entry->limit - entry->base + 1));
951 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
952 }
953
954 crs_range_merge(temp_range_set.mem_64bit_ranges);
955 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) {
956 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i);
957 aml_append(crs,
958 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
959 AML_MAX_FIXED, AML_NON_CACHEABLE,
960 AML_READ_WRITE,
961 0, entry->base, entry->limit, 0,
962 entry->limit - entry->base + 1));
963 crs_range_insert(range_set->mem_64bit_ranges,
964 entry->base, entry->limit);
965 }
966
967 crs_range_set_free(&temp_range_set);
968
969 aml_append(crs,
970 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
971 0,
972 pci_bus_num(host->bus),
973 max_bus,
974 0,
975 max_bus - pci_bus_num(host->bus) + 1));
976
977 return crs;
978}
979
980static void build_hpet_aml(Aml *table)
981{
982 Aml *crs;
983 Aml *field;
984 Aml *method;
985 Aml *if_ctx;
986 Aml *scope = aml_scope("_SB");
987 Aml *dev = aml_device("HPET");
988 Aml *zero = aml_int(0);
989 Aml *id = aml_local(0);
990 Aml *period = aml_local(1);
991
992 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
993 aml_append(dev, aml_name_decl("_UID", zero));
994
995 aml_append(dev,
996 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
997 HPET_LEN));
998 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
999 aml_append(field, aml_named_field("VEND", 32));
1000 aml_append(field, aml_named_field("PRD", 32));
1001 aml_append(dev, field);
1002
1003 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1004 aml_append(method, aml_store(aml_name("VEND"), id));
1005 aml_append(method, aml_store(aml_name("PRD"), period));
1006 aml_append(method, aml_shiftright(id, aml_int(16), id));
1007 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1008 aml_equal(id, aml_int(0xffff))));
1009 {
1010 aml_append(if_ctx, aml_return(zero));
1011 }
1012 aml_append(method, if_ctx);
1013
1014 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1015 aml_lgreater(period, aml_int(100000000))));
1016 {
1017 aml_append(if_ctx, aml_return(zero));
1018 }
1019 aml_append(method, if_ctx);
1020
1021 aml_append(method, aml_return(aml_int(0x0F)));
1022 aml_append(dev, method);
1023
1024 crs = aml_resource_template();
1025 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1026 aml_append(dev, aml_name_decl("_CRS", crs));
1027
1028 aml_append(scope, dev);
1029 aml_append(table, scope);
1030}
1031
1032static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
1033{
1034 Aml *dev, *fdi;
1035 uint8_t maxc, maxh, maxs;
1036
1037 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1038
1039 dev = aml_device("FLP%c", 'A' + idx);
1040
1041 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1042
1043 fdi = aml_package(16);
1044 aml_append(fdi, aml_int(idx));
1045 aml_append(fdi,
1046 aml_int(cmos_get_fd_drive_type(type)));
1047
1048
1049
1050
1051 aml_append(fdi, aml_int(maxc));
1052 aml_append(fdi, aml_int(maxs));
1053 aml_append(fdi, aml_int(maxh));
1054
1055
1056
1057
1058 aml_append(fdi, aml_int(0xAF));
1059 aml_append(fdi, aml_int(0x02));
1060 aml_append(fdi, aml_int(0x25));
1061 aml_append(fdi, aml_int(0x02));
1062 aml_append(fdi, aml_int(0x12));
1063 aml_append(fdi, aml_int(0x1B));
1064 aml_append(fdi, aml_int(0xFF));
1065 aml_append(fdi, aml_int(0x6C));
1066 aml_append(fdi, aml_int(0xF6));
1067 aml_append(fdi, aml_int(0x0F));
1068 aml_append(fdi, aml_int(0x08));
1069
1070 aml_append(dev, aml_name_decl("_FDI", fdi));
1071 return dev;
1072}
1073
1074static Aml *build_fdc_device_aml(ISADevice *fdc)
1075{
1076 int i;
1077 Aml *dev;
1078 Aml *crs;
1079
1080#define ACPI_FDE_MAX_FD 4
1081 uint32_t fde_buf[5] = {
1082 0, 0, 0, 0,
1083 cpu_to_le32(2)
1084 };
1085
1086 dev = aml_device("FDC0");
1087 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1088
1089 crs = aml_resource_template();
1090 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1091 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1092 aml_append(crs, aml_irq_no_flags(6));
1093 aml_append(crs,
1094 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1095 aml_append(dev, aml_name_decl("_CRS", crs));
1096
1097 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1098 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1099
1100 if (type < FLOPPY_DRIVE_TYPE_NONE) {
1101 fde_buf[i] = cpu_to_le32(1);
1102 aml_append(dev, build_fdinfo_aml(i, type));
1103 }
1104 }
1105 aml_append(dev, aml_name_decl("_FDE",
1106 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1107
1108 return dev;
1109}
1110
1111static Aml *build_rtc_device_aml(void)
1112{
1113 Aml *dev;
1114 Aml *crs;
1115
1116 dev = aml_device("RTC");
1117 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1118 crs = aml_resource_template();
1119 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1120 aml_append(crs, aml_irq_no_flags(8));
1121 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
1122 aml_append(dev, aml_name_decl("_CRS", crs));
1123
1124 return dev;
1125}
1126
1127static Aml *build_kbd_device_aml(void)
1128{
1129 Aml *dev;
1130 Aml *crs;
1131 Aml *method;
1132
1133 dev = aml_device("KBD");
1134 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1135
1136 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1137 aml_append(method, aml_return(aml_int(0x0f)));
1138 aml_append(dev, method);
1139
1140 crs = aml_resource_template();
1141 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1142 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1143 aml_append(crs, aml_irq_no_flags(1));
1144 aml_append(dev, aml_name_decl("_CRS", crs));
1145
1146 return dev;
1147}
1148
1149static Aml *build_mouse_device_aml(void)
1150{
1151 Aml *dev;
1152 Aml *crs;
1153 Aml *method;
1154
1155 dev = aml_device("MOU");
1156 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1157
1158 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1159 aml_append(method, aml_return(aml_int(0x0f)));
1160 aml_append(dev, method);
1161
1162 crs = aml_resource_template();
1163 aml_append(crs, aml_irq_no_flags(12));
1164 aml_append(dev, aml_name_decl("_CRS", crs));
1165
1166 return dev;
1167}
1168
1169static Aml *build_lpt_device_aml(void)
1170{
1171 Aml *dev;
1172 Aml *crs;
1173 Aml *method;
1174 Aml *if_ctx;
1175 Aml *else_ctx;
1176 Aml *zero = aml_int(0);
1177 Aml *is_present = aml_local(0);
1178
1179 dev = aml_device("LPT");
1180 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1181
1182 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1183 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1184 if_ctx = aml_if(aml_equal(is_present, zero));
1185 {
1186 aml_append(if_ctx, aml_return(aml_int(0x00)));
1187 }
1188 aml_append(method, if_ctx);
1189 else_ctx = aml_else();
1190 {
1191 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1192 }
1193 aml_append(method, else_ctx);
1194 aml_append(dev, method);
1195
1196 crs = aml_resource_template();
1197 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1198 aml_append(crs, aml_irq_no_flags(7));
1199 aml_append(dev, aml_name_decl("_CRS", crs));
1200
1201 return dev;
1202}
1203
1204static Aml *build_com_device_aml(uint8_t uid)
1205{
1206 Aml *dev;
1207 Aml *crs;
1208 Aml *method;
1209 Aml *if_ctx;
1210 Aml *else_ctx;
1211 Aml *zero = aml_int(0);
1212 Aml *is_present = aml_local(0);
1213 const char *enabled_field = "CAEN";
1214 uint8_t irq = 4;
1215 uint16_t io_port = 0x03F8;
1216
1217 assert(uid == 1 || uid == 2);
1218 if (uid == 2) {
1219 enabled_field = "CBEN";
1220 irq = 3;
1221 io_port = 0x02F8;
1222 }
1223
1224 dev = aml_device("COM%d", uid);
1225 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1226 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1227
1228 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1229 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1230 if_ctx = aml_if(aml_equal(is_present, zero));
1231 {
1232 aml_append(if_ctx, aml_return(aml_int(0x00)));
1233 }
1234 aml_append(method, if_ctx);
1235 else_ctx = aml_else();
1236 {
1237 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1238 }
1239 aml_append(method, else_ctx);
1240 aml_append(dev, method);
1241
1242 crs = aml_resource_template();
1243 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1244 aml_append(crs, aml_irq_no_flags(irq));
1245 aml_append(dev, aml_name_decl("_CRS", crs));
1246
1247 return dev;
1248}
1249
1250static void build_isa_devices_aml(Aml *table)
1251{
1252 ISADevice *fdc = pc_find_fdc0();
1253 bool ambiguous;
1254
1255 Aml *scope = aml_scope("_SB.PCI0.ISA");
1256 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
1257
1258 aml_append(scope, build_rtc_device_aml());
1259 aml_append(scope, build_kbd_device_aml());
1260 aml_append(scope, build_mouse_device_aml());
1261 if (fdc) {
1262 aml_append(scope, build_fdc_device_aml(fdc));
1263 }
1264 aml_append(scope, build_lpt_device_aml());
1265 aml_append(scope, build_com_device_aml(1));
1266 aml_append(scope, build_com_device_aml(2));
1267
1268 if (ambiguous) {
1269 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1270 } else if (!obj) {
1271 error_report("No ISA bus, unable to define IPMI ACPI data");
1272 } else {
1273 build_acpi_ipmi_devices(scope, BUS(obj));
1274 }
1275
1276 aml_append(table, scope);
1277}
1278
1279static void build_dbg_aml(Aml *table)
1280{
1281 Aml *field;
1282 Aml *method;
1283 Aml *while_ctx;
1284 Aml *scope = aml_scope("\\");
1285 Aml *buf = aml_local(0);
1286 Aml *len = aml_local(1);
1287 Aml *idx = aml_local(2);
1288
1289 aml_append(scope,
1290 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
1291 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1292 aml_append(field, aml_named_field("DBGB", 8));
1293 aml_append(scope, field);
1294
1295 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1296
1297 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1298 aml_append(method, aml_to_buffer(buf, buf));
1299 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1300 aml_append(method, aml_store(aml_int(0), idx));
1301
1302 while_ctx = aml_while(aml_lless(idx, len));
1303 aml_append(while_ctx,
1304 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1305 aml_append(while_ctx, aml_increment(idx));
1306 aml_append(method, while_ctx);
1307
1308 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1309 aml_append(scope, method);
1310
1311 aml_append(table, scope);
1312}
1313
1314static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1315{
1316 Aml *dev;
1317 Aml *crs;
1318 Aml *method;
1319 uint32_t irqs[] = {5, 10, 11};
1320
1321 dev = aml_device("%s", name);
1322 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1323 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1324
1325 crs = aml_resource_template();
1326 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1327 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1328 aml_append(dev, aml_name_decl("_PRS", crs));
1329
1330 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1331 aml_append(method, aml_return(aml_call1("IQST", reg)));
1332 aml_append(dev, method);
1333
1334 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1335 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1336 aml_append(dev, method);
1337
1338 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1339 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1340 aml_append(dev, method);
1341
1342 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1343 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1344 aml_append(method, aml_store(aml_name("PRRI"), reg));
1345 aml_append(dev, method);
1346
1347 return dev;
1348 }
1349
1350static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1351{
1352 Aml *dev;
1353 Aml *crs;
1354 Aml *method;
1355 uint32_t irqs;
1356
1357 dev = aml_device("%s", name);
1358 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1359 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1360
1361 crs = aml_resource_template();
1362 irqs = gsi;
1363 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1364 AML_SHARED, &irqs, 1));
1365 aml_append(dev, aml_name_decl("_PRS", crs));
1366
1367 aml_append(dev, aml_name_decl("_CRS", crs));
1368
1369
1370
1371
1372 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1373 aml_append(dev, method);
1374
1375 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1376 aml_append(dev, method);
1377
1378 return dev;
1379}
1380
1381
1382static Aml *build_iqcr_method(bool is_piix4)
1383{
1384 Aml *if_ctx;
1385 uint32_t irqs;
1386 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1387 Aml *crs = aml_resource_template();
1388
1389 irqs = 0;
1390 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1391 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1392 aml_append(method, aml_name_decl("PRR0", crs));
1393
1394 aml_append(method,
1395 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1396
1397 if (is_piix4) {
1398 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1399 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1400 aml_append(method, if_ctx);
1401 } else {
1402 aml_append(method,
1403 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1404 aml_name("PRRI")));
1405 }
1406
1407 aml_append(method, aml_return(aml_name("PRR0")));
1408 return method;
1409}
1410
1411
1412static Aml *build_irq_status_method(void)
1413{
1414 Aml *if_ctx;
1415 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1416
1417 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1418 aml_append(if_ctx, aml_return(aml_int(0x09)));
1419 aml_append(method, if_ctx);
1420 aml_append(method, aml_return(aml_int(0x0B)));
1421 return method;
1422}
1423
1424static void build_piix4_pci0_int(Aml *table)
1425{
1426 Aml *dev;
1427 Aml *crs;
1428 Aml *field;
1429 Aml *method;
1430 uint32_t irqs;
1431 Aml *sb_scope = aml_scope("_SB");
1432 Aml *pci0_scope = aml_scope("PCI0");
1433
1434 aml_append(pci0_scope, build_prt(true));
1435 aml_append(sb_scope, pci0_scope);
1436
1437 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1438 aml_append(field, aml_named_field("PRQ0", 8));
1439 aml_append(field, aml_named_field("PRQ1", 8));
1440 aml_append(field, aml_named_field("PRQ2", 8));
1441 aml_append(field, aml_named_field("PRQ3", 8));
1442 aml_append(sb_scope, field);
1443
1444 aml_append(sb_scope, build_irq_status_method());
1445 aml_append(sb_scope, build_iqcr_method(true));
1446
1447 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1448 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1449 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1450 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1451
1452 dev = aml_device("LNKS");
1453 {
1454 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1455 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1456
1457 crs = aml_resource_template();
1458 irqs = 9;
1459 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1460 AML_ACTIVE_HIGH, AML_SHARED,
1461 &irqs, 1));
1462 aml_append(dev, aml_name_decl("_PRS", crs));
1463
1464
1465
1466
1467
1468 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1469 aml_append(method, aml_return(aml_int(0x0b)));
1470 aml_append(dev, method);
1471
1472 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1473 aml_append(dev, method);
1474
1475 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1476 aml_append(method, aml_return(aml_name("_PRS")));
1477 aml_append(dev, method);
1478
1479 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1480 aml_append(dev, method);
1481 }
1482 aml_append(sb_scope, dev);
1483
1484 aml_append(table, sb_scope);
1485}
1486
1487static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1488{
1489 int i;
1490 int head;
1491 Aml *pkg;
1492 char base = name[3] < 'E' ? 'A' : 'E';
1493 char *s = g_strdup(name);
1494 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1495
1496 assert(strlen(s) == 4);
1497
1498 head = name[3] - base;
1499 for (i = 0; i < 4; i++) {
1500 if (head + i > 3) {
1501 head = i * -1;
1502 }
1503 s[3] = base + head + i;
1504 pkg = aml_package(4);
1505 aml_append(pkg, a_nr);
1506 aml_append(pkg, aml_int(i));
1507 aml_append(pkg, aml_name("%s", s));
1508 aml_append(pkg, aml_int(0));
1509 aml_append(ctx, pkg);
1510 }
1511 g_free(s);
1512}
1513
1514static Aml *build_q35_routing_table(const char *str)
1515{
1516 int i;
1517 Aml *pkg;
1518 char *name = g_strdup_printf("%s ", str);
1519
1520 pkg = aml_package(128);
1521 for (i = 0; i < 0x18; i++) {
1522 name[3] = 'E' + (i & 0x3);
1523 append_q35_prt_entry(pkg, i, name);
1524 }
1525
1526 name[3] = 'E';
1527 append_q35_prt_entry(pkg, 0x18, name);
1528
1529
1530 for (i = 0x0019; i < 0x1e; i++) {
1531 name[3] = 'A';
1532 append_q35_prt_entry(pkg, i, name);
1533 }
1534
1535
1536 name[3] = 'E';
1537 append_q35_prt_entry(pkg, 0x1e, name);
1538 name[3] = 'A';
1539 append_q35_prt_entry(pkg, 0x1f, name);
1540
1541 g_free(name);
1542 return pkg;
1543}
1544
1545static void build_q35_pci0_int(Aml *table)
1546{
1547 Aml *field;
1548 Aml *method;
1549 Aml *sb_scope = aml_scope("_SB");
1550 Aml *pci0_scope = aml_scope("PCI0");
1551
1552
1553 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1554 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1555 {
1556 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1557 }
1558 aml_append(table, method);
1559
1560 aml_append(pci0_scope,
1561 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1562 aml_append(pci0_scope,
1563 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1564
1565 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1566 {
1567 Aml *if_ctx;
1568 Aml *else_ctx;
1569
1570
1571
1572
1573
1574 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1575 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1576 aml_append(method, if_ctx);
1577 else_ctx = aml_else();
1578 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1579 aml_append(method, else_ctx);
1580 }
1581 aml_append(pci0_scope, method);
1582 aml_append(sb_scope, pci0_scope);
1583
1584 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1585 aml_append(field, aml_named_field("PRQA", 8));
1586 aml_append(field, aml_named_field("PRQB", 8));
1587 aml_append(field, aml_named_field("PRQC", 8));
1588 aml_append(field, aml_named_field("PRQD", 8));
1589 aml_append(field, aml_reserved_field(0x20));
1590 aml_append(field, aml_named_field("PRQE", 8));
1591 aml_append(field, aml_named_field("PRQF", 8));
1592 aml_append(field, aml_named_field("PRQG", 8));
1593 aml_append(field, aml_named_field("PRQH", 8));
1594 aml_append(sb_scope, field);
1595
1596 aml_append(sb_scope, build_irq_status_method());
1597 aml_append(sb_scope, build_iqcr_method(false));
1598
1599 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1600 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1601 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1602 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1603 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1604 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1605 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1606 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1607
1608 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1609 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1610 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1611 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1612 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1613 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1614 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1615 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1616
1617 aml_append(table, sb_scope);
1618}
1619
1620static void build_q35_isa_bridge(Aml *table)
1621{
1622 Aml *dev;
1623 Aml *scope;
1624 Aml *field;
1625
1626 scope = aml_scope("_SB.PCI0");
1627 dev = aml_device("ISA");
1628 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1629
1630
1631 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1632 aml_int(0x60), 0x0C));
1633
1634 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
1635 aml_int(0x80), 0x02));
1636 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1637 aml_append(field, aml_named_field("COMA", 3));
1638 aml_append(field, aml_reserved_field(1));
1639 aml_append(field, aml_named_field("COMB", 3));
1640 aml_append(field, aml_reserved_field(1));
1641 aml_append(field, aml_named_field("LPTD", 2));
1642 aml_append(dev, field);
1643
1644 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
1645 aml_int(0x82), 0x02));
1646
1647 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1648 aml_append(field, aml_named_field("CAEN", 1));
1649 aml_append(field, aml_named_field("CBEN", 1));
1650 aml_append(field, aml_named_field("LPEN", 1));
1651 aml_append(dev, field);
1652
1653 aml_append(scope, dev);
1654 aml_append(table, scope);
1655}
1656
1657static void build_piix4_pm(Aml *table)
1658{
1659 Aml *dev;
1660 Aml *scope;
1661
1662 scope = aml_scope("_SB.PCI0");
1663 dev = aml_device("PX13");
1664 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1665
1666 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
1667 aml_int(0x00), 0xff));
1668 aml_append(scope, dev);
1669 aml_append(table, scope);
1670}
1671
1672static void build_piix4_isa_bridge(Aml *table)
1673{
1674 Aml *dev;
1675 Aml *scope;
1676 Aml *field;
1677
1678 scope = aml_scope("_SB.PCI0");
1679 dev = aml_device("ISA");
1680 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1681
1682
1683 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1684 aml_int(0x60), 0x04));
1685
1686 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1687
1688 aml_append(field, aml_reserved_field(0x2f8));
1689 aml_append(field, aml_reserved_field(7));
1690 aml_append(field, aml_named_field("LPEN", 1));
1691
1692 aml_append(field, aml_reserved_field(0x38));
1693 aml_append(field, aml_reserved_field(3));
1694 aml_append(field, aml_named_field("CAEN", 1));
1695 aml_append(field, aml_reserved_field(3));
1696 aml_append(field, aml_named_field("CBEN", 1));
1697 aml_append(dev, field);
1698
1699 aml_append(scope, dev);
1700 aml_append(table, scope);
1701}
1702
1703static void build_piix4_pci_hotplug(Aml *table)
1704{
1705 Aml *scope;
1706 Aml *field;
1707 Aml *method;
1708
1709 scope = aml_scope("_SB.PCI0");
1710
1711 aml_append(scope,
1712 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1713 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1714 aml_append(field, aml_named_field("PCIU", 32));
1715 aml_append(field, aml_named_field("PCID", 32));
1716 aml_append(scope, field);
1717
1718 aml_append(scope,
1719 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1720 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1721 aml_append(field, aml_named_field("B0EJ", 32));
1722 aml_append(scope, field);
1723
1724 aml_append(scope,
1725 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
1726 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1727 aml_append(field, aml_named_field("BNUM", 32));
1728 aml_append(scope, field);
1729
1730 aml_append(scope, aml_mutex("BLCK", 0));
1731
1732 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1733 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1734 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1735 aml_append(method,
1736 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1737 aml_append(method, aml_release(aml_name("BLCK")));
1738 aml_append(method, aml_return(aml_int(0)));
1739 aml_append(scope, method);
1740
1741 aml_append(table, scope);
1742}
1743
1744static Aml *build_q35_osc_method(void)
1745{
1746 Aml *if_ctx;
1747 Aml *if_ctx2;
1748 Aml *else_ctx;
1749 Aml *method;
1750 Aml *a_cwd1 = aml_name("CDW1");
1751 Aml *a_ctrl = aml_local(0);
1752
1753 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1754 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1755
1756 if_ctx = aml_if(aml_equal(
1757 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1758 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1759 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1760
1761 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1762
1763
1764
1765
1766
1767 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl));
1768
1769 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1770
1771 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1772 aml_append(if_ctx, if_ctx2);
1773
1774 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1775
1776 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1777 aml_append(if_ctx, if_ctx2);
1778
1779
1780 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1781 aml_append(method, if_ctx);
1782
1783 else_ctx = aml_else();
1784
1785 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1786 aml_append(method, else_ctx);
1787
1788 aml_append(method, aml_return(aml_arg(3)));
1789 return method;
1790}
1791
1792static void
1793build_dsdt(GArray *table_data, BIOSLinker *linker,
1794 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1795 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1796{
1797 CrsRangeEntry *entry;
1798 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1799 CrsRangeSet crs_range_set;
1800 PCMachineState *pcms = PC_MACHINE(machine);
1801 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1802 uint32_t nr_mem = machine->ram_slots;
1803 int root_bus_limit = 0xFF;
1804 PCIBus *bus = NULL;
1805 int i;
1806
1807 dsdt = init_aml_allocator();
1808
1809
1810 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1811
1812 build_dbg_aml(dsdt);
1813 if (misc->is_piix4) {
1814 sb_scope = aml_scope("_SB");
1815 dev = aml_device("PCI0");
1816 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1817 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1818 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1819 aml_append(sb_scope, dev);
1820 aml_append(dsdt, sb_scope);
1821
1822 build_hpet_aml(dsdt);
1823 build_piix4_pm(dsdt);
1824 build_piix4_isa_bridge(dsdt);
1825 build_isa_devices_aml(dsdt);
1826 build_piix4_pci_hotplug(dsdt);
1827 build_piix4_pci0_int(dsdt);
1828 } else {
1829 sb_scope = aml_scope("_SB");
1830 dev = aml_device("PCI0");
1831 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1832 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1833 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1834 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1835 aml_append(dev, build_q35_osc_method());
1836 aml_append(sb_scope, dev);
1837 aml_append(dsdt, sb_scope);
1838
1839 build_hpet_aml(dsdt);
1840 build_q35_isa_bridge(dsdt);
1841 build_isa_devices_aml(dsdt);
1842 build_q35_pci0_int(dsdt);
1843 }
1844
1845 if (pcmc->legacy_cpu_hotplug) {
1846 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1847 } else {
1848 CPUHotplugFeatures opts = {
1849 .apci_1_compatible = true, .has_legacy_cphp = true
1850 };
1851 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1852 "\\_SB.PCI0", "\\_GPE._E02");
1853 }
1854 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", "\\_GPE._E03");
1855
1856 scope = aml_scope("_GPE");
1857 {
1858 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1859
1860 if (misc->is_piix4) {
1861 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1862 aml_append(method,
1863 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1864 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1865 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1866 aml_append(scope, method);
1867 }
1868
1869 if (pcms->acpi_nvdimm_state.is_enabled) {
1870 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1871 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1872 aml_int(0x80)));
1873 aml_append(scope, method);
1874 }
1875 }
1876 aml_append(dsdt, scope);
1877
1878 crs_range_set_init(&crs_range_set);
1879 bus = PC_MACHINE(machine)->bus;
1880 if (bus) {
1881 QLIST_FOREACH(bus, &bus->child, sibling) {
1882 uint8_t bus_num = pci_bus_num(bus);
1883 uint8_t numa_node = pci_bus_numa_node(bus);
1884
1885
1886 if (!pci_bus_is_root(bus)) {
1887 continue;
1888 }
1889
1890 if (bus_num < root_bus_limit) {
1891 root_bus_limit = bus_num - 1;
1892 }
1893
1894 scope = aml_scope("\\_SB");
1895 dev = aml_device("PC%.02X", bus_num);
1896 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1897 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1898 if (pci_bus_is_express(bus)) {
1899 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1900 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1901 aml_append(dev, build_q35_osc_method());
1902 } else {
1903 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1904 }
1905
1906 if (numa_node != NUMA_NODE_UNASSIGNED) {
1907 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1908 }
1909
1910 aml_append(dev, build_prt(false));
1911 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
1912 aml_append(dev, aml_name_decl("_CRS", crs));
1913 aml_append(scope, dev);
1914 aml_append(dsdt, scope);
1915 }
1916 }
1917
1918 scope = aml_scope("\\_SB.PCI0");
1919
1920 crs = aml_resource_template();
1921 aml_append(crs,
1922 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1923 0x0000, 0x0, root_bus_limit,
1924 0x0000, root_bus_limit + 1));
1925 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1926
1927 aml_append(crs,
1928 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1929 AML_POS_DECODE, AML_ENTIRE_RANGE,
1930 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1931
1932 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1933 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1934 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
1935 aml_append(crs,
1936 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1937 AML_POS_DECODE, AML_ENTIRE_RANGE,
1938 0x0000, entry->base, entry->limit,
1939 0x0000, entry->limit - entry->base + 1));
1940 }
1941
1942 aml_append(crs,
1943 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1944 AML_CACHEABLE, AML_READ_WRITE,
1945 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1946
1947 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
1948 range_lob(pci_hole),
1949 range_upb(pci_hole));
1950 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
1951 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
1952 aml_append(crs,
1953 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1954 AML_NON_CACHEABLE, AML_READ_WRITE,
1955 0, entry->base, entry->limit,
1956 0, entry->limit - entry->base + 1));
1957 }
1958
1959 if (!range_is_empty(pci_hole64)) {
1960 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
1961 range_lob(pci_hole64),
1962 range_upb(pci_hole64));
1963 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
1964 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
1965 aml_append(crs,
1966 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1967 AML_MAX_FIXED,
1968 AML_CACHEABLE, AML_READ_WRITE,
1969 0, entry->base, entry->limit,
1970 0, entry->limit - entry->base + 1));
1971 }
1972 }
1973
1974 if (TPM_IS_TIS(tpm_find())) {
1975 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1976 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1977 }
1978 aml_append(scope, aml_name_decl("_CRS", crs));
1979
1980
1981 dev = aml_device("GPE0");
1982 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1983 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1984
1985 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1986 crs = aml_resource_template();
1987 aml_append(crs,
1988 aml_io(
1989 AML_DECODE16,
1990 pm->fadt.gpe0_blk.address,
1991 pm->fadt.gpe0_blk.address,
1992 1,
1993 pm->fadt.gpe0_blk.bit_width / 8)
1994 );
1995 aml_append(dev, aml_name_decl("_CRS", crs));
1996 aml_append(scope, dev);
1997
1998 crs_range_set_free(&crs_range_set);
1999
2000
2001 if (pm->pcihp_io_len) {
2002 dev = aml_device("PHPR");
2003 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2004 aml_append(dev,
2005 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2006
2007 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2008 crs = aml_resource_template();
2009 aml_append(crs,
2010 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
2011 pm->pcihp_io_len)
2012 );
2013 aml_append(dev, aml_name_decl("_CRS", crs));
2014 aml_append(scope, dev);
2015 }
2016 aml_append(dsdt, scope);
2017
2018
2019 scope = aml_scope("\\");
2020 if (!pm->s3_disabled) {
2021 pkg = aml_package(4);
2022 aml_append(pkg, aml_int(1));
2023 aml_append(pkg, aml_int(1));
2024 aml_append(pkg, aml_int(0));
2025 aml_append(pkg, aml_int(0));
2026 aml_append(scope, aml_name_decl("_S3", pkg));
2027 }
2028
2029 if (!pm->s4_disabled) {
2030 pkg = aml_package(4);
2031 aml_append(pkg, aml_int(pm->s4_val));
2032
2033 aml_append(pkg, aml_int(pm->s4_val));
2034 aml_append(pkg, aml_int(0));
2035 aml_append(pkg, aml_int(0));
2036 aml_append(scope, aml_name_decl("_S4", pkg));
2037 }
2038
2039 pkg = aml_package(4);
2040 aml_append(pkg, aml_int(0));
2041 aml_append(pkg, aml_int(0));
2042 aml_append(pkg, aml_int(0));
2043 aml_append(pkg, aml_int(0));
2044 aml_append(scope, aml_name_decl("_S5", pkg));
2045 aml_append(dsdt, scope);
2046
2047
2048 {
2049
2050
2051
2052
2053 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
2054 "dma_enabled", NULL) ?
2055 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2056 FW_CFG_CTL_SIZE;
2057
2058 scope = aml_scope("\\_SB.PCI0");
2059 dev = aml_device("FWCF");
2060
2061 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2062
2063
2064 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2065
2066 crs = aml_resource_template();
2067 aml_append(crs,
2068 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2069 );
2070 aml_append(dev, aml_name_decl("_CRS", crs));
2071
2072 aml_append(scope, dev);
2073 aml_append(dsdt, scope);
2074 }
2075
2076 if (misc->applesmc_io_base) {
2077 scope = aml_scope("\\_SB.PCI0.ISA");
2078 dev = aml_device("SMC");
2079
2080 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2081
2082 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2083
2084 crs = aml_resource_template();
2085 aml_append(crs,
2086 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
2087 0x01, APPLESMC_MAX_DATA_LENGTH)
2088 );
2089 aml_append(crs, aml_irq_no_flags(6));
2090 aml_append(dev, aml_name_decl("_CRS", crs));
2091
2092 aml_append(scope, dev);
2093 aml_append(dsdt, scope);
2094 }
2095
2096 if (misc->pvpanic_port) {
2097 scope = aml_scope("\\_SB.PCI0.ISA");
2098
2099 dev = aml_device("PEVT");
2100 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
2101
2102 crs = aml_resource_template();
2103 aml_append(crs,
2104 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
2105 );
2106 aml_append(dev, aml_name_decl("_CRS", crs));
2107
2108 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
2109 aml_int(misc->pvpanic_port), 1));
2110 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
2111 aml_append(field, aml_named_field("PEPT", 8));
2112 aml_append(dev, field);
2113
2114
2115 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2116
2117 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
2118 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2119 aml_append(method, aml_return(aml_local(0)));
2120 aml_append(dev, method);
2121
2122 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
2123 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2124 aml_append(dev, method);
2125
2126 aml_append(scope, dev);
2127 aml_append(dsdt, scope);
2128 }
2129
2130 sb_scope = aml_scope("\\_SB");
2131 {
2132 Object *pci_host;
2133 PCIBus *bus = NULL;
2134
2135 pci_host = acpi_get_i386_pci_host();
2136 if (pci_host) {
2137 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2138 }
2139
2140 if (bus) {
2141 Aml *scope = aml_scope("PCI0");
2142
2143 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
2144
2145 if (TPM_IS_TIS(tpm_find())) {
2146 dev = aml_device("ISA.TPM");
2147 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2148 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2149 crs = aml_resource_template();
2150 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2151 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2152
2153
2154
2155
2156
2157
2158 aml_append(dev, aml_name_decl("_CRS", crs));
2159 aml_append(scope, dev);
2160 }
2161
2162 aml_append(sb_scope, scope);
2163 }
2164 }
2165
2166 if (TPM_IS_CRB(tpm_find())) {
2167 dev = aml_device("TPM");
2168 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
2169 crs = aml_resource_template();
2170 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
2171 TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
2172 aml_append(dev, aml_name_decl("_CRS", crs));
2173
2174 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
2175 aml_append(method, aml_return(aml_int(0x0f)));
2176 aml_append(dev, method);
2177
2178 aml_append(sb_scope, dev);
2179 }
2180
2181 aml_append(dsdt, sb_scope);
2182
2183
2184 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
2185 build_header(linker, table_data,
2186 (void *)(table_data->data + table_data->len - dsdt->buf->len),
2187 "DSDT", dsdt->buf->len, 1, NULL, NULL);
2188 free_aml_allocator();
2189}
2190
2191static void
2192build_hpet(GArray *table_data, BIOSLinker *linker)
2193{
2194 Acpi20Hpet *hpet;
2195
2196 hpet = acpi_data_push(table_data, sizeof(*hpet));
2197
2198
2199
2200 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2201 hpet->addr.address = cpu_to_le64(HPET_BASE);
2202 build_header(linker, table_data,
2203 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
2204}
2205
2206static void
2207build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
2208{
2209 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
2210 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
2211 unsigned log_addr_offset =
2212 (char *)&tcpa->log_area_start_address - table_data->data;
2213
2214 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2215 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2216 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
2217
2218 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
2219 false );
2220
2221
2222 bios_linker_loader_add_pointer(linker,
2223 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
2224 ACPI_BUILD_TPMLOG_FILE, 0);
2225
2226 build_header(linker, table_data,
2227 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
2228}
2229
2230static void
2231build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
2232{
2233 Acpi20TPM2 *tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2234 unsigned log_addr_size = sizeof(tpm2_ptr->log_area_start_address);
2235 unsigned log_addr_offset =
2236 (char *)&tpm2_ptr->log_area_start_address - table_data->data;
2237
2238 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2239 if (TPM_IS_TIS(tpm_find())) {
2240 tpm2_ptr->control_area_address = cpu_to_le64(0);
2241 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2242 } else if (TPM_IS_CRB(tpm_find())) {
2243 tpm2_ptr->control_area_address = cpu_to_le64(TPM_CRB_ADDR_CTRL);
2244 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_CRB);
2245 } else {
2246 g_warn_if_reached();
2247 }
2248
2249 tpm2_ptr->log_area_minimum_length =
2250 cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2251
2252
2253 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
2254 log_addr_offset, log_addr_size,
2255 ACPI_BUILD_TPMLOG_FILE, 0);
2256 build_header(linker, table_data,
2257 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
2258}
2259
2260#define HOLE_640K_START (640 * KiB)
2261#define HOLE_640K_END (1 * MiB)
2262
2263static void
2264build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
2265{
2266 AcpiSystemResourceAffinityTable *srat;
2267 AcpiSratMemoryAffinity *numamem;
2268
2269 int i;
2270 int srat_start, numa_start, slots;
2271 uint64_t mem_len, mem_base, next_base;
2272 MachineClass *mc = MACHINE_GET_CLASS(machine);
2273 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
2274 PCMachineState *pcms = PC_MACHINE(machine);
2275 ram_addr_t hotplugabble_address_space_size =
2276 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE,
2277 NULL);
2278
2279 srat_start = table_data->len;
2280
2281 srat = acpi_data_push(table_data, sizeof *srat);
2282 srat->reserved1 = cpu_to_le32(1);
2283
2284 for (i = 0; i < apic_ids->len; i++) {
2285 int node_id = apic_ids->cpus[i].props.node_id;
2286 uint32_t apic_id = apic_ids->cpus[i].arch_id;
2287
2288 if (apic_id < 255) {
2289 AcpiSratProcessorAffinity *core;
2290
2291 core = acpi_data_push(table_data, sizeof *core);
2292 core->type = ACPI_SRAT_PROCESSOR_APIC;
2293 core->length = sizeof(*core);
2294 core->local_apic_id = apic_id;
2295 core->proximity_lo = node_id;
2296 memset(core->proximity_hi, 0, 3);
2297 core->local_sapic_eid = 0;
2298 core->flags = cpu_to_le32(1);
2299 } else {
2300 AcpiSratProcessorX2ApicAffinity *core;
2301
2302 core = acpi_data_push(table_data, sizeof *core);
2303 core->type = ACPI_SRAT_PROCESSOR_x2APIC;
2304 core->length = sizeof(*core);
2305 core->x2apic_id = cpu_to_le32(apic_id);
2306 core->proximity_domain = cpu_to_le32(node_id);
2307 core->flags = cpu_to_le32(1);
2308 }
2309 }
2310
2311
2312
2313
2314
2315 next_base = 0;
2316 numa_start = table_data->len;
2317
2318 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
2319 mem_base = next_base;
2320 mem_len = pcms->node_mem[i - 1];
2321 next_base = mem_base + mem_len;
2322
2323
2324 if (mem_base <= HOLE_640K_START &&
2325 next_base > HOLE_640K_START) {
2326 mem_len -= next_base - HOLE_640K_START;
2327 if (mem_len > 0) {
2328 numamem = acpi_data_push(table_data, sizeof *numamem);
2329 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2330 MEM_AFFINITY_ENABLED);
2331 }
2332
2333
2334 if (next_base <= HOLE_640K_END) {
2335 next_base = HOLE_640K_END;
2336 continue;
2337 }
2338 mem_base = HOLE_640K_END;
2339 mem_len = next_base - HOLE_640K_END;
2340 }
2341
2342
2343 if (mem_base <= pcms->below_4g_mem_size &&
2344 next_base > pcms->below_4g_mem_size) {
2345 mem_len -= next_base - pcms->below_4g_mem_size;
2346 if (mem_len > 0) {
2347 numamem = acpi_data_push(table_data, sizeof *numamem);
2348 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2349 MEM_AFFINITY_ENABLED);
2350 }
2351 mem_base = 1ULL << 32;
2352 mem_len = next_base - pcms->below_4g_mem_size;
2353 next_base = mem_base + mem_len;
2354 }
2355
2356 if (mem_len > 0) {
2357 numamem = acpi_data_push(table_data, sizeof *numamem);
2358 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2359 MEM_AFFINITY_ENABLED);
2360 }
2361 }
2362 slots = (table_data->len - numa_start) / sizeof *numamem;
2363 for (; slots < pcms->numa_nodes + 2; slots++) {
2364 numamem = acpi_data_push(table_data, sizeof *numamem);
2365 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2366 }
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376 if (hotplugabble_address_space_size) {
2377 numamem = acpi_data_push(table_data, sizeof *numamem);
2378 build_srat_memory(numamem, machine->device_memory->base,
2379 hotplugabble_address_space_size, pcms->numa_nodes - 1,
2380 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2381 }
2382
2383 build_header(linker, table_data,
2384 (void *)(table_data->data + srat_start),
2385 "SRAT",
2386 table_data->len - srat_start, 1, NULL, NULL);
2387}
2388
2389static void
2390build_mcfg_q35(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info)
2391{
2392 AcpiTableMcfg *mcfg;
2393 const char *sig;
2394 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2395
2396 mcfg = acpi_data_push(table_data, len);
2397 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2398
2399 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2400 mcfg->allocation[0].start_bus_number = 0;
2401 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2402
2403
2404
2405
2406
2407
2408
2409 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
2410
2411 sig = "QEMU";
2412 } else {
2413 sig = "MCFG";
2414 }
2415 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL);
2416}
2417
2418
2419
2420
2421
2422static void
2423build_dmar_q35(GArray *table_data, BIOSLinker *linker)
2424{
2425 int dmar_start = table_data->len;
2426
2427 AcpiTableDmar *dmar;
2428 AcpiDmarHardwareUnit *drhd;
2429 AcpiDmarRootPortATS *atsr;
2430 uint8_t dmar_flags = 0;
2431 X86IOMMUState *iommu = x86_iommu_get_default();
2432 AcpiDmarDeviceScope *scope = NULL;
2433
2434 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
2435 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
2436
2437 assert(iommu);
2438 if (iommu->intr_supported) {
2439 dmar_flags |= 0x1;
2440 }
2441
2442 dmar = acpi_data_push(table_data, sizeof(*dmar));
2443 dmar->host_address_width = intel_iommu->aw_bits - 1;
2444 dmar->flags = dmar_flags;
2445
2446
2447 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
2448 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2449 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
2450 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2451 drhd->pci_segment = cpu_to_le16(0);
2452 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2453
2454
2455
2456 scope = &drhd->scope[0];
2457 scope->entry_type = 0x03;
2458 scope->length = ioapic_scope_size;
2459 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
2460 scope->bus = Q35_PSEUDO_BUS_PLATFORM;
2461 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC);
2462 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC);
2463
2464 if (iommu->dt_supported) {
2465 atsr = acpi_data_push(table_data, sizeof(*atsr));
2466 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR);
2467 atsr->length = cpu_to_le16(sizeof(*atsr));
2468 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS;
2469 atsr->pci_segment = cpu_to_le16(0);
2470 }
2471
2472 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2473 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
2474}
2475
2476
2477
2478
2479#define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
2480
2481static void
2482build_amd_iommu(GArray *table_data, BIOSLinker *linker)
2483{
2484 int ivhd_table_len = 28;
2485 int iommu_start = table_data->len;
2486 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2487
2488
2489 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2490
2491
2492
2493 build_append_int_noprefix(table_data, 40UL << 8, 4);
2494
2495 build_append_int_noprefix(table_data, 0, 8);
2496
2497
2498 build_append_int_noprefix(table_data, 0x10, 1);
2499
2500 build_append_int_noprefix(table_data,
2501 (1UL << 0) |
2502 (1UL << 4) |
2503 (1UL << 6) |
2504 (1UL << 7),
2505 1);
2506
2507
2508
2509
2510
2511 if (x86_iommu_get_default()->intr_supported) {
2512 ivhd_table_len += 8;
2513 }
2514
2515 build_append_int_noprefix(table_data, ivhd_table_len, 2);
2516
2517 build_append_int_noprefix(table_data, s->devid, 2);
2518
2519 build_append_int_noprefix(table_data, s->capab_offset, 2);
2520
2521 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2522
2523 build_append_int_noprefix(table_data, 0, 2);
2524
2525 build_append_int_noprefix(table_data, 0, 2);
2526
2527 build_append_int_noprefix(table_data,
2528 (48UL << 30) |
2529 (48UL << 28) |
2530 (1UL << 2) |
2531 (1UL << 6),
2532 4);
2533
2534
2535
2536
2537
2538 build_append_int_noprefix(table_data, 0x0000001, 4);
2539
2540
2541
2542
2543
2544
2545
2546
2547 if (x86_iommu_get_default()->intr_supported) {
2548 build_append_int_noprefix(table_data,
2549 (0x1ull << 56) |
2550 (IOAPIC_SB_DEVID << 40) |
2551 0x48,
2552 8);
2553 }
2554
2555 build_header(linker, table_data, (void *)(table_data->data + iommu_start),
2556 "IVRS", table_data->len - iommu_start, 1, NULL, NULL);
2557}
2558
2559static GArray *
2560build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned rsdt_tbl_offset)
2561{
2562 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
2563 unsigned rsdt_pa_size = sizeof(rsdp->rsdt_physical_address);
2564 unsigned rsdt_pa_offset =
2565 (char *)&rsdp->rsdt_physical_address - rsdp_table->data;
2566
2567 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, rsdp_table, 16,
2568 true );
2569
2570 memcpy(&rsdp->signature, "RSD PTR ", 8);
2571 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
2572
2573 bios_linker_loader_add_pointer(linker,
2574 ACPI_BUILD_RSDP_FILE, rsdt_pa_offset, rsdt_pa_size,
2575 ACPI_BUILD_TABLE_FILE, rsdt_tbl_offset);
2576
2577
2578 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
2579 (char *)rsdp - rsdp_table->data, sizeof *rsdp,
2580 (char *)&rsdp->checksum - rsdp_table->data);
2581
2582 return rsdp_table;
2583}
2584
2585typedef
2586struct AcpiBuildState {
2587
2588 MemoryRegion *table_mr;
2589
2590 uint8_t patched;
2591 void *rsdp;
2592 MemoryRegion *rsdp_mr;
2593 MemoryRegion *linker_mr;
2594} AcpiBuildState;
2595
2596static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2597{
2598 Object *pci_host;
2599 QObject *o;
2600
2601 pci_host = acpi_get_i386_pci_host();
2602 g_assert(pci_host);
2603
2604 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2605 if (!o) {
2606 return false;
2607 }
2608 mcfg->mcfg_base = qnum_get_uint(qobject_to(QNum, o));
2609 qobject_unref(o);
2610
2611 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2612 assert(o);
2613 mcfg->mcfg_size = qnum_get_uint(qobject_to(QNum, o));
2614 qobject_unref(o);
2615 return true;
2616}
2617
2618static
2619void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2620{
2621 PCMachineState *pcms = PC_MACHINE(machine);
2622 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2623 GArray *table_offsets;
2624 unsigned facs, dsdt, rsdt, fadt;
2625 AcpiPmInfo pm;
2626 AcpiMiscInfo misc;
2627 AcpiMcfgInfo mcfg;
2628 Range pci_hole, pci_hole64;
2629 uint8_t *u;
2630 size_t aml_len = 0;
2631 GArray *tables_blob = tables->table_data;
2632 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2633 Object *vmgenid_dev;
2634
2635 acpi_get_pm_info(&pm);
2636 acpi_get_misc_info(&misc);
2637 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2638 acpi_get_slic_oem(&slic_oem);
2639
2640 table_offsets = g_array_new(false, true ,
2641 sizeof(uint32_t));
2642 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2643
2644 bios_linker_loader_alloc(tables->linker,
2645 ACPI_BUILD_TABLE_FILE, tables_blob,
2646 64 ,
2647 false );
2648
2649
2650
2651
2652
2653
2654 facs = tables_blob->len;
2655 build_facs(tables_blob, tables->linker);
2656
2657
2658 dsdt = tables_blob->len;
2659 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2660 &pci_hole, &pci_hole64, machine);
2661
2662
2663
2664
2665 aml_len += tables_blob->len - dsdt;
2666
2667
2668 fadt = tables_blob->len;
2669 acpi_add_table(table_offsets, tables_blob);
2670 pm.fadt.facs_tbl_offset = &facs;
2671 pm.fadt.dsdt_tbl_offset = &dsdt;
2672 pm.fadt.xdsdt_tbl_offset = &dsdt;
2673 build_fadt(tables_blob, tables->linker, &pm.fadt,
2674 slic_oem.id, slic_oem.table_id);
2675 aml_len += tables_blob->len - fadt;
2676
2677 acpi_add_table(table_offsets, tables_blob);
2678 build_madt(tables_blob, tables->linker, pcms);
2679
2680 vmgenid_dev = find_vmgenid_dev();
2681 if (vmgenid_dev) {
2682 acpi_add_table(table_offsets, tables_blob);
2683 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2684 tables->vmgenid, tables->linker);
2685 }
2686
2687 if (misc.has_hpet) {
2688 acpi_add_table(table_offsets, tables_blob);
2689 build_hpet(tables_blob, tables->linker);
2690 }
2691 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2692 acpi_add_table(table_offsets, tables_blob);
2693 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2694
2695 if (misc.tpm_version == TPM_VERSION_2_0) {
2696 acpi_add_table(table_offsets, tables_blob);
2697 build_tpm2(tables_blob, tables->linker, tables->tcpalog);
2698 }
2699 }
2700 if (pcms->numa_nodes) {
2701 acpi_add_table(table_offsets, tables_blob);
2702 build_srat(tables_blob, tables->linker, machine);
2703 if (have_numa_distance) {
2704 acpi_add_table(table_offsets, tables_blob);
2705 build_slit(tables_blob, tables->linker);
2706 }
2707 }
2708 if (acpi_get_mcfg(&mcfg)) {
2709 acpi_add_table(table_offsets, tables_blob);
2710 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
2711 }
2712 if (x86_iommu_get_default()) {
2713 IommuType IOMMUType = x86_iommu_get_type();
2714 if (IOMMUType == TYPE_AMD) {
2715 acpi_add_table(table_offsets, tables_blob);
2716 build_amd_iommu(tables_blob, tables->linker);
2717 } else if (IOMMUType == TYPE_INTEL) {
2718 acpi_add_table(table_offsets, tables_blob);
2719 build_dmar_q35(tables_blob, tables->linker);
2720 }
2721 }
2722 if (pcms->acpi_nvdimm_state.is_enabled) {
2723 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2724 &pcms->acpi_nvdimm_state, machine->ram_slots);
2725 }
2726
2727
2728 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2729 unsigned len = acpi_table_len(u);
2730
2731 acpi_add_table(table_offsets, tables_blob);
2732 g_array_append_vals(tables_blob, u, len);
2733 }
2734
2735
2736 rsdt = tables_blob->len;
2737 build_rsdt(tables_blob, tables->linker, table_offsets,
2738 slic_oem.id, slic_oem.table_id);
2739
2740
2741 build_rsdp(tables->rsdp, tables->linker, rsdt);
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760 if (pcmc->legacy_acpi_table_size) {
2761
2762
2763
2764 int legacy_aml_len =
2765 pcmc->legacy_acpi_table_size +
2766 ACPI_BUILD_LEGACY_CPU_AML_SIZE * pcms->apic_id_limit;
2767 int legacy_table_size =
2768 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2769 ACPI_BUILD_ALIGN_SIZE);
2770 if (tables_blob->len > legacy_table_size) {
2771
2772 warn_report("ACPI table size %u exceeds %d bytes,"
2773 " migration may not work",
2774 tables_blob->len, legacy_table_size);
2775 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2776 " or PCI bridges.");
2777 }
2778 g_array_set_size(tables_blob, legacy_table_size);
2779 } else {
2780
2781 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2782
2783 warn_report("ACPI table size %u exceeds %d bytes,"
2784 " migration may not work",
2785 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
2786 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2787 " or PCI bridges.");
2788 }
2789 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2790 }
2791
2792 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2793
2794
2795 g_array_free(table_offsets, true);
2796}
2797
2798static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2799{
2800 uint32_t size = acpi_data_len(data);
2801
2802
2803 memory_region_ram_resize(mr, size, &error_abort);
2804
2805 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2806 memory_region_set_dirty(mr, 0, size);
2807}
2808
2809static void acpi_build_update(void *build_opaque)
2810{
2811 AcpiBuildState *build_state = build_opaque;
2812 AcpiBuildTables tables;
2813
2814
2815 if (!build_state || build_state->patched) {
2816 return;
2817 }
2818 build_state->patched = 1;
2819
2820 acpi_build_tables_init(&tables);
2821
2822 acpi_build(&tables, MACHINE(qdev_get_machine()));
2823
2824 acpi_ram_update(build_state->table_mr, tables.table_data);
2825
2826 if (build_state->rsdp) {
2827 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2828 } else {
2829 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2830 }
2831
2832 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2833 acpi_build_tables_cleanup(&tables, true);
2834}
2835
2836static void acpi_build_reset(void *build_opaque)
2837{
2838 AcpiBuildState *build_state = build_opaque;
2839 build_state->patched = 0;
2840}
2841
2842static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2843 GArray *blob, const char *name,
2844 uint64_t max_size)
2845{
2846 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
2847 name, acpi_build_update, build_state, NULL, true);
2848}
2849
2850static const VMStateDescription vmstate_acpi_build = {
2851 .name = "acpi_build",
2852 .version_id = 1,
2853 .minimum_version_id = 1,
2854 .fields = (VMStateField[]) {
2855 VMSTATE_UINT8(patched, AcpiBuildState),
2856 VMSTATE_END_OF_LIST()
2857 },
2858};
2859
2860void acpi_setup(void)
2861{
2862 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2863 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2864 AcpiBuildTables tables;
2865 AcpiBuildState *build_state;
2866 Object *vmgenid_dev;
2867
2868 if (!pcms->fw_cfg) {
2869 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2870 return;
2871 }
2872
2873 if (!pcms->acpi_build_enabled) {
2874 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2875 return;
2876 }
2877
2878 if (!acpi_enabled) {
2879 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2880 return;
2881 }
2882
2883 build_state = g_malloc0(sizeof *build_state);
2884
2885 acpi_build_tables_init(&tables);
2886 acpi_build(&tables, MACHINE(pcms));
2887
2888
2889 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
2890 ACPI_BUILD_TABLE_FILE,
2891 ACPI_BUILD_TABLE_MAX_SIZE);
2892 assert(build_state->table_mr != NULL);
2893
2894 build_state->linker_mr =
2895 acpi_add_rom_blob(build_state, tables.linker->cmd_blob,
2896 "etc/table-loader", 0);
2897
2898 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2899 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2900
2901 vmgenid_dev = find_vmgenid_dev();
2902 if (vmgenid_dev) {
2903 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), pcms->fw_cfg,
2904 tables.vmgenid);
2905 }
2906
2907 if (!pcmc->rsdp_in_ram) {
2908
2909
2910
2911
2912
2913 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2914
2915 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2916 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2917 acpi_build_update, NULL, build_state,
2918 build_state->rsdp, rsdp_size, true);
2919 build_state->rsdp_mr = NULL;
2920 } else {
2921 build_state->rsdp = NULL;
2922 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
2923 ACPI_BUILD_RSDP_FILE, 0);
2924 }
2925
2926 qemu_register_reset(acpi_build_reset, build_state);
2927 acpi_build_reset(build_state);
2928 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2929
2930
2931
2932
2933 acpi_build_tables_cleanup(&tables, false);
2934}
2935