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28#ifndef HW_I386_INTEL_IOMMU_INTERNAL_H
29#define HW_I386_INTEL_IOMMU_INTERNAL_H
30#include "hw/i386/intel_iommu.h"
31
32
33
34
35#define DMAR_VER_REG 0x0
36#define DMAR_CAP_REG 0x8
37#define DMAR_CAP_REG_HI 0xc
38#define DMAR_ECAP_REG 0x10
39#define DMAR_ECAP_REG_HI 0X14
40#define DMAR_GCMD_REG 0x18
41#define DMAR_GSTS_REG 0x1c
42#define DMAR_RTADDR_REG 0x20
43#define DMAR_RTADDR_REG_HI 0X24
44#define DMAR_CCMD_REG 0x28
45#define DMAR_CCMD_REG_HI 0x2c
46#define DMAR_FSTS_REG 0x34
47#define DMAR_FECTL_REG 0x38
48#define DMAR_FEDATA_REG 0x3c
49#define DMAR_FEADDR_REG 0x40
50#define DMAR_FEUADDR_REG 0x44
51#define DMAR_AFLOG_REG 0x58
52#define DMAR_AFLOG_REG_HI 0X5c
53#define DMAR_PMEN_REG 0x64
54#define DMAR_PLMBASE_REG 0x68
55#define DMAR_PLMLIMIT_REG 0x6c
56#define DMAR_PHMBASE_REG 0x70
57#define DMAR_PHMBASE_REG_HI 0X74
58#define DMAR_PHMLIMIT_REG 0x78
59#define DMAR_PHMLIMIT_REG_HI 0x7c
60#define DMAR_IQH_REG 0x80
61#define DMAR_IQH_REG_HI 0X84
62#define DMAR_IQT_REG 0x88
63#define DMAR_IQT_REG_HI 0X8c
64#define DMAR_IQA_REG 0x90
65#define DMAR_IQA_REG_HI 0x94
66#define DMAR_ICS_REG 0x9c
67#define DMAR_IRTA_REG 0xb8
68#define DMAR_IRTA_REG_HI 0xbc
69#define DMAR_IECTL_REG 0xa0
70#define DMAR_IEDATA_REG 0xa4
71#define DMAR_IEADDR_REG 0xa8
72#define DMAR_IEUADDR_REG 0xac
73#define DMAR_PQH_REG 0xc0
74#define DMAR_PQH_REG_HI 0xc4
75#define DMAR_PQT_REG 0xc8
76#define DMAR_PQT_REG_HI 0xcc
77#define DMAR_PQA_REG 0xd0
78#define DMAR_PQA_REG_HI 0xd4
79#define DMAR_PRS_REG 0xdc
80#define DMAR_PECTL_REG 0xe0
81#define DMAR_PEDATA_REG 0xe4
82#define DMAR_PEADDR_REG 0xe8
83#define DMAR_PEUADDR_REG 0xec
84#define DMAR_MTRRCAP_REG 0x100
85#define DMAR_MTRRCAP_REG_HI 0x104
86#define DMAR_MTRRDEF_REG 0x108
87#define DMAR_MTRRDEF_REG_HI 0x10c
88
89
90#define DMAR_IOTLB_REG_OFFSET 0xf0
91#define DMAR_IVA_REG DMAR_IOTLB_REG_OFFSET
92#define DMAR_IVA_REG_HI (DMAR_IVA_REG + 4)
93
94#define DMAR_IOTLB_REG (DMAR_IOTLB_REG_OFFSET + 0x8)
95#define DMAR_IOTLB_REG_HI (DMAR_IOTLB_REG + 4)
96
97
98#define DMAR_FRCD_REG_OFFSET 0x220
99
100
101
102
103#define DMAR_FRCD_REG_NR 1ULL
104
105#define DMAR_FRCD_REG_0_0 0x220
106#define DMAR_FRCD_REG_0_1 0x224
107#define DMAR_FRCD_REG_0_2 0x228
108#define DMAR_FRCD_REG_0_3 0x22c
109
110
111#define VTD_INTERRUPT_ADDR_FIRST 0xfee00000ULL
112#define VTD_INTERRUPT_ADDR_LAST 0xfeefffffULL
113#define VTD_INTERRUPT_ADDR_SIZE (VTD_INTERRUPT_ADDR_LAST - \
114 VTD_INTERRUPT_ADDR_FIRST + 1)
115
116
117#define VTD_IOTLB_SID_SHIFT 36
118#define VTD_IOTLB_LVL_SHIFT 52
119#define VTD_IOTLB_MAX_SIZE 1024
120
121
122#define VTD_TLB_GLOBAL_FLUSH (1ULL << 60)
123#define VTD_TLB_DSI_FLUSH (2ULL << 60)
124#define VTD_TLB_PSI_FLUSH (3ULL << 60)
125#define VTD_TLB_FLUSH_GRANU_MASK (3ULL << 60)
126#define VTD_TLB_GLOBAL_FLUSH_A (1ULL << 57)
127#define VTD_TLB_DSI_FLUSH_A (2ULL << 57)
128#define VTD_TLB_PSI_FLUSH_A (3ULL << 57)
129#define VTD_TLB_FLUSH_GRANU_MASK_A (3ULL << 57)
130#define VTD_TLB_IVT (1ULL << 63)
131#define VTD_TLB_DID(val) (((val) >> 32) & VTD_DOMAIN_ID_MASK)
132
133
134#define VTD_IVA_ADDR(val) ((val) & ~0xfffULL)
135#define VTD_IVA_AM(val) ((val) & 0x3fULL)
136
137
138#define VTD_GCMD_TE (1UL << 31)
139#define VTD_GCMD_SRTP (1UL << 30)
140#define VTD_GCMD_SFL (1UL << 29)
141#define VTD_GCMD_EAFL (1UL << 28)
142#define VTD_GCMD_WBF (1UL << 27)
143#define VTD_GCMD_QIE (1UL << 26)
144#define VTD_GCMD_IRE (1UL << 25)
145#define VTD_GCMD_SIRTP (1UL << 24)
146#define VTD_GCMD_CFI (1UL << 23)
147
148
149#define VTD_GSTS_TES (1UL << 31)
150#define VTD_GSTS_RTPS (1UL << 30)
151#define VTD_GSTS_FLS (1UL << 29)
152#define VTD_GSTS_AFLS (1UL << 28)
153#define VTD_GSTS_WBFS (1UL << 27)
154#define VTD_GSTS_QIES (1UL << 26)
155#define VTD_GSTS_IRES (1UL << 25)
156#define VTD_GSTS_IRTPS (1UL << 24)
157#define VTD_GSTS_CFIS (1UL << 23)
158
159
160#define VTD_CCMD_ICC (1ULL << 63)
161#define VTD_CCMD_GLOBAL_INVL (1ULL << 61)
162#define VTD_CCMD_DOMAIN_INVL (2ULL << 61)
163#define VTD_CCMD_DEVICE_INVL (3ULL << 61)
164#define VTD_CCMD_CIRG_MASK (3ULL << 61)
165#define VTD_CCMD_GLOBAL_INVL_A (1ULL << 59)
166#define VTD_CCMD_DOMAIN_INVL_A (2ULL << 59)
167#define VTD_CCMD_DEVICE_INVL_A (3ULL << 59)
168#define VTD_CCMD_CAIG_MASK (3ULL << 59)
169#define VTD_CCMD_DID(val) ((val) & VTD_DOMAIN_ID_MASK)
170#define VTD_CCMD_SID(val) (((val) >> 16) & 0xffffULL)
171#define VTD_CCMD_FM(val) (((val) >> 32) & 3ULL)
172
173
174#define VTD_RTADDR_RTT (1ULL << 11)
175#define VTD_RTADDR_ADDR_MASK(aw) (VTD_HAW_MASK(aw) ^ 0xfffULL)
176
177
178#define VTD_IRTA_ADDR_MASK(aw) (VTD_HAW_MASK(aw) ^ 0xfffULL)
179#define VTD_IRTA_EIME (1ULL << 11)
180#define VTD_IRTA_SIZE_MASK (0xfULL)
181
182
183
184#define VTD_ECAP_IRO (DMAR_IOTLB_REG_OFFSET << 4)
185#define VTD_ECAP_QI (1ULL << 1)
186#define VTD_ECAP_DT (1ULL << 2)
187
188#define VTD_ECAP_IR (1ULL << 3)
189#define VTD_ECAP_EIM (1ULL << 4)
190#define VTD_ECAP_PT (1ULL << 6)
191#define VTD_ECAP_MHMV (15ULL << 20)
192
193
194
195#define VTD_CAP_FRO (DMAR_FRCD_REG_OFFSET << 20)
196#define VTD_CAP_NFR ((DMAR_FRCD_REG_NR - 1) << 40)
197#define VTD_DOMAIN_ID_SHIFT 16
198#define VTD_DOMAIN_ID_MASK ((1UL << VTD_DOMAIN_ID_SHIFT) - 1)
199#define VTD_CAP_ND (((VTD_DOMAIN_ID_SHIFT - 4) / 2) & 7ULL)
200#define VTD_ADDRESS_SIZE(aw) (1ULL << (aw))
201#define VTD_CAP_MGAW(aw) ((((aw) - 1) & 0x3fULL) << 16)
202#define VTD_MAMV 18ULL
203#define VTD_CAP_MAMV (VTD_MAMV << 48)
204#define VTD_CAP_PSI (1ULL << 39)
205#define VTD_CAP_SLLPS ((1ULL << 34) | (1ULL << 35))
206#define VTD_CAP_CM (1ULL << 7)
207
208
209#define VTD_CAP_SAGAW_SHIFT 8
210#define VTD_CAP_SAGAW_MASK (0x1fULL << VTD_CAP_SAGAW_SHIFT)
211
212#define VTD_CAP_SAGAW_39bit (0x2ULL << VTD_CAP_SAGAW_SHIFT)
213
214#define VTD_CAP_SAGAW_48bit (0x4ULL << VTD_CAP_SAGAW_SHIFT)
215
216
217#define VTD_IQT_QT(val) (((val) >> 4) & 0x7fffULL)
218
219
220#define VTD_IQA_IQA_MASK(aw) (VTD_HAW_MASK(aw) ^ 0xfffULL)
221#define VTD_IQA_QS 0x7ULL
222
223
224#define VTD_IQH_QH_SHIFT 4
225#define VTD_IQH_QH_MASK 0x7fff0ULL
226
227
228#define VTD_ICS_IWC 1UL
229
230
231#define VTD_IECTL_IM (1UL << 31)
232#define VTD_IECTL_IP (1UL << 30)
233
234
235#define VTD_FSTS_FRI_MASK 0xff00UL
236#define VTD_FSTS_FRI(val) ((((uint32_t)(val)) << 8) & VTD_FSTS_FRI_MASK)
237#define VTD_FSTS_IQE (1UL << 4)
238#define VTD_FSTS_PPF (1UL << 1)
239#define VTD_FSTS_PFO 1UL
240
241
242#define VTD_FECTL_IM (1UL << 31)
243#define VTD_FECTL_IP (1UL << 30)
244
245
246
247#define VTD_FRCD_F (1ULL << 63)
248#define VTD_FRCD_T (1ULL << 62)
249#define VTD_FRCD_FR(val) (((val) & 0xffULL) << 32)
250#define VTD_FRCD_SID_MASK 0xffffULL
251#define VTD_FRCD_SID(val) ((val) & VTD_FRCD_SID_MASK)
252
253#define VTD_FRCD_FI(val) ((val) & ~0xfffULL)
254
255
256typedef enum VTDFaultReason {
257 VTD_FR_RESERVED = 0,
258 VTD_FR_ROOT_ENTRY_P = 1,
259 VTD_FR_CONTEXT_ENTRY_P,
260 VTD_FR_CONTEXT_ENTRY_INV,
261 VTD_FR_ADDR_BEYOND_MGAW,
262 VTD_FR_WRITE,
263 VTD_FR_READ,
264
265 VTD_FR_PAGING_ENTRY_INV,
266 VTD_FR_ROOT_TABLE_INV,
267 VTD_FR_CONTEXT_TABLE_INV,
268
269 VTD_FR_ROOT_ENTRY_RSVD,
270
271 VTD_FR_CONTEXT_ENTRY_RSVD,
272
273
274
275 VTD_FR_PAGING_ENTRY_RSVD,
276
277
278
279
280 VTD_FR_CONTEXT_ENTRY_TT,
281
282
283 VTD_FR_IR_REQ_RSVD = 0x20,
284
285 VTD_FR_IR_INDEX_OVER = 0x21,
286 VTD_FR_IR_ENTRY_P = 0x22,
287 VTD_FR_IR_ROOT_INVAL = 0x23,
288 VTD_FR_IR_IRTE_RSVD = 0x24,
289
290 VTD_FR_IR_REQ_COMPAT = 0x25,
291
292 VTD_FR_IR_SID_ERR = 0x26,
293
294
295
296
297
298 VTD_FR_RESERVED_ERR,
299 VTD_FR_MAX,
300} VTDFaultReason;
301
302#define VTD_CONTEXT_CACHE_GEN_MAX 0xffffffffUL
303
304
305struct VTDInvDescIEC {
306 uint32_t type:4;
307 uint32_t granularity:1;
308 uint32_t resved_1:22;
309 uint32_t index_mask:5;
310 uint32_t index:16;
311 uint32_t reserved_2:16;
312};
313typedef struct VTDInvDescIEC VTDInvDescIEC;
314
315
316union VTDInvDesc {
317 struct {
318 uint64_t lo;
319 uint64_t hi;
320 };
321 union {
322 VTDInvDescIEC iec;
323 };
324};
325typedef union VTDInvDesc VTDInvDesc;
326
327
328#define VTD_INV_DESC_TYPE 0xf
329#define VTD_INV_DESC_CC 0x1
330#define VTD_INV_DESC_IOTLB 0x2
331#define VTD_INV_DESC_DEVICE 0x3
332#define VTD_INV_DESC_IEC 0x4
333
334#define VTD_INV_DESC_WAIT 0x5
335#define VTD_INV_DESC_NONE 0
336
337
338#define VTD_INV_DESC_WAIT_SW (1ULL << 5)
339#define VTD_INV_DESC_WAIT_IF (1ULL << 4)
340#define VTD_INV_DESC_WAIT_FN (1ULL << 6)
341#define VTD_INV_DESC_WAIT_DATA_SHIFT 32
342#define VTD_INV_DESC_WAIT_RSVD_LO 0Xffffff80ULL
343#define VTD_INV_DESC_WAIT_RSVD_HI 3ULL
344
345
346#define VTD_INV_DESC_CC_G (3ULL << 4)
347#define VTD_INV_DESC_CC_GLOBAL (1ULL << 4)
348#define VTD_INV_DESC_CC_DOMAIN (2ULL << 4)
349#define VTD_INV_DESC_CC_DEVICE (3ULL << 4)
350#define VTD_INV_DESC_CC_DID(val) (((val) >> 16) & VTD_DOMAIN_ID_MASK)
351#define VTD_INV_DESC_CC_SID(val) (((val) >> 32) & 0xffffUL)
352#define VTD_INV_DESC_CC_FM(val) (((val) >> 48) & 3UL)
353#define VTD_INV_DESC_CC_RSVD 0xfffc00000000ffc0ULL
354
355
356#define VTD_INV_DESC_IOTLB_G (3ULL << 4)
357#define VTD_INV_DESC_IOTLB_GLOBAL (1ULL << 4)
358#define VTD_INV_DESC_IOTLB_DOMAIN (2ULL << 4)
359#define VTD_INV_DESC_IOTLB_PAGE (3ULL << 4)
360#define VTD_INV_DESC_IOTLB_DID(val) (((val) >> 16) & VTD_DOMAIN_ID_MASK)
361#define VTD_INV_DESC_IOTLB_ADDR(val) ((val) & ~0xfffULL)
362#define VTD_INV_DESC_IOTLB_AM(val) ((val) & 0x3fULL)
363#define VTD_INV_DESC_IOTLB_RSVD_LO 0xffffffff0000ff00ULL
364#define VTD_INV_DESC_IOTLB_RSVD_HI 0xf80ULL
365
366
367#define VTD_INV_DESC_DEVICE_IOTLB_ADDR(val) ((val) & 0xfffffffffffff000ULL)
368#define VTD_INV_DESC_DEVICE_IOTLB_SIZE(val) ((val) & 0x1)
369#define VTD_INV_DESC_DEVICE_IOTLB_SID(val) (((val) >> 32) & 0xFFFFULL)
370#define VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI 0xffeULL
371#define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8
372
373
374#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw) \
375 (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
376#define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \
377 (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
378#define VTD_SPTE_PAGE_L3_RSVD_MASK(aw) \
379 (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
380#define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \
381 (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
382#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw) \
383 (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
384#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \
385 (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
386#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \
387 (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
388#define VTD_SPTE_LPAGE_L4_RSVD_MASK(aw) \
389 (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
390
391
392struct VTDIOTLBPageInvInfo {
393 uint16_t domain_id;
394 uint64_t addr;
395 uint8_t mask;
396};
397typedef struct VTDIOTLBPageInvInfo VTDIOTLBPageInvInfo;
398
399
400#define VTD_PAGE_SHIFT 12
401#define VTD_PAGE_SIZE (1ULL << VTD_PAGE_SHIFT)
402
403#define VTD_PAGE_SHIFT_4K 12
404#define VTD_PAGE_MASK_4K (~((1ULL << VTD_PAGE_SHIFT_4K) - 1))
405#define VTD_PAGE_SHIFT_2M 21
406#define VTD_PAGE_MASK_2M (~((1ULL << VTD_PAGE_SHIFT_2M) - 1))
407#define VTD_PAGE_SHIFT_1G 30
408#define VTD_PAGE_MASK_1G (~((1ULL << VTD_PAGE_SHIFT_1G) - 1))
409
410struct VTDRootEntry {
411 uint64_t val;
412 uint64_t rsvd;
413};
414typedef struct VTDRootEntry VTDRootEntry;
415
416
417#define VTD_ROOT_ENTRY_P 1ULL
418#define VTD_ROOT_ENTRY_CTP (~0xfffULL)
419
420#define VTD_ROOT_ENTRY_NR (VTD_PAGE_SIZE / sizeof(VTDRootEntry))
421#define VTD_ROOT_ENTRY_RSVD(aw) (0xffeULL | ~VTD_HAW_MASK(aw))
422
423
424
425#define VTD_CONTEXT_ENTRY_P (1ULL << 0)
426#define VTD_CONTEXT_ENTRY_FPD (1ULL << 1)
427#define VTD_CONTEXT_ENTRY_TT (3ULL << 2)
428#define VTD_CONTEXT_TT_MULTI_LEVEL 0
429#define VTD_CONTEXT_TT_DEV_IOTLB (1ULL << 2)
430#define VTD_CONTEXT_TT_PASS_THROUGH (2ULL << 2)
431
432#define VTD_CONTEXT_ENTRY_SLPTPTR (~0xfffULL)
433#define VTD_CONTEXT_ENTRY_RSVD_LO(aw) (0xff0ULL | ~VTD_HAW_MASK(aw))
434
435#define VTD_CONTEXT_ENTRY_AW 7ULL
436#define VTD_CONTEXT_ENTRY_DID(val) (((val) >> 8) & VTD_DOMAIN_ID_MASK)
437#define VTD_CONTEXT_ENTRY_RSVD_HI 0xffffffffff000080ULL
438
439#define VTD_CONTEXT_ENTRY_NR (VTD_PAGE_SIZE / sizeof(VTDContextEntry))
440
441
442#define VTD_SL_PT_PAGE_SIZE_MASK (1ULL << 7)
443
444#define VTD_SL_LEVEL_BITS 9
445
446
447#define VTD_SL_PML4_LEVEL 4
448#define VTD_SL_PDP_LEVEL 3
449#define VTD_SL_PD_LEVEL 2
450#define VTD_SL_PT_LEVEL 1
451#define VTD_SL_PT_ENTRY_NR 512
452
453
454#define VTD_SL_RW_MASK 3ULL
455#define VTD_SL_R 1ULL
456#define VTD_SL_W (1ULL << 1)
457#define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw))
458#define VTD_SL_IGN_COM 0xbff0000000000000ULL
459
460#endif
461