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63#include "qemu/osdep.h"
64#include "hw/hw.h"
65#include "hw/pci/msi.h"
66#include "hw/pci/pci.h"
67#include "hw/isa/isa.h"
68#include "sysemu/dma.h"
69#include "hw/ide/pci.h"
70#include "ahci_internal.h"
71
72#define ICH9_MSI_CAP_OFFSET 0x80
73#define ICH9_SATA_CAP_OFFSET 0xA8
74
75#define ICH9_IDP_BAR 4
76#define ICH9_MEM_BAR 5
77
78#define ICH9_IDP_INDEX 0x10
79#define ICH9_IDP_INDEX_LOG2 0x04
80
81static const VMStateDescription vmstate_ich9_ahci = {
82 .name = "ich9_ahci",
83 .version_id = 1,
84 .fields = (VMStateField[]) {
85 VMSTATE_PCI_DEVICE(parent_obj, AHCIPCIState),
86 VMSTATE_AHCI(ahci, AHCIPCIState),
87 VMSTATE_END_OF_LIST()
88 },
89};
90
91static void pci_ich9_reset(DeviceState *dev)
92{
93 AHCIPCIState *d = ICH_AHCI(dev);
94
95 ahci_reset(&d->ahci);
96}
97
98static void pci_ich9_ahci_init(Object *obj)
99{
100 struct AHCIPCIState *d = ICH_AHCI(obj);
101
102 ahci_init(&d->ahci, DEVICE(obj));
103}
104
105static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp)
106{
107 struct AHCIPCIState *d;
108 int sata_cap_offset;
109 uint8_t *sata_cap;
110 d = ICH_AHCI(dev);
111 int ret;
112
113 ahci_realize(&d->ahci, DEVICE(dev), pci_get_address_space(dev), 6);
114
115 pci_config_set_prog_interface(dev->config, AHCI_PROGMODE_MAJOR_REV_1);
116
117 dev->config[PCI_CACHE_LINE_SIZE] = 0x08;
118 dev->config[PCI_LATENCY_TIMER] = 0x00;
119 pci_config_set_interrupt_pin(dev->config, 1);
120
121
122 dev->config[0x90] = 1 << 6;
123
124 d->ahci.irq = pci_allocate_irq(dev);
125
126 pci_register_bar(dev, ICH9_IDP_BAR, PCI_BASE_ADDRESS_SPACE_IO,
127 &d->ahci.idp);
128 pci_register_bar(dev, ICH9_MEM_BAR, PCI_BASE_ADDRESS_SPACE_MEMORY,
129 &d->ahci.mem);
130
131 sata_cap_offset = pci_add_capability(dev, PCI_CAP_ID_SATA,
132 ICH9_SATA_CAP_OFFSET, SATA_CAP_SIZE,
133 errp);
134 if (sata_cap_offset < 0) {
135 return;
136 }
137
138 sata_cap = dev->config + sata_cap_offset;
139 pci_set_word(sata_cap + SATA_CAP_REV, 0x10);
140 pci_set_long(sata_cap + SATA_CAP_BAR,
141 (ICH9_IDP_BAR + 0x4) | (ICH9_IDP_INDEX_LOG2 << 4));
142 d->ahci.idp_offset = ICH9_IDP_INDEX;
143
144
145
146
147 ret = msi_init(dev, ICH9_MSI_CAP_OFFSET, 1, true, false, NULL);
148
149
150 assert(!ret || ret == -ENOTSUP);
151}
152
153static void pci_ich9_uninit(PCIDevice *dev)
154{
155 struct AHCIPCIState *d;
156 d = ICH_AHCI(dev);
157
158 msi_uninit(dev);
159 ahci_uninit(&d->ahci);
160 qemu_free_irq(d->ahci.irq);
161}
162
163static void ich_ahci_class_init(ObjectClass *klass, void *data)
164{
165 DeviceClass *dc = DEVICE_CLASS(klass);
166 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
167
168 k->realize = pci_ich9_ahci_realize;
169 k->exit = pci_ich9_uninit;
170 k->vendor_id = PCI_VENDOR_ID_INTEL;
171 k->device_id = PCI_DEVICE_ID_INTEL_82801IR;
172 k->revision = 0x02;
173 k->class_id = PCI_CLASS_STORAGE_SATA;
174 dc->vmsd = &vmstate_ich9_ahci;
175 dc->reset = pci_ich9_reset;
176 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
177}
178
179static const TypeInfo ich_ahci_info = {
180 .name = TYPE_ICH9_AHCI,
181 .parent = TYPE_PCI_DEVICE,
182 .instance_size = sizeof(AHCIPCIState),
183 .instance_init = pci_ich9_ahci_init,
184 .class_init = ich_ahci_class_init,
185 .interfaces = (InterfaceInfo[]) {
186 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
187 { },
188 },
189};
190
191static void ich_ahci_register_types(void)
192{
193 type_register_static(&ich_ahci_info);
194}
195
196type_init(ich_ahci_register_types)
197