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24#include "qemu/osdep.h"
25#include "qemu/units.h"
26#include "qapi/error.h"
27#include "qemu-common.h"
28#include "cpu.h"
29#include "hw/hw.h"
30#include "hw/ppc/ppc.h"
31#include "ppc405.h"
32#include "hw/timer/m48t59.h"
33#include "hw/block/flash.h"
34#include "sysemu/sysemu.h"
35#include "sysemu/qtest.h"
36#include "sysemu/block-backend.h"
37#include "hw/boards.h"
38#include "qemu/log.h"
39#include "qemu/error-report.h"
40#include "hw/loader.h"
41#include "exec/address-spaces.h"
42
43#define BIOS_FILENAME "ppc405_rom.bin"
44#define BIOS_SIZE (2 * MiB)
45
46#define KERNEL_LOAD_ADDR 0x00000000
47#define INITRD_LOAD_ADDR 0x01800000
48
49#define USE_FLASH_BIOS
50
51
52
53
54
55
56
57
58
59
60
61
62
63typedef struct ref405ep_fpga_t ref405ep_fpga_t;
64struct ref405ep_fpga_t {
65 uint8_t reg0;
66 uint8_t reg1;
67};
68
69static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
70{
71 ref405ep_fpga_t *fpga;
72 uint32_t ret;
73
74 fpga = opaque;
75 switch (addr) {
76 case 0x0:
77 ret = fpga->reg0;
78 break;
79 case 0x1:
80 ret = fpga->reg1;
81 break;
82 default:
83 ret = 0;
84 break;
85 }
86
87 return ret;
88}
89
90static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
91 unsigned size)
92{
93 ref405ep_fpga_t *fpga;
94
95 fpga = opaque;
96 switch (addr) {
97 case 0x0:
98
99 break;
100 case 0x1:
101 fpga->reg1 = value;
102 break;
103 default:
104 break;
105 }
106}
107
108static const MemoryRegionOps ref405ep_fpga_ops = {
109 .read = ref405ep_fpga_readb,
110 .write = ref405ep_fpga_writeb,
111 .impl.min_access_size = 1,
112 .impl.max_access_size = 1,
113 .valid.min_access_size = 1,
114 .valid.max_access_size = 4,
115 .endianness = DEVICE_BIG_ENDIAN,
116};
117
118static void ref405ep_fpga_reset (void *opaque)
119{
120 ref405ep_fpga_t *fpga;
121
122 fpga = opaque;
123 fpga->reg0 = 0x00;
124 fpga->reg1 = 0x0F;
125}
126
127static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
128{
129 ref405ep_fpga_t *fpga;
130 MemoryRegion *fpga_memory = g_new(MemoryRegion, 1);
131
132 fpga = g_malloc0(sizeof(ref405ep_fpga_t));
133 memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga,
134 "fpga", 0x00000100);
135 memory_region_add_subregion(sysmem, base, fpga_memory);
136 qemu_register_reset(&ref405ep_fpga_reset, fpga);
137}
138
139static void ref405ep_init(MachineState *machine)
140{
141 ram_addr_t ram_size = machine->ram_size;
142 const char *kernel_filename = machine->kernel_filename;
143 const char *kernel_cmdline = machine->kernel_cmdline;
144 const char *initrd_filename = machine->initrd_filename;
145 char *filename;
146 ppc4xx_bd_info_t bd;
147 CPUPPCState *env;
148 qemu_irq *pic;
149 MemoryRegion *bios;
150 MemoryRegion *sram = g_new(MemoryRegion, 1);
151 ram_addr_t bdloc;
152 MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
153 hwaddr ram_bases[2], ram_sizes[2];
154 target_ulong sram_size;
155 long bios_size;
156
157
158 target_ulong kernel_base, initrd_base;
159 long kernel_size, initrd_size;
160 int linux_boot;
161 int fl_idx, fl_sectors, len;
162 DriveInfo *dinfo;
163 MemoryRegion *sysmem = get_system_memory();
164
165
166 memory_region_allocate_system_memory(&ram_memories[0], NULL, "ef405ep.ram",
167 0x08000000);
168 ram_bases[0] = 0;
169 ram_sizes[0] = 0x08000000;
170 memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
171 ram_bases[1] = 0x00000000;
172 ram_sizes[1] = 0x00000000;
173 ram_size = 128 * MiB;
174#ifdef DEBUG_BOARD_INIT
175 printf("%s: register cpu\n", __func__);
176#endif
177 env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
178 33333333, &pic, kernel_filename == NULL ? 0 : 1);
179
180 sram_size = 512 * KiB;
181 memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size,
182 &error_fatal);
183 memory_region_add_subregion(sysmem, 0xFFF00000, sram);
184
185#ifdef DEBUG_BOARD_INIT
186 printf("%s: register BIOS\n", __func__);
187#endif
188 fl_idx = 0;
189#ifdef USE_FLASH_BIOS
190 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
191 if (dinfo) {
192 BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
193
194 bios_size = blk_getlength(blk);
195 fl_sectors = (bios_size + 65535) >> 16;
196#ifdef DEBUG_BOARD_INIT
197 printf("Register parallel flash %d size %lx"
198 " at addr %lx '%s' %d\n",
199 fl_idx, bios_size, -bios_size,
200 blk_name(blk), fl_sectors);
201#endif
202 pflash_cfi02_register((uint32_t)(-bios_size),
203 NULL, "ef405ep.bios", bios_size,
204 blk, 65536, fl_sectors, 1,
205 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
206 1);
207 fl_idx++;
208 } else
209#endif
210 {
211#ifdef DEBUG_BOARD_INIT
212 printf("Load BIOS from file\n");
213#endif
214 bios = g_new(MemoryRegion, 1);
215 memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE,
216 &error_fatal);
217
218 if (bios_name == NULL)
219 bios_name = BIOS_FILENAME;
220 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
221 if (filename) {
222 bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
223 g_free(filename);
224 if (bios_size < 0 || bios_size > BIOS_SIZE) {
225 error_report("Could not load PowerPC BIOS '%s'", bios_name);
226 exit(1);
227 }
228 bios_size = (bios_size + 0xfff) & ~0xfff;
229 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
230 } else if (!qtest_enabled() || kernel_filename != NULL) {
231 error_report("Could not load PowerPC BIOS '%s'", bios_name);
232 exit(1);
233 } else {
234
235 bios_size = -1;
236 }
237 memory_region_set_readonly(bios, true);
238 }
239
240#ifdef DEBUG_BOARD_INIT
241 printf("%s: register FPGA\n", __func__);
242#endif
243 ref405ep_fpga_init(sysmem, 0xF0300000);
244
245#ifdef DEBUG_BOARD_INIT
246 printf("%s: register NVRAM\n", __func__);
247#endif
248 m48t59_init(NULL, 0xF0000000, 0, 8192, 1968, 8);
249
250 linux_boot = (kernel_filename != NULL);
251 if (linux_boot) {
252#ifdef DEBUG_BOARD_INIT
253 printf("%s: load kernel\n", __func__);
254#endif
255 memset(&bd, 0, sizeof(bd));
256 bd.bi_memstart = 0x00000000;
257 bd.bi_memsize = ram_size;
258 bd.bi_flashstart = -bios_size;
259 bd.bi_flashsize = -bios_size;
260 bd.bi_flashoffset = 0;
261 bd.bi_sramstart = 0xFFF00000;
262 bd.bi_sramsize = sram_size;
263 bd.bi_bootflags = 0;
264 bd.bi_intfreq = 133333333;
265 bd.bi_busfreq = 33333333;
266 bd.bi_baudrate = 115200;
267 bd.bi_s_version[0] = 'Q';
268 bd.bi_s_version[1] = 'M';
269 bd.bi_s_version[2] = 'U';
270 bd.bi_s_version[3] = '\0';
271 bd.bi_r_version[0] = 'Q';
272 bd.bi_r_version[1] = 'E';
273 bd.bi_r_version[2] = 'M';
274 bd.bi_r_version[3] = 'U';
275 bd.bi_r_version[4] = '\0';
276 bd.bi_procfreq = 133333333;
277 bd.bi_plb_busfreq = 33333333;
278 bd.bi_pci_busfreq = 33333333;
279 bd.bi_opbfreq = 33333333;
280 bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
281 env->gpr[3] = bdloc;
282 kernel_base = KERNEL_LOAD_ADDR;
283
284 kernel_size = load_image_targphys(kernel_filename, kernel_base,
285 ram_size - kernel_base);
286 if (kernel_size < 0) {
287 error_report("could not load kernel '%s'", kernel_filename);
288 exit(1);
289 }
290 printf("Load kernel size %ld at " TARGET_FMT_lx,
291 kernel_size, kernel_base);
292
293 if (initrd_filename) {
294 initrd_base = INITRD_LOAD_ADDR;
295 initrd_size = load_image_targphys(initrd_filename, initrd_base,
296 ram_size - initrd_base);
297 if (initrd_size < 0) {
298 error_report("could not load initial ram disk '%s'",
299 initrd_filename);
300 exit(1);
301 }
302 } else {
303 initrd_base = 0;
304 initrd_size = 0;
305 }
306 env->gpr[4] = initrd_base;
307 env->gpr[5] = initrd_size;
308 if (kernel_cmdline != NULL) {
309 len = strlen(kernel_cmdline);
310 bdloc -= ((len + 255) & ~255);
311 cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1);
312 env->gpr[6] = bdloc;
313 env->gpr[7] = bdloc + len;
314 } else {
315 env->gpr[6] = 0;
316 env->gpr[7] = 0;
317 }
318 env->nip = KERNEL_LOAD_ADDR;
319 } else {
320 kernel_base = 0;
321 kernel_size = 0;
322 initrd_base = 0;
323 initrd_size = 0;
324 bdloc = 0;
325 }
326#ifdef DEBUG_BOARD_INIT
327 printf("bdloc " RAM_ADDR_FMT "\n", bdloc);
328 printf("%s: Done\n", __func__);
329#endif
330}
331
332static void ref405ep_class_init(ObjectClass *oc, void *data)
333{
334 MachineClass *mc = MACHINE_CLASS(oc);
335
336 mc->desc = "ref405ep";
337 mc->init = ref405ep_init;
338}
339
340static const TypeInfo ref405ep_type = {
341 .name = MACHINE_TYPE_NAME("ref405ep"),
342 .parent = TYPE_MACHINE,
343 .class_init = ref405ep_class_init,
344};
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364
365typedef struct taihu_cpld_t taihu_cpld_t;
366struct taihu_cpld_t {
367 uint8_t reg0;
368 uint8_t reg1;
369};
370
371static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size)
372{
373 taihu_cpld_t *cpld;
374 uint32_t ret;
375
376 cpld = opaque;
377 switch (addr) {
378 case 0x0:
379 ret = cpld->reg0;
380 break;
381 case 0x1:
382 ret = cpld->reg1;
383 break;
384 default:
385 ret = 0;
386 break;
387 }
388
389 return ret;
390}
391
392static void taihu_cpld_write(void *opaque, hwaddr addr,
393 uint64_t value, unsigned size)
394{
395 taihu_cpld_t *cpld;
396
397 cpld = opaque;
398 switch (addr) {
399 case 0x0:
400
401 break;
402 case 0x1:
403 cpld->reg1 = value;
404 break;
405 default:
406 break;
407 }
408}
409
410static const MemoryRegionOps taihu_cpld_ops = {
411 .read = taihu_cpld_read,
412 .write = taihu_cpld_write,
413 .impl = {
414 .min_access_size = 1,
415 .max_access_size = 1,
416 },
417 .endianness = DEVICE_NATIVE_ENDIAN,
418};
419
420static void taihu_cpld_reset (void *opaque)
421{
422 taihu_cpld_t *cpld;
423
424 cpld = opaque;
425 cpld->reg0 = 0x01;
426 cpld->reg1 = 0x80;
427}
428
429static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base)
430{
431 taihu_cpld_t *cpld;
432 MemoryRegion *cpld_memory = g_new(MemoryRegion, 1);
433
434 cpld = g_malloc0(sizeof(taihu_cpld_t));
435 memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100);
436 memory_region_add_subregion(sysmem, base, cpld_memory);
437 qemu_register_reset(&taihu_cpld_reset, cpld);
438}
439
440static void taihu_405ep_init(MachineState *machine)
441{
442 ram_addr_t ram_size = machine->ram_size;
443 const char *kernel_filename = machine->kernel_filename;
444 const char *initrd_filename = machine->initrd_filename;
445 char *filename;
446 qemu_irq *pic;
447 MemoryRegion *sysmem = get_system_memory();
448 MemoryRegion *bios;
449 MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
450 MemoryRegion *ram = g_malloc0(sizeof(*ram));
451 hwaddr ram_bases[2], ram_sizes[2];
452 long bios_size;
453 target_ulong kernel_base, initrd_base;
454 long kernel_size, initrd_size;
455 int linux_boot;
456 int fl_idx, fl_sectors;
457 DriveInfo *dinfo;
458
459
460 ram_size = 0x08000000;
461 memory_region_allocate_system_memory(ram, NULL, "taihu_405ep.ram",
462 ram_size);
463
464 ram_bases[0] = 0;
465 ram_sizes[0] = 0x04000000;
466 memory_region_init_alias(&ram_memories[0], NULL,
467 "taihu_405ep.ram-0", ram, ram_bases[0],
468 ram_sizes[0]);
469 ram_bases[1] = 0x04000000;
470 ram_sizes[1] = 0x04000000;
471 memory_region_init_alias(&ram_memories[1], NULL,
472 "taihu_405ep.ram-1", ram, ram_bases[1],
473 ram_sizes[1]);
474#ifdef DEBUG_BOARD_INIT
475 printf("%s: register cpu\n", __func__);
476#endif
477 ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
478 33333333, &pic, kernel_filename == NULL ? 0 : 1);
479
480#ifdef DEBUG_BOARD_INIT
481 printf("%s: register BIOS\n", __func__);
482#endif
483 fl_idx = 0;
484#if defined(USE_FLASH_BIOS)
485 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
486 if (dinfo) {
487 BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
488
489 bios_size = blk_getlength(blk);
490
491
492 fl_sectors = (bios_size + 65535) >> 16;
493#ifdef DEBUG_BOARD_INIT
494 printf("Register parallel flash %d size %lx"
495 " at addr %lx '%s' %d\n",
496 fl_idx, bios_size, -bios_size,
497 blk_name(blk), fl_sectors);
498#endif
499 pflash_cfi02_register((uint32_t)(-bios_size),
500 NULL, "taihu_405ep.bios", bios_size,
501 blk, 65536, fl_sectors, 1,
502 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
503 1);
504 fl_idx++;
505 } else
506#endif
507 {
508#ifdef DEBUG_BOARD_INIT
509 printf("Load BIOS from file\n");
510#endif
511 if (bios_name == NULL)
512 bios_name = BIOS_FILENAME;
513 bios = g_new(MemoryRegion, 1);
514 memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE,
515 &error_fatal);
516 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
517 if (filename) {
518 bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
519 g_free(filename);
520 if (bios_size < 0 || bios_size > BIOS_SIZE) {
521 error_report("Could not load PowerPC BIOS '%s'", bios_name);
522 exit(1);
523 }
524 bios_size = (bios_size + 0xfff) & ~0xfff;
525 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
526 } else if (!qtest_enabled()) {
527 error_report("Could not load PowerPC BIOS '%s'", bios_name);
528 exit(1);
529 }
530 memory_region_set_readonly(bios, true);
531 }
532
533 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
534 if (dinfo) {
535 BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
536
537 bios_size = blk_getlength(blk);
538
539 bios_size = 32 * MiB;
540 fl_sectors = (bios_size + 65535) >> 16;
541#ifdef DEBUG_BOARD_INIT
542 printf("Register parallel flash %d size %lx"
543 " at addr " TARGET_FMT_lx " '%s'\n",
544 fl_idx, bios_size, (target_ulong)0xfc000000,
545 blk_name(blk));
546#endif
547 pflash_cfi02_register(0xfc000000, NULL, "taihu_405ep.flash", bios_size,
548 blk, 65536, fl_sectors, 1,
549 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
550 1);
551 fl_idx++;
552 }
553
554#ifdef DEBUG_BOARD_INIT
555 printf("%s: register CPLD\n", __func__);
556#endif
557 taihu_cpld_init(sysmem, 0x50100000);
558
559 linux_boot = (kernel_filename != NULL);
560 if (linux_boot) {
561#ifdef DEBUG_BOARD_INIT
562 printf("%s: load kernel\n", __func__);
563#endif
564 kernel_base = KERNEL_LOAD_ADDR;
565
566 kernel_size = load_image_targphys(kernel_filename, kernel_base,
567 ram_size - kernel_base);
568 if (kernel_size < 0) {
569 error_report("could not load kernel '%s'", kernel_filename);
570 exit(1);
571 }
572
573 if (initrd_filename) {
574 initrd_base = INITRD_LOAD_ADDR;
575 initrd_size = load_image_targphys(initrd_filename, initrd_base,
576 ram_size - initrd_base);
577 if (initrd_size < 0) {
578 error_report("could not load initial ram disk '%s'",
579 initrd_filename);
580 exit(1);
581 }
582 } else {
583 initrd_base = 0;
584 initrd_size = 0;
585 }
586 } else {
587 kernel_base = 0;
588 kernel_size = 0;
589 initrd_base = 0;
590 initrd_size = 0;
591 }
592#ifdef DEBUG_BOARD_INIT
593 printf("%s: Done\n", __func__);
594#endif
595}
596
597static void taihu_class_init(ObjectClass *oc, void *data)
598{
599 MachineClass *mc = MACHINE_CLASS(oc);
600
601 mc->desc = "taihu";
602 mc->init = taihu_405ep_init;
603}
604
605static const TypeInfo taihu_type = {
606 .name = MACHINE_TYPE_NAME("taihu"),
607 .parent = TYPE_MACHINE,
608 .class_init = taihu_class_init,
609};
610
611static void ppc405_machine_init(void)
612{
613 type_register_static(&ref405ep_type);
614 type_register_static(&taihu_type);
615}
616
617type_init(ppc405_machine_init)
618
