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19#include "qemu/osdep.h"
20#include "qemu/log.h"
21#include "trace.h"
22#include "qapi/error.h"
23#include "qemu/main-loop.h"
24#include "sysemu/watchdog.h"
25#include "hw/sysbus.h"
26#include "hw/registerfields.h"
27#include "hw/watchdog/cmsdk-apb-watchdog.h"
28
29REG32(WDOGLOAD, 0x0)
30REG32(WDOGVALUE, 0x4)
31REG32(WDOGCONTROL, 0x8)
32 FIELD(WDOGCONTROL, INTEN, 0, 1)
33 FIELD(WDOGCONTROL, RESEN, 1, 1)
34#define R_WDOGCONTROL_VALID_MASK (R_WDOGCONTROL_INTEN_MASK | \
35 R_WDOGCONTROL_RESEN_MASK)
36REG32(WDOGINTCLR, 0xc)
37REG32(WDOGRIS, 0x10)
38 FIELD(WDOGRIS, INT, 0, 1)
39REG32(WDOGMIS, 0x14)
40REG32(WDOGLOCK, 0xc00)
41#define WDOG_UNLOCK_VALUE 0x1ACCE551
42REG32(WDOGITCR, 0xf00)
43 FIELD(WDOGITCR, ENABLE, 0, 1)
44#define R_WDOGITCR_VALID_MASK R_WDOGITCR_ENABLE_MASK
45REG32(WDOGITOP, 0xf04)
46 FIELD(WDOGITOP, WDOGRES, 0, 1)
47 FIELD(WDOGITOP, WDOGINT, 1, 1)
48#define R_WDOGITOP_VALID_MASK (R_WDOGITOP_WDOGRES_MASK | \
49 R_WDOGITOP_WDOGINT_MASK)
50REG32(PID4, 0xfd0)
51REG32(PID5, 0xfd4)
52REG32(PID6, 0xfd8)
53REG32(PID7, 0xfdc)
54REG32(PID0, 0xfe0)
55REG32(PID1, 0xfe4)
56REG32(PID2, 0xfe8)
57REG32(PID3, 0xfec)
58REG32(CID0, 0xff0)
59REG32(CID1, 0xff4)
60REG32(CID2, 0xff8)
61REG32(CID3, 0xffc)
62
63
64static const int watchdog_id[] = {
65 0x04, 0x00, 0x00, 0x00,
66 0x24, 0xb8, 0x1b, 0x00,
67 0x0d, 0xf0, 0x05, 0xb1,
68};
69
70static bool cmsdk_apb_watchdog_intstatus(CMSDKAPBWatchdog *s)
71{
72
73 return s->intstatus && (s->control & R_WDOGCONTROL_INTEN_MASK);
74}
75
76static bool cmsdk_apb_watchdog_resetstatus(CMSDKAPBWatchdog *s)
77{
78
79 return s->resetstatus && (s->control & R_WDOGCONTROL_RESEN_MASK);
80}
81
82static void cmsdk_apb_watchdog_update(CMSDKAPBWatchdog *s)
83{
84 bool wdogint;
85 bool wdogres;
86
87 if (s->itcr) {
88 wdogint = s->itop & R_WDOGITOP_WDOGINT_MASK;
89 wdogres = s->itop & R_WDOGITOP_WDOGRES_MASK;
90 } else {
91 wdogint = cmsdk_apb_watchdog_intstatus(s);
92 wdogres = cmsdk_apb_watchdog_resetstatus(s);
93 }
94
95 qemu_set_irq(s->wdogint, wdogint);
96 if (wdogres) {
97 watchdog_perform_action();
98 }
99}
100
101static uint64_t cmsdk_apb_watchdog_read(void *opaque, hwaddr offset,
102 unsigned size)
103{
104 CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);
105 uint64_t r;
106
107 switch (offset) {
108 case A_WDOGLOAD:
109 r = ptimer_get_limit(s->timer);
110 break;
111 case A_WDOGVALUE:
112 r = ptimer_get_count(s->timer);
113 break;
114 case A_WDOGCONTROL:
115 r = s->control;
116 break;
117 case A_WDOGRIS:
118 r = s->intstatus;
119 break;
120 case A_WDOGMIS:
121 r = cmsdk_apb_watchdog_intstatus(s);
122 break;
123 case A_WDOGLOCK:
124 r = s->lock;
125 break;
126 case A_WDOGITCR:
127 r = s->itcr;
128 break;
129 case A_PID4 ... A_CID3:
130 r = watchdog_id[(offset - A_PID4) / 4];
131 break;
132 case A_WDOGINTCLR:
133 case A_WDOGITOP:
134 qemu_log_mask(LOG_GUEST_ERROR,
135 "CMSDK APB watchdog read: read of WO offset %x\n",
136 (int)offset);
137 r = 0;
138 break;
139 default:
140 qemu_log_mask(LOG_GUEST_ERROR,
141 "CMSDK APB watchdog read: bad offset %x\n", (int)offset);
142 r = 0;
143 break;
144 }
145 trace_cmsdk_apb_watchdog_read(offset, r, size);
146 return r;
147}
148
149static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset,
150 uint64_t value, unsigned size)
151{
152 CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);
153
154 trace_cmsdk_apb_watchdog_write(offset, value, size);
155
156 if (s->lock && offset != A_WDOGLOCK) {
157
158 qemu_log_mask(LOG_GUEST_ERROR,
159 "CMSDK APB watchdog write: write to locked watchdog\n");
160 return;
161 }
162
163 switch (offset) {
164 case A_WDOGLOAD:
165
166
167
168
169 ptimer_set_limit(s->timer, value, 1);
170 ptimer_run(s->timer, 0);
171 break;
172 case A_WDOGCONTROL:
173 s->control = value & R_WDOGCONTROL_VALID_MASK;
174 cmsdk_apb_watchdog_update(s);
175 break;
176 case A_WDOGINTCLR:
177 s->intstatus = 0;
178 ptimer_set_count(s->timer, ptimer_get_limit(s->timer));
179 cmsdk_apb_watchdog_update(s);
180 break;
181 case A_WDOGLOCK:
182 s->lock = (value != WDOG_UNLOCK_VALUE);
183 break;
184 case A_WDOGITCR:
185 s->itcr = value & R_WDOGITCR_VALID_MASK;
186 cmsdk_apb_watchdog_update(s);
187 break;
188 case A_WDOGITOP:
189 s->itop = value & R_WDOGITOP_VALID_MASK;
190 cmsdk_apb_watchdog_update(s);
191 break;
192 case A_WDOGVALUE:
193 case A_WDOGRIS:
194 case A_WDOGMIS:
195 case A_PID4 ... A_CID3:
196 qemu_log_mask(LOG_GUEST_ERROR,
197 "CMSDK APB watchdog write: write to RO offset 0x%x\n",
198 (int)offset);
199 break;
200 default:
201 qemu_log_mask(LOG_GUEST_ERROR,
202 "CMSDK APB watchdog write: bad offset 0x%x\n",
203 (int)offset);
204 break;
205 }
206}
207
208static const MemoryRegionOps cmsdk_apb_watchdog_ops = {
209 .read = cmsdk_apb_watchdog_read,
210 .write = cmsdk_apb_watchdog_write,
211 .endianness = DEVICE_LITTLE_ENDIAN,
212
213 .impl.min_access_size = 4,
214 .impl.max_access_size = 4,
215 .valid.min_access_size = 1,
216 .valid.max_access_size = 4,
217};
218
219static void cmsdk_apb_watchdog_tick(void *opaque)
220{
221 CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);
222
223 if (!s->intstatus) {
224
225 s->intstatus = R_WDOGRIS_INT_MASK;
226 } else {
227
228 s->resetstatus = 1;
229 ptimer_stop(s->timer);
230 }
231 cmsdk_apb_watchdog_update(s);
232}
233
234static void cmsdk_apb_watchdog_reset(DeviceState *dev)
235{
236 CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev);
237
238 trace_cmsdk_apb_watchdog_reset();
239 s->control = 0;
240 s->intstatus = 0;
241 s->lock = 0;
242 s->itcr = 0;
243 s->itop = 0;
244 s->resetstatus = 0;
245
246 ptimer_set_limit(s->timer, 0xffffffff, 1);
247 ptimer_run(s->timer, 0);
248}
249
250static void cmsdk_apb_watchdog_init(Object *obj)
251{
252 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
253 CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(obj);
254
255 memory_region_init_io(&s->iomem, obj, &cmsdk_apb_watchdog_ops,
256 s, "cmsdk-apb-watchdog", 0x1000);
257 sysbus_init_mmio(sbd, &s->iomem);
258 sysbus_init_irq(sbd, &s->wdogint);
259}
260
261static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp)
262{
263 CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev);
264 QEMUBH *bh;
265
266 if (s->wdogclk_frq == 0) {
267 error_setg(errp,
268 "CMSDK APB watchdog: wdogclk-frq property must be set");
269 return;
270 }
271
272 bh = qemu_bh_new(cmsdk_apb_watchdog_tick, s);
273 s->timer = ptimer_init(bh,
274 PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |
275 PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT |
276 PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
277 PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
278
279 ptimer_set_freq(s->timer, s->wdogclk_frq);
280}
281
282static const VMStateDescription cmsdk_apb_watchdog_vmstate = {
283 .name = "cmsdk-apb-watchdog",
284 .version_id = 1,
285 .minimum_version_id = 1,
286 .fields = (VMStateField[]) {
287 VMSTATE_PTIMER(timer, CMSDKAPBWatchdog),
288 VMSTATE_UINT32(control, CMSDKAPBWatchdog),
289 VMSTATE_UINT32(intstatus, CMSDKAPBWatchdog),
290 VMSTATE_UINT32(lock, CMSDKAPBWatchdog),
291 VMSTATE_UINT32(itcr, CMSDKAPBWatchdog),
292 VMSTATE_UINT32(itop, CMSDKAPBWatchdog),
293 VMSTATE_UINT32(resetstatus, CMSDKAPBWatchdog),
294 VMSTATE_END_OF_LIST()
295 }
296};
297
298static Property cmsdk_apb_watchdog_properties[] = {
299 DEFINE_PROP_UINT32("wdogclk-frq", CMSDKAPBWatchdog, wdogclk_frq, 0),
300 DEFINE_PROP_END_OF_LIST(),
301};
302
303static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data)
304{
305 DeviceClass *dc = DEVICE_CLASS(klass);
306
307 dc->realize = cmsdk_apb_watchdog_realize;
308 dc->vmsd = &cmsdk_apb_watchdog_vmstate;
309 dc->reset = cmsdk_apb_watchdog_reset;
310 dc->props = cmsdk_apb_watchdog_properties;
311}
312
313static const TypeInfo cmsdk_apb_watchdog_info = {
314 .name = TYPE_CMSDK_APB_WATCHDOG,
315 .parent = TYPE_SYS_BUS_DEVICE,
316 .instance_size = sizeof(CMSDKAPBWatchdog),
317 .instance_init = cmsdk_apb_watchdog_init,
318 .class_init = cmsdk_apb_watchdog_class_init,
319};
320
321static void cmsdk_apb_watchdog_register_types(void)
322{
323 type_register_static(&cmsdk_apb_watchdog_info);
324}
325
326type_init(cmsdk_apb_watchdog_register_types);
327
