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19#ifndef CADENCE_UART_H
20
21#include "hw/sysbus.h"
22#include "chardev/char-fe.h"
23#include "qemu/timer.h"
24
25#define CADENCE_UART_RX_FIFO_SIZE 16
26#define CADENCE_UART_TX_FIFO_SIZE 16
27
28#define CADENCE_UART_R_MAX (0x48/4)
29
30#define TYPE_CADENCE_UART "cadence_uart"
31#define CADENCE_UART(obj) OBJECT_CHECK(CadenceUARTState, (obj), \
32 TYPE_CADENCE_UART)
33
34typedef struct {
35
36 SysBusDevice parent_obj;
37
38
39 MemoryRegion iomem;
40 uint32_t r[CADENCE_UART_R_MAX];
41 uint8_t rx_fifo[CADENCE_UART_RX_FIFO_SIZE];
42 uint8_t tx_fifo[CADENCE_UART_TX_FIFO_SIZE];
43 uint32_t rx_wpos;
44 uint32_t rx_count;
45 uint32_t tx_count;
46 uint64_t char_tx_time;
47 CharBackend chr;
48 qemu_irq irq;
49 QEMUTimer *fifo_trigger_handle;
50} CadenceUARTState;
51
52static inline DeviceState *cadence_uart_create(hwaddr addr,
53 qemu_irq irq,
54 Chardev *chr)
55{
56 DeviceState *dev;
57 SysBusDevice *s;
58
59 dev = qdev_create(NULL, TYPE_CADENCE_UART);
60 s = SYS_BUS_DEVICE(dev);
61 qdev_prop_set_chr(dev, "chardev", chr);
62 qdev_init_nofail(dev);
63 sysbus_mmio_map(s, 0, addr);
64 sysbus_connect_irq(s, 0, irq);
65
66 return dev;
67}
68
69#define CADENCE_UART_H
70#endif
71