1#ifndef HW_ICH9_H
2#define HW_ICH9_H
3
4#include "hw/hw.h"
5#include "hw/isa/isa.h"
6#include "hw/sysbus.h"
7#include "hw/i386/pc.h"
8#include "hw/isa/apm.h"
9#include "hw/i386/ioapic.h"
10#include "hw/pci/pci.h"
11#include "hw/pci/pcie_host.h"
12#include "hw/pci/pci_bridge.h"
13#include "hw/acpi/acpi.h"
14#include "hw/acpi/ich9.h"
15#include "hw/pci/pci_bus.h"
16
17void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
18int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
19PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
20void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled);
21I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
22
23void ich9_generate_smi(void);
24
25#define ICH9_CC_SIZE (16 * 1024)
26
27#define TYPE_ICH9_LPC_DEVICE "ICH9-LPC"
28#define ICH9_LPC_DEVICE(obj) \
29 OBJECT_CHECK(ICH9LPCState, (obj), TYPE_ICH9_LPC_DEVICE)
30
31typedef struct ICH9LPCState {
32
33 PCIDevice d;
34
35
36
37
38
39
40
41
42 uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
43
44 APMState apm;
45 ICH9LPCPMRegs pm;
46 uint32_t sci_level;
47 uint8_t sci_gsi;
48
49
50 struct {
51 bool spkr_hi;
52 } pin_strap;
53
54
55
56 uint8_t chip_config[ICH9_CC_SIZE];
57
58
59
60
61
62
63 uint8_t rst_cnt;
64 MemoryRegion rst_cnt_mem;
65
66
67 uint64_t smi_host_features;
68 uint8_t smi_host_features_le[8];
69
70 uint8_t smi_guest_features_le[8];
71
72 uint8_t smi_features_ok;
73
74 uint64_t smi_negotiated_features;
75
76
77 ISABus *isa_bus;
78 MemoryRegion rcrb_mem;
79 Notifier machine_ready;
80
81 qemu_irq gsi[GSI_NUM_PINS];
82} ICH9LPCState;
83
84Object *ich9_lpc_find(void);
85
86#define Q35_MASK(bit, ms_bit, ls_bit) \
87((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
88
89
90#define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1)
91
92#define ICH9_CC
93#define ICH9_CC_D28IP 0x310C
94#define ICH9_CC_D28IP_SHIFT 4
95#define ICH9_CC_D28IP_MASK 0xf
96#define ICH9_CC_D28IP_DEFAULT 0x00214321
97#define ICH9_CC_D31IR 0x3140
98#define ICH9_CC_D30IR 0x3142
99#define ICH9_CC_D29IR 0x3144
100#define ICH9_CC_D28IR 0x3146
101#define ICH9_CC_D27IR 0x3148
102#define ICH9_CC_D26IR 0x314C
103#define ICH9_CC_D25IR 0x3150
104#define ICH9_CC_DIR_DEFAULT 0x3210
105#define ICH9_CC_D30IR_DEFAULT 0x0
106#define ICH9_CC_DIR_SHIFT 4
107#define ICH9_CC_DIR_MASK 0x7
108#define ICH9_CC_OIC 0x31FF
109#define ICH9_CC_OIC_AEN 0x1
110#define ICH9_CC_GCS 0x3410
111#define ICH9_CC_GCS_DEFAULT 0x00000020
112#define ICH9_CC_GCS_NO_REBOOT (1 << 5)
113
114
115#define ICH9_PCIE_DEV 28
116#define ICH9_PCIE_FUNC_MAX 6
117
118
119
120#define ICH9_USB_UHCI1_DEV 29
121#define ICH9_USB_UHCI1_FUNC 0
122
123
124#define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE"
125#define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0
126
127#define ICH9_D2P_BRIDGE_DEV 30
128#define ICH9_D2P_BRIDGE_FUNC 0
129
130#define ICH9_D2P_SECONDARY_DEFAULT (256 - 8)
131
132#define ICH9_D2P_A2_REVISION 0x92
133
134
135#define ICH9_RST_CNT_IOPORT 0xCF9
136
137
138#define ICH9_A2_LPC "ICH9 A2 LPC"
139#define ICH9_A2_LPC_SAVEVM_VERSION 0
140
141#define ICH9_LPC_DEV 31
142#define ICH9_LPC_FUNC 0
143
144#define ICH9_A2_LPC_REVISION 0x2
145#define ICH9_LPC_NB_PIRQS 8
146
147#define ICH9_LPC_PMBASE 0x40
148#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK Q35_MASK(32, 15, 7)
149#define ICH9_LPC_PMBASE_RTE 0x1
150#define ICH9_LPC_PMBASE_DEFAULT 0x1
151#define ICH9_LPC_ACPI_CTRL 0x44
152#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80
153#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK Q35_MASK(8, 2, 0)
154#define ICH9_LPC_ACPI_CTRL_9 0x0
155#define ICH9_LPC_ACPI_CTRL_10 0x1
156#define ICH9_LPC_ACPI_CTRL_11 0x2
157#define ICH9_LPC_ACPI_CTRL_20 0x4
158#define ICH9_LPC_ACPI_CTRL_21 0x5
159#define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0
160
161#define ICH9_LPC_PIRQA_ROUT 0x60
162#define ICH9_LPC_PIRQB_ROUT 0x61
163#define ICH9_LPC_PIRQC_ROUT 0x62
164#define ICH9_LPC_PIRQD_ROUT 0x63
165
166#define ICH9_LPC_PIRQE_ROUT 0x68
167#define ICH9_LPC_PIRQF_ROUT 0x69
168#define ICH9_LPC_PIRQG_ROUT 0x6a
169#define ICH9_LPC_PIRQH_ROUT 0x6b
170
171#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80
172#define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0)
173#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80
174
175#define ICH9_LPC_GEN_PMCON_1 0xa0
176#define ICH9_LPC_GEN_PMCON_1_SMI_LOCK (1 << 4)
177#define ICH9_LPC_GEN_PMCON_2 0xa2
178#define ICH9_LPC_GEN_PMCON_3 0xa4
179#define ICH9_LPC_GEN_PMCON_LOCK 0xa6
180
181#define ICH9_LPC_RCBA 0xf0
182#define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14)
183#define ICH9_LPC_RCBA_EN 0x1
184#define ICH9_LPC_RCBA_DEFAULT 0x0
185
186#define ICH9_LPC_PIC_NUM_PINS 16
187#define ICH9_LPC_IOAPIC_NUM_PINS 24
188
189#define ICH9_GPIO_GSI "gsi"
190
191
192#define ICH9_SATA1_DEV 31
193#define ICH9_SATA1_FUNC 2
194
195
196
197
198
199#define ICH9_PMIO_SIZE 128
200#define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1)
201
202#define ICH9_PMIO_PM1_STS 0x00
203#define ICH9_PMIO_PM1_EN 0x02
204#define ICH9_PMIO_PM1_CNT 0x04
205#define ICH9_PMIO_PM1_TMR 0x08
206#define ICH9_PMIO_GPE0_STS 0x20
207#define ICH9_PMIO_GPE0_EN 0x28
208#define ICH9_PMIO_GPE0_LEN 16
209#define ICH9_PMIO_SMI_EN 0x30
210#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5)
211#define ICH9_PMIO_SMI_EN_TCO_EN (1 << 13)
212#define ICH9_PMIO_SMI_STS 0x34
213#define ICH9_PMIO_TCO_RLD 0x60
214#define ICH9_PMIO_TCO_LEN 32
215
216
217#define ICH9_APM_ACPI_ENABLE 0x2
218#define ICH9_APM_ACPI_DISABLE 0x3
219
220
221
222#define TYPE_ICH9_SMB_DEVICE "ICH9 SMB"
223
224#define ICH9_A2_SMB_REVISION 0x02
225#define ICH9_SMB_PI 0x00
226
227#define ICH9_SMB_SMBMBAR0 0x10
228#define ICH9_SMB_SMBMBAR1 0x14
229#define ICH9_SMB_SMBM_BAR 0
230#define ICH9_SMB_SMBM_SIZE (1 << 8)
231#define ICH9_SMB_SMB_BASE 0x20
232#define ICH9_SMB_SMB_BASE_BAR 4
233#define ICH9_SMB_SMB_BASE_SIZE (1 << 5)
234#define ICH9_SMB_HOSTC 0x40
235#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3))
236#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2))
237#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1))
238#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0))
239
240
241#define ICH9_SMB_DEV 31
242#define ICH9_SMB_FUNC 3
243
244#define ICH9_SMB_HST_STS 0x00
245#define ICH9_SMB_HST_CNT 0x02
246#define ICH9_SMB_HST_CMD 0x03
247#define ICH9_SMB_XMIT_SLVA 0x04
248#define ICH9_SMB_HST_D0 0x05
249#define ICH9_SMB_HST_D1 0x06
250#define ICH9_SMB_HOST_BLOCK_DB 0x07
251
252
253#define ICH9_LPC_SMI_F_BROADCAST_BIT 0
254
255#endif
256