LXR qemu/include/hw/pci/pcie

   1/*
   2 * constants for pcie configurations space from pci express spec.
   3 *
   4 * TODO:
   5 * Those constants and macros should go to Linux pci_regs.h
   6 * Once they're merged, they will go away.
   7 */
   8#ifndef QEMU_PCIE_REGS_H
   9#define QEMU_PCIE_REGS_H
  10
  11
  12/* express capability */
  13
  14#define PCI_EXP_VER1_SIZEOF             0x14 /* express capability of ver. 1 */
  15#define PCI_EXP_VER2_SIZEOF             0x3c /* express capability of ver. 2 */
  16#define PCI_EXT_CAP_VER_SHIFT           16
  17#define PCI_EXT_CAP_NEXT_SHIFT          20
  18#define PCI_EXT_CAP_NEXT_MASK           (0xffc << PCI_EXT_CAP_NEXT_SHIFT)
  19
  20#define PCI_EXT_CAP(id, ver, next)                                      \
  21    ((id) |                                                             \
  22     ((ver) << PCI_EXT_CAP_VER_SHIFT) |                                 \
  23     ((next) << PCI_EXT_CAP_NEXT_SHIFT))
  24
  25#define PCI_EXT_CAP_ALIGN               4
  26#define PCI_EXT_CAP_ALIGNUP(x)                                  \
  27    (((x) + PCI_EXT_CAP_ALIGN - 1) & ~(PCI_EXT_CAP_ALIGN - 1))
  28
  29/* PCI_EXP_FLAGS */
  30#define PCI_EXP_FLAGS_VER1              1
  31#define PCI_EXP_FLAGS_VER2              2
  32#define PCI_EXP_FLAGS_IRQ_SHIFT         ctz32(PCI_EXP_FLAGS_IRQ)
  33#define PCI_EXP_FLAGS_TYPE_SHIFT        ctz32(PCI_EXP_FLAGS_TYPE)
  34
  35/* PCI_EXP_LINK{CAP, STA} */
  36/* link speed */
  37#define PCI_EXP_LNK_LS_25               1
  38
  39#define PCI_EXP_LNK_MLW_SHIFT           ctz32(PCI_EXP_LNKCAP_MLW)
  40#define PCI_EXP_LNK_MLW_1               (1 << PCI_EXP_LNK_MLW_SHIFT)
  41
  42/* PCI_EXP_LINKCAP */
  43#define PCI_EXP_LNKCAP_ASPMS_SHIFT      ctz32(PCI_EXP_LNKCAP_ASPMS)
  44#define PCI_EXP_LNKCAP_ASPMS_0S         (1 << PCI_EXP_LNKCAP_ASPMS_SHIFT)
  45
  46#define PCI_EXP_LNKCAP_PN_SHIFT         ctz32(PCI_EXP_LNKCAP_PN)
  47
  48#define PCI_EXP_SLTCAP_PSN_SHIFT        ctz32(PCI_EXP_SLTCAP_PSN)
  49
  50#define PCI_EXP_SLTCTL_IND_RESERVED     0x0
  51#define PCI_EXP_SLTCTL_IND_ON           0x1
  52#define PCI_EXP_SLTCTL_IND_BLINK        0x2
  53#define PCI_EXP_SLTCTL_IND_OFF          0x3
  54#define PCI_EXP_SLTCTL_AIC_SHIFT        ctz32(PCI_EXP_SLTCTL_AIC)
  55#define PCI_EXP_SLTCTL_AIC_OFF                          \
  56    (PCI_EXP_SLTCTL_IND_OFF << PCI_EXP_SLTCTL_AIC_SHIFT)
  57
  58#define PCI_EXP_SLTCTL_PIC_SHIFT        ctz32(PCI_EXP_SLTCTL_PIC)
  59#define PCI_EXP_SLTCTL_PIC_OFF                          \
  60    (PCI_EXP_SLTCTL_IND_OFF << PCI_EXP_SLTCTL_PIC_SHIFT)
  61#define PCI_EXP_SLTCTL_PIC_ON                          \
  62    (PCI_EXP_SLTCTL_IND_ON << PCI_EXP_SLTCTL_PIC_SHIFT)
  63
  64#define PCI_EXP_SLTCTL_SUPPORTED        \
  65            (PCI_EXP_SLTCTL_ABPE |      \
  66             PCI_EXP_SLTCTL_PDCE |      \
  67             PCI_EXP_SLTCTL_CCIE |      \
  68             PCI_EXP_SLTCTL_HPIE |      \
  69             PCI_EXP_SLTCTL_AIC |       \
  70             PCI_EXP_SLTCTL_PCC |       \
  71             PCI_EXP_SLTCTL_EIC)
  72
  73#define PCI_EXP_DEVCAP2_EFF             0x100000
  74#define PCI_EXP_DEVCAP2_EETLPP          0x200000
  75
  76#define PCI_EXP_DEVCTL2_EETLPPB         0x8000
  77
  78/* ARI */
  79#define PCI_ARI_VER                     1
  80#define PCI_ARI_SIZEOF                  8
  81
  82/* AER */
  83#define PCI_ERR_VER                     2
  84#define PCI_ERR_SIZEOF                  0x48
  85
  86#define PCI_ERR_UNC_SDN                 0x00000020      /* surprise down */
  87#define PCI_ERR_UNC_ACSV                0x00200000      /* ACS Violation */
  88#define PCI_ERR_UNC_INTN                0x00400000      /* Internal Error */
  89#define PCI_ERR_UNC_MCBTLP              0x00800000      /* MC Blcoked TLP */
  90#define PCI_ERR_UNC_ATOP_EBLOCKED       0x01000000      /* atomic op egress blocked */
  91#define PCI_ERR_UNC_TLP_PRF_BLOCKED     0x02000000      /* TLP Prefix Blocked */
  92#define PCI_ERR_COR_ADV_NONFATAL        0x00002000      /* Advisory Non-Fatal */
  93#define PCI_ERR_COR_INTERNAL            0x00004000      /* Corrected Internal */
  94#define PCI_ERR_COR_HL_OVERFLOW         0x00008000      /* Header Long Overflow */
  95#define PCI_ERR_CAP_FEP_MASK            0x0000001f
  96#define PCI_ERR_CAP_MHRC                0x00000200
  97#define PCI_ERR_CAP_MHRE                0x00000400
  98#define PCI_ERR_CAP_TLP                 0x00000800
  99
 100#define PCI_ERR_HEADER_LOG_SIZE         16
 101#define PCI_ERR_TLP_PREFIX_LOG          0x38
 102#define PCI_ERR_TLP_PREFIX_LOG_SIZE     16
 103
 104#define PCI_SEC_STATUS_RCV_SYSTEM_ERROR         0x4000
 105
 106/* aer root error command/status */
 107#define PCI_ERR_ROOT_CMD_EN_MASK        (PCI_ERR_ROOT_CMD_COR_EN |      \
 108                                         PCI_ERR_ROOT_CMD_NONFATAL_EN | \
 109                                         PCI_ERR_ROOT_CMD_FATAL_EN)
 110
 111#define PCI_ERR_ROOT_IRQ_MAX            32
 112#define PCI_ERR_ROOT_IRQ                0xf8000000
 113#define PCI_ERR_ROOT_IRQ_SHIFT          ctz32(PCI_ERR_ROOT_IRQ)
 114#define PCI_ERR_ROOT_STATUS_REPORT_MASK (PCI_ERR_ROOT_COR_RCV |         \
 115                                         PCI_ERR_ROOT_MULTI_COR_RCV |   \
 116                                         PCI_ERR_ROOT_UNCOR_RCV |       \
 117                                         PCI_ERR_ROOT_MULTI_UNCOR_RCV | \
 118                                         PCI_ERR_ROOT_FIRST_FATAL |     \
 119                                         PCI_ERR_ROOT_NONFATAL_RCV |    \
 120                                         PCI_ERR_ROOT_FATAL_RCV)
 121
 122#define PCI_ERR_UNC_SUPPORTED           (PCI_ERR_UNC_DLP |              \
 123                                         PCI_ERR_UNC_SDN |              \
 124                                         PCI_ERR_UNC_POISON_TLP |       \
 125                                         PCI_ERR_UNC_FCP |              \
 126                                         PCI_ERR_UNC_COMP_TIME |        \
 127                                         PCI_ERR_UNC_COMP_ABORT |       \
 128                                         PCI_ERR_UNC_UNX_COMP |         \
 129                                         PCI_ERR_UNC_RX_OVER |          \
 130                                         PCI_ERR_UNC_MALF_TLP |         \
 131                                         PCI_ERR_UNC_ECRC |             \
 132                                         PCI_ERR_UNC_UNSUP |            \
 133                                         PCI_ERR_UNC_ACSV |             \
 134                                         PCI_ERR_UNC_INTN |             \
 135                                         PCI_ERR_UNC_MCBTLP |           \
 136                                         PCI_ERR_UNC_ATOP_EBLOCKED |    \
 137                                         PCI_ERR_UNC_TLP_PRF_BLOCKED)
 138
 139#define PCI_ERR_UNC_SEVERITY_DEFAULT    (PCI_ERR_UNC_DLP |              \
 140                                         PCI_ERR_UNC_SDN |              \
 141                                         PCI_ERR_UNC_FCP |              \
 142                                         PCI_ERR_UNC_RX_OVER |          \
 143                                         PCI_ERR_UNC_MALF_TLP |         \
 144                                         PCI_ERR_UNC_INTN)
 145
 146#define PCI_ERR_COR_SUPPORTED           (PCI_ERR_COR_RCVR |             \
 147                                         PCI_ERR_COR_BAD_TLP |          \
 148                                         PCI_ERR_COR_BAD_DLLP |         \
 149                                         PCI_ERR_COR_REP_ROLL |         \
 150                                         PCI_ERR_COR_REP_TIMER |        \
 151                                         PCI_ERR_COR_ADV_NONFATAL |     \
 152                                         PCI_ERR_COR_INTERNAL |         \
 153                                         PCI_ERR_COR_HL_OVERFLOW)
 154
 155#define PCI_ERR_COR_MASK_DEFAULT        (PCI_ERR_COR_ADV_NONFATAL |     \
 156                                         PCI_ERR_COR_INTERNAL |         \
 157                                         PCI_ERR_COR_HL_OVERFLOW)
 158
 159#endif /* QEMU_PCIE_REGS_H */
 160