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19#ifndef _PPC_PNV_H
20#define _PPC_PNV_H
21
22#include "hw/boards.h"
23#include "hw/sysbus.h"
24#include "hw/ipmi/ipmi.h"
25#include "hw/ppc/pnv_lpc.h"
26#include "hw/ppc/pnv_psi.h"
27#include "hw/ppc/pnv_occ.h"
28
29#define TYPE_PNV_CHIP "pnv-chip"
30#define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
31#define PNV_CHIP_CLASS(klass) \
32 OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP)
33#define PNV_CHIP_GET_CLASS(obj) \
34 OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP)
35
36typedef enum PnvChipType {
37 PNV_CHIP_POWER8E,
38 PNV_CHIP_POWER8,
39 PNV_CHIP_POWER8NVL,
40 PNV_CHIP_POWER9,
41} PnvChipType;
42
43typedef struct PnvChip {
44
45 SysBusDevice parent_obj;
46
47
48 uint32_t chip_id;
49 uint64_t ram_start;
50 uint64_t ram_size;
51
52 uint32_t nr_cores;
53 uint64_t cores_mask;
54 void *cores;
55
56 hwaddr xscom_base;
57 MemoryRegion xscom_mmio;
58 MemoryRegion xscom;
59 AddressSpace xscom_as;
60} PnvChip;
61
62#define TYPE_PNV8_CHIP "pnv8-chip"
63#define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP)
64
65typedef struct Pnv8Chip {
66
67 PnvChip parent_obj;
68
69
70 MemoryRegion icp_mmio;
71
72 PnvLpcController lpc;
73 PnvPsi psi;
74 PnvOCC occ;
75} Pnv8Chip;
76
77#define TYPE_PNV9_CHIP "pnv9-chip"
78#define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP)
79
80typedef struct Pnv9Chip {
81
82 PnvChip parent_obj;
83
84
85} Pnv9Chip;
86
87typedef struct PnvChipClass {
88
89 SysBusDeviceClass parent_class;
90
91
92 PnvChipType chip_type;
93 uint64_t chip_cfam_id;
94 uint64_t cores_mask;
95
96 hwaddr xscom_base;
97
98 DeviceRealize parent_realize;
99
100 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
101 Object *(*intc_create)(PnvChip *chip, Object *child, Error **errp);
102 ISABus *(*isa_create)(PnvChip *chip, Error **errp);
103} PnvChipClass;
104
105#define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
106#define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
107
108#define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1")
109#define PNV_CHIP_POWER8E(obj) \
110 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E)
111
112#define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0")
113#define PNV_CHIP_POWER8(obj) \
114 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8)
115
116#define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0")
117#define PNV_CHIP_POWER8NVL(obj) \
118 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL)
119
120#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0")
121#define PNV_CHIP_POWER9(obj) \
122 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9)
123
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133
134#define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1))
135
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139
140#define PNV_CHIP_INDEX(chip) \
141 (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3))
142
143#define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
144#define PNV_MACHINE(obj) \
145 OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE)
146
147typedef struct PnvMachineState {
148
149 MachineState parent_obj;
150
151 uint32_t initrd_base;
152 long initrd_size;
153
154 uint32_t num_chips;
155 PnvChip **chips;
156
157 ISABus *isa_bus;
158 uint32_t cpld_irqstate;
159
160 IPMIBmc *bmc;
161 Notifier powerdown_notifier;
162} PnvMachineState;
163
164static inline bool pnv_chip_is_power9(const PnvChip *chip)
165{
166 return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER9;
167}
168
169static inline bool pnv_is_power9(PnvMachineState *pnv)
170{
171 return pnv_chip_is_power9(pnv->chips[0]);
172}
173
174#define PNV_FDT_ADDR 0x01000000
175#define PNV_TIMEBASE_FREQ 512000000ULL
176
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179
180void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt);
181void pnv_bmc_powerdown(IPMIBmc *bmc);
182
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185
186#define PNV_XSCOM_SIZE 0x800000000ull
187#define PNV_XSCOM_BASE(chip) \
188 (chip->xscom_base + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
189
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204#define PNV_ICP_SIZE 0x0000000000100000ull
205#define PNV_ICP_BASE(chip) \
206 (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE)
207
208
209#define PNV_PSIHB_SIZE 0x0000000000100000ull
210#define PNV_PSIHB_BASE(chip) \
211 (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE)
212
213#define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull
214#define PNV_PSIHB_FSP_BASE(chip) \
215 (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \
216 PNV_PSIHB_FSP_SIZE)
217
218#endif
219