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21#ifndef HW_SIFIVE_PLIC_H
22#define HW_SIFIVE_PLIC_H
23
24#include "hw/irq.h"
25
26#define TYPE_SIFIVE_PLIC "riscv.sifive.plic"
27
28#define SIFIVE_PLIC(obj) \
29 OBJECT_CHECK(SiFivePLICState, (obj), TYPE_SIFIVE_PLIC)
30
31typedef enum PLICMode {
32 PLICMode_U,
33 PLICMode_S,
34 PLICMode_H,
35 PLICMode_M
36} PLICMode;
37
38typedef struct PLICAddr {
39 uint32_t addrid;
40 uint32_t hartid;
41 PLICMode mode;
42} PLICAddr;
43
44typedef struct SiFivePLICState {
45
46 SysBusDevice parent_obj;
47
48
49 MemoryRegion mmio;
50 uint32_t num_addrs;
51 uint32_t bitfield_words;
52 PLICAddr *addr_config;
53 uint32_t *source_priority;
54 uint32_t *target_priority;
55 uint32_t *pending;
56 uint32_t *claimed;
57 uint32_t *enable;
58
59
60 char *hart_config;
61 uint32_t num_sources;
62 uint32_t num_priorities;
63 uint32_t priority_base;
64 uint32_t pending_base;
65 uint32_t enable_base;
66 uint32_t enable_stride;
67 uint32_t context_base;
68 uint32_t context_stride;
69 uint32_t aperture_size;
70} SiFivePLICState;
71
72void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq);
73void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq);
74
75DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
76 uint32_t num_sources, uint32_t num_priorities,
77 uint32_t priority_base, uint32_t pending_base,
78 uint32_t enable_base, uint32_t enable_stride,
79 uint32_t context_base, uint32_t context_stride,
80 uint32_t aperture_size);
81
82#endif
83
84