1/* RISC-V ISA constants */ 2 3#define get_field(reg, mask) (((reg) & \ 4 (target_ulong)(mask)) / ((mask) & ~((mask) << 1))) 5#define set_field(reg, mask, val) (((reg) & ~(target_ulong)(mask)) | \ 6 (((target_ulong)(val) * ((mask) & ~((mask) << 1))) & \ 7 (target_ulong)(mask))) 8 9/* Floating point round mode */ 10#define FSR_RD_SHIFT 5 11#define FSR_RD (0x7 << FSR_RD_SHIFT) 12 13/* Floating point accrued exception flags */ 14#define FPEXC_NX 0x01 15#define FPEXC_UF 0x02 16#define FPEXC_OF 0x04 17#define FPEXC_DZ 0x08 18#define FPEXC_NV 0x10 19 20/* Floating point status register bits */ 21#define FSR_AEXC_SHIFT 0 22#define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT) 23#define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT) 24#define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT) 25#define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) 26#define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT) 27#define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) 28 29/* Control and Status Registers */ 30 31/* User Trap Setup */ 32#define CSR_USTATUS 0x000 33#define CSR_UIE 0x004 34#define CSR_UTVEC 0x005 35 36/* User Trap Handling */ 37#define CSR_USCRATCH 0x040 38#define CSR_UEPC 0x041 39#define CSR_UCAUSE 0x042 40#define CSR_UTVAL 0x043 41#define CSR_UIP 0x044 42 43/* User Floating-Point CSRs */ 44#define CSR_FFLAGS 0x001 45#define CSR_FRM 0x002 46#define CSR_FCSR 0x003 47 48/* User Timers and Counters */ 49#define CSR_CYCLE 0xc00 50#define CSR_TIME 0xc01 51#define CSR_INSTRET 0xc02 52#define CSR_HPMCOUNTER3 0xc03 53#define CSR_HPMCOUNTER4 0xc04 54#define CSR_HPMCOUNTER5 0xc05 55#define CSR_HPMCOUNTER6 0xc06 56#define CSR_HPMCOUNTER7 0xc07 57#define CSR_HPMCOUNTER8 0xc08 58#define CSR_HPMCOUNTER9 0xc09 59#define CSR_HPMCOUNTER10 0xc0a 60#define CSR_HPMCOUNTER11 0xc0b 61#define CSR_HPMCOUNTER12 0xc0c 62#define CSR_HPMCOUNTER13 0xc0d 63#define CSR_HPMCOUNTER14 0xc0e 64#define CSR_HPMCOUNTER15 0xc0f 65#define CSR_HPMCOUNTER16 0xc10 66#define CSR_HPMCOUNTER17 0xc11 67#define CSR_HPMCOUNTER18 0xc12 68#define CSR_HPMCOUNTER19 0xc13 69#define CSR_HPMCOUNTER20 0xc14 70#define CSR_HPMCOUNTER21 0xc15 71#define CSR_HPMCOUNTER22 0xc16 72#define CSR_HPMCOUNTER23 0xc17 73#define CSR_HPMCOUNTER24 0xc18 74#define CSR_HPMCOUNTER25 0xc19 75#define CSR_HPMCOUNTER26 0xc1a 76#define CSR_HPMCOUNTER27 0xc1b 77#define CSR_HPMCOUNTER28 0xc1c 78#define CSR_HPMCOUNTER29 0xc1d 79#define CSR_HPMCOUNTER30 0xc1e 80#define CSR_HPMCOUNTER31 0xc1f 81#define CSR_CYCLEH 0xc80 82#define CSR_TIMEH 0xc81 83#define CSR_INSTRETH 0xc82 84#define CSR_HPMCOUNTER3H 0xc83 85#define CSR_HPMCOUNTER4H 0xc84 86#define CSR_HPMCOUNTER5H 0xc85 87#define CSR_HPMCOUNTER6H 0xc86 88#define CSR_HPMCOUNTER7H 0xc87 89#define CSR_HPMCOUNTER8H 0xc88 90#define CSR_HPMCOUNTER9H 0xc89 91#define CSR_HPMCOUNTER10H 0xc8a 92#define CSR_HPMCOUNTER11H 0xc8b 93#define CSR_HPMCOUNTER12H 0xc8c 94#define CSR_HPMCOUNTER13H 0xc8d 95#define CSR_HPMCOUNTER14H 0xc8e 96#define CSR_HPMCOUNTER15H 0xc8f 97#define CSR_HPMCOUNTER16H 0xc90 98#define CSR_HPMCOUNTER17H 0xc91 99#define CSR_HPMCOUNTER18H 0xc92 100#define CSR_HPMCOUNTER19H 0xc93 101#define CSR_HPMCOUNTER20H 0xc94 102#define CSR_HPMCOUNTER21H 0xc95 103#define CSR_HPMCOUNTER22H 0xc96 104#define CSR_HPMCOUNTER23H 0xc97 105#define CSR_HPMCOUNTER24H 0xc98 106#define CSR_HPMCOUNTER25H 0xc99 107#define CSR_HPMCOUNTER26H 0xc9a 108#define CSR_HPMCOUNTER27H 0xc9b 109#define CSR_HPMCOUNTER28H 0xc9c 110#define CSR_HPMCOUNTER29H 0xc9d 111#define CSR_HPMCOUNTER30H 0xc9e 112#define CSR_HPMCOUNTER31H 0xc9f 113 114/* Machine Timers and Counters */ 115#define CSR_MCYCLE 0xb00 116#define CSR_MINSTRET 0xb02 117#define CSR_MCYCLEH 0xb80 118#define CSR_MINSTRETH 0xb82 119 120/* Machine Information Registers */ 121#define CSR_MVENDORID 0xf11 122#define CSR_MARCHID 0xf12 123#define CSR_MIMPID 0xf13 124#define CSR_MHARTID 0xf14 125 126/* Machine Trap Setup */ 127#define CSR_MSTATUS 0x300 128#define CSR_MISA 0x301 129#define CSR_MEDELEG 0x302 130#define CSR_MIDELEG 0x303 131#define CSR_MIE 0x304 132#define CSR_MTVEC 0x305 133#define CSR_MCOUNTEREN 0x306 134 135/* Legacy Counter Setup (priv v1.9.1) */ 136#define CSR_MUCOUNTEREN 0x320 137#define CSR_MSCOUNTEREN 0x321 138 139/* Machine Trap Handling */ 140#define CSR_MSCRATCH 0x340 141#define CSR_MEPC 0x341 142#define CSR_MCAUSE 0x342 143#define CSR_MBADADDR 0x343 144#define CSR_MIP 0x344 145 146/* Supervisor Trap Setup */ 147#define CSR_SSTATUS 0x100 148#define CSR_SIE 0x104 149#define CSR_STVEC 0x105 150#define CSR_SCOUNTEREN 0x106 151 152/* Supervisor Trap Handling */ 153#define CSR_SSCRATCH 0x140 154#define CSR_SEPC 0x141 155#define CSR_SCAUSE 0x142 156#define CSR_SBADADDR 0x143 157#define CSR_SIP 0x144 158 159/* Supervisor Protection and Translation */ 160#define CSR_SPTBR 0x180 161#define CSR_SATP 0x180 162 163/* Physical Memory Protection */ 164#define CSR_PMPCFG0 0x3a0 165#define CSR_PMPCFG1 0x3a1 166#define CSR_PMPCFG2 0x3a2 167#define CSR_PMPCFG3 0x3a3 168#define CSR_PMPADDR0 0x3b0 169#define CSR_PMPADDR1 0x3b1 170#define CSR_PMPADDR2 0x3b2 171#define CSR_PMPADDR3 0x3b3 172#define CSR_PMPADDR4 0x3b4 173#define CSR_PMPADDR5 0x3b5 174#define CSR_PMPADDR6 0x3b6 175#define CSR_PMPADDR7 0x3b7 176#define CSR_PMPADDR8 0x3b8 177#define CSR_PMPADDR9 0x3b9 178#define CSR_PMPADDR10 0x3ba 179#define CSR_PMPADDR11 0x3bb 180#define CSR_PMPADDR12 0x3bc 181#define CSR_PMPADDR13 0x3bd 182#define CSR_PMPADDR14 0x3be 183#define CSR_PMPADDR15 0x3bf 184 185/* Debug/Trace Registers (shared with Debug Mode) */ 186#define CSR_TSELECT 0x7a0 187#define CSR_TDATA1 0x7a1 188#define CSR_TDATA2 0x7a2 189#define CSR_TDATA3 0x7a3 190 191/* Debug Mode Registers */ 192#define CSR_DCSR 0x7b0 193#define CSR_DPC 0x7b1 194#define CSR_DSCRATCH 0x7b2 195 196/* Performance Counters */ 197#define CSR_MHPMCOUNTER3 0xb03 198#define CSR_MHPMCOUNTER4 0xb04 199#define CSR_MHPMCOUNTER5 0xb05 200#define CSR_MHPMCOUNTER6 0xb06 201#define CSR_MHPMCOUNTER7 0xb07 202#define CSR_MHPMCOUNTER8 0xb08 203#define CSR_MHPMCOUNTER9 0xb09 204#define CSR_MHPMCOUNTER10 0xb0a 205#define CSR_MHPMCOUNTER11 0xb0b 206#define CSR_MHPMCOUNTER12 0xb0c 207#define CSR_MHPMCOUNTER13 0xb0d 208#define CSR_MHPMCOUNTER14 0xb0e 209#define CSR_MHPMCOUNTER15 0xb0f 210#define CSR_MHPMCOUNTER16 0xb10 211#define CSR_MHPMCOUNTER17 0xb11 212#define CSR_MHPMCOUNTER18 0xb12 213#define CSR_MHPMCOUNTER19 0xb13 214#define CSR_MHPMCOUNTER20 0xb14 215#define CSR_MHPMCOUNTER21 0xb15 216#define CSR_MHPMCOUNTER22 0xb16 217#define CSR_MHPMCOUNTER23 0xb17 218#define CSR_MHPMCOUNTER24 0xb18 219#define CSR_MHPMCOUNTER25 0xb19 220#define CSR_MHPMCOUNTER26 0xb1a 221#define CSR_MHPMCOUNTER27 0xb1b 222#define CSR_MHPMCOUNTER28 0xb1c 223#define CSR_MHPMCOUNTER29 0xb1d 224#define CSR_MHPMCOUNTER30 0xb1e 225#define CSR_MHPMCOUNTER31 0xb1f 226#define CSR_MHPMEVENT3 0x323 227#define CSR_MHPMEVENT4 0x324 228#define CSR_MHPMEVENT5 0x325 229#define CSR_MHPMEVENT6 0x326 230#define CSR_MHPMEVENT7 0x327 231#define CSR_MHPMEVENT8 0x328 232#define CSR_MHPMEVENT9 0x329 233#define CSR_MHPMEVENT10 0x32a 234#define CSR_MHPMEVENT11 0x32b 235#define CSR_MHPMEVENT12 0x32c 236#define CSR_MHPMEVENT13 0x32d 237#define CSR_MHPMEVENT14 0x32e 238#define CSR_MHPMEVENT15 0x32f 239#define CSR_MHPMEVENT16 0x330 240#define CSR_MHPMEVENT17 0x331 241#define CSR_MHPMEVENT18 0x332 242#define CSR_MHPMEVENT19 0x333 243#define CSR_MHPMEVENT20 0x334 244#define CSR_MHPMEVENT21 0x335 245#define CSR_MHPMEVENT22 0x336 246#define CSR_MHPMEVENT23 0x337 247#define CSR_MHPMEVENT24 0x338 248#define CSR_MHPMEVENT25 0x339 249#define CSR_MHPMEVENT26 0x33a 250#define CSR_MHPMEVENT27 0x33b 251#define CSR_MHPMEVENT28 0x33c 252#define CSR_MHPMEVENT29 0x33d 253#define CSR_MHPMEVENT30 0x33e 254#define CSR_MHPMEVENT31 0x33f 255#define CSR_MHPMCOUNTER3H 0xb83 256#define CSR_MHPMCOUNTER4H 0xb84 257#define CSR_MHPMCOUNTER5H 0xb85 258#define CSR_MHPMCOUNTER6H 0xb86 259#define CSR_MHPMCOUNTER7H 0xb87 260#define CSR_MHPMCOUNTER8H 0xb88 261#define CSR_MHPMCOUNTER9H 0xb89 262#define CSR_MHPMCOUNTER10H 0xb8a 263#define CSR_MHPMCOUNTER11H 0xb8b 264#define CSR_MHPMCOUNTER12H 0xb8c 265#define CSR_MHPMCOUNTER13H 0xb8d 266#define CSR_MHPMCOUNTER14H 0xb8e 267#define CSR_MHPMCOUNTER15H 0xb8f 268#define CSR_MHPMCOUNTER16H 0xb90 269#define CSR_MHPMCOUNTER17H 0xb91 270#define CSR_MHPMCOUNTER18H 0xb92 271#define CSR_MHPMCOUNTER19H 0xb93 272#define CSR_MHPMCOUNTER20H 0xb94 273#define CSR_MHPMCOUNTER21H 0xb95 274#define CSR_MHPMCOUNTER22H 0xb96 275#define CSR_MHPMCOUNTER23H 0xb97 276#define CSR_MHPMCOUNTER24H 0xb98 277#define CSR_MHPMCOUNTER25H 0xb99 278#define CSR_MHPMCOUNTER26H 0xb9a 279#define CSR_MHPMCOUNTER27H 0xb9b 280#define CSR_MHPMCOUNTER28H 0xb9c 281#define CSR_MHPMCOUNTER29H 0xb9d 282#define CSR_MHPMCOUNTER30H 0xb9e 283#define CSR_MHPMCOUNTER31H 0xb9f 284 285/* mstatus CSR bits */ 286#define MSTATUS_UIE 0x00000001 287#define MSTATUS_SIE 0x00000002 288#define MSTATUS_HIE 0x00000004 289#define MSTATUS_MIE 0x00000008 290#define MSTATUS_UPIE 0x00000010 291#define MSTATUS_SPIE 0x00000020 292#define MSTATUS_HPIE 0x00000040 293#define MSTATUS_MPIE 0x00000080 294#define MSTATUS_SPP 0x00000100 295#define MSTATUS_HPP 0x00000600 296#define MSTATUS_MPP 0x00001800 297#define MSTATUS_FS 0x00006000 298#define MSTATUS_XS 0x00018000 299#define MSTATUS_MPRV 0x00020000 300#define MSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */ 301#define MSTATUS_SUM 0x00040000 /* since: priv-1.10 */ 302#define MSTATUS_MXR 0x00080000 303#define MSTATUS_VM 0x1F000000 /* until: priv-1.9.1 */ 304#define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ 305#define MSTATUS_TW 0x20000000 /* since: priv-1.10 */ 306#define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */ 307 308#define MSTATUS64_UXL 0x0000000300000000ULL 309#define MSTATUS64_SXL 0x0000000C00000000ULL 310 311#define MSTATUS32_SD 0x80000000 312#define MSTATUS64_SD 0x8000000000000000ULL 313 314#if defined(TARGET_RISCV32) 315#define MSTATUS_SD MSTATUS32_SD 316#elif defined(TARGET_RISCV64) 317#define MSTATUS_SD MSTATUS64_SD 318#endif 319 320/* sstatus CSR bits */ 321#define SSTATUS_UIE 0x00000001 322#define SSTATUS_SIE 0x00000002 323#define SSTATUS_UPIE 0x00000010 324#define SSTATUS_SPIE 0x00000020 325#define SSTATUS_SPP 0x00000100 326#define SSTATUS_FS 0x00006000 327#define SSTATUS_XS 0x00018000 328#define SSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */ 329#define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */ 330#define SSTATUS_MXR 0x00080000 331 332#define SSTATUS32_SD 0x80000000 333#define SSTATUS64_SD 0x8000000000000000ULL 334 335#if defined(TARGET_RISCV32) 336#define SSTATUS_SD SSTATUS32_SD 337#elif defined(TARGET_RISCV64) 338#define SSTATUS_SD SSTATUS64_SD 339#endif 340 341/* Privilege modes */ 342#define PRV_U 0 343#define PRV_S 1 344#define PRV_H 2 345#define PRV_M 3 346 347/* RV32 satp CSR field masks */ 348#define SATP32_MODE 0x80000000 349#define SATP32_ASID 0x7fc00000 350#define SATP32_PPN 0x003fffff 351 352/* RV64 satp CSR field masks */ 353#define SATP64_MODE 0xF000000000000000ULL 354#define SATP64_ASID 0x0FFFF00000000000ULL 355#define SATP64_PPN 0x00000FFFFFFFFFFFULL 356 357#if defined(TARGET_RISCV32) 358#define SATP_MODE SATP32_MODE 359#define SATP_ASID SATP32_ASID 360#define SATP_PPN SATP32_PPN 361#endif 362#if defined(TARGET_RISCV64) 363#define SATP_MODE SATP64_MODE 364#define SATP_ASID SATP64_ASID 365#define SATP_PPN SATP64_PPN 366#endif 367 368/* VM modes (mstatus.vm) privileged ISA 1.9.1 */ 369#define VM_1_09_MBARE 0 370#define VM_1_09_MBB 1 371#define VM_1_09_MBBID 2 372#define VM_1_09_SV32 8 373#define VM_1_09_SV39 9 374#define VM_1_09_SV48 10 375 376/* VM modes (satp.mode) privileged ISA 1.10 */ 377#define VM_1_10_MBARE 0 378#define VM_1_10_SV32 1 379#define VM_1_10_SV39 8 380#define VM_1_10_SV48 9 381#define VM_1_10_SV57 10 382#define VM_1_10_SV64 11 383 384/* Page table entry (PTE) fields */ 385#define PTE_V 0x001 /* Valid */ 386#define PTE_R 0x002 /* Read */ 387#define PTE_W 0x004 /* Write */ 388#define PTE_X 0x008 /* Execute */ 389#define PTE_U 0x010 /* User */ 390#define PTE_G 0x020 /* Global */ 391#define PTE_A 0x040 /* Accessed */ 392#define PTE_D 0x080 /* Dirty */ 393#define PTE_SOFT 0x300 /* Reserved for Software */ 394 395/* Page table PPN shift amount */ 396#define PTE_PPN_SHIFT 10 397 398/* Leaf page shift amount */ 399#define PGSHIFT 12 400 401/* Default Reset Vector adress */ 402#define DEFAULT_RSTVEC 0x1000 403 404/* Exception causes */ 405#define EXCP_NONE -1 /* sentinel value */ 406#define RISCV_EXCP_INST_ADDR_MIS 0x0 407#define RISCV_EXCP_INST_ACCESS_FAULT 0x1 408#define RISCV_EXCP_ILLEGAL_INST 0x2 409#define RISCV_EXCP_BREAKPOINT 0x3 410#define RISCV_EXCP_LOAD_ADDR_MIS 0x4 411#define RISCV_EXCP_LOAD_ACCESS_FAULT 0x5 412#define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6 413#define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7 414#define RISCV_EXCP_U_ECALL 0x8 415#define RISCV_EXCP_S_ECALL 0x9 416#define RISCV_EXCP_H_ECALL 0xa 417#define RISCV_EXCP_M_ECALL 0xb 418#define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0 */ 419#define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0 */ 420#define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0 */ 421 422#define RISCV_EXCP_INT_FLAG 0x80000000 423#define RISCV_EXCP_INT_MASK 0x7fffffff 424 425/* Interrupt causes */ 426#define IRQ_U_SOFT 0 427#define IRQ_S_SOFT 1 428#define IRQ_H_SOFT 2 /* reserved */ 429#define IRQ_M_SOFT 3 430#define IRQ_U_TIMER 4 431#define IRQ_S_TIMER 5 432#define IRQ_H_TIMER 6 /* reserved */ 433#define IRQ_M_TIMER 7 434#define IRQ_U_EXT 8 435#define IRQ_S_EXT 9 436#define IRQ_H_EXT 10 /* reserved */ 437#define IRQ_M_EXT 11 438 439/* mip masks */ 440#define MIP_USIP (1 << IRQ_U_SOFT) 441#define MIP_SSIP (1 << IRQ_S_SOFT) 442#define MIP_HSIP (1 << IRQ_H_SOFT) 443#define MIP_MSIP (1 << IRQ_M_SOFT) 444#define MIP_UTIP (1 << IRQ_U_TIMER) 445#define MIP_STIP (1 << IRQ_S_TIMER) 446#define MIP_HTIP (1 << IRQ_H_TIMER) 447#define MIP_MTIP (1 << IRQ_M_TIMER) 448#define MIP_UEIP (1 << IRQ_U_EXT) 449#define MIP_SEIP (1 << IRQ_S_EXT) 450#define MIP_HEIP (1 << IRQ_H_EXT) 451#define MIP_MEIP (1 << IRQ_M_EXT) 452 453/* sip masks */ 454#define SIP_SSIP MIP_SSIP 455#define SIP_STIP MIP_STIP 456#define SIP_SEIP MIP_SEIP 457