LXR qemu/tcg/tcg-opc.h

   1/*
   2 * Tiny Code Generator for QEMU
   3 *
   4 * Copyright (c) 2008 Fabrice Bellard
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25/*
  26 * DEF(name, oargs, iargs, cargs, flags)
  27 */
  28
  29/* predefined ops */
  30DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT)
  31DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
  32
  33/* variable number of parameters */
  34DEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER | TCG_OPF_NOT_PRESENT)
  35
  36DEF(br, 0, 0, 1, TCG_OPF_BB_END)
  37
  38#define IMPL(X) (__builtin_constant_p(X) && !(X) ? TCG_OPF_NOT_PRESENT : 0)
  39#if TCG_TARGET_REG_BITS == 32
  40# define IMPL64  TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT
  41#else
  42# define IMPL64  TCG_OPF_64BIT
  43#endif
  44
  45DEF(mb, 0, 0, 1, 0)
  46
  47DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT)
  48DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT)
  49DEF(setcond_i32, 1, 2, 1, 0)
  50DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32))
  51/* load/store */
  52DEF(ld8u_i32, 1, 1, 1, 0)
  53DEF(ld8s_i32, 1, 1, 1, 0)
  54DEF(ld16u_i32, 1, 1, 1, 0)
  55DEF(ld16s_i32, 1, 1, 1, 0)
  56DEF(ld_i32, 1, 1, 1, 0)
  57DEF(st8_i32, 0, 2, 1, 0)
  58DEF(st16_i32, 0, 2, 1, 0)
  59DEF(st_i32, 0, 2, 1, 0)
  60/* arith */
  61DEF(add_i32, 1, 2, 0, 0)
  62DEF(sub_i32, 1, 2, 0, 0)
  63DEF(mul_i32, 1, 2, 0, 0)
  64DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
  65DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
  66DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
  67DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
  68DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
  69DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
  70DEF(and_i32, 1, 2, 0, 0)
  71DEF(or_i32, 1, 2, 0, 0)
  72DEF(xor_i32, 1, 2, 0, 0)
  73/* shifts/rotates */
  74DEF(shl_i32, 1, 2, 0, 0)
  75DEF(shr_i32, 1, 2, 0, 0)
  76DEF(sar_i32, 1, 2, 0, 0)
  77DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
  78DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
  79DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
  80DEF(extract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_extract_i32))
  81DEF(sextract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_sextract_i32))
  82
  83DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)
  84
  85DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32))
  86DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32))
  87DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32))
  88DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32))
  89DEF(muluh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i32))
  90DEF(mulsh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i32))
  91DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | IMPL(TCG_TARGET_REG_BITS == 32))
  92DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32))
  93
  94DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32))
  95DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32))
  96DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32))
  97DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32))
  98DEF(bswap16_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap16_i32))
  99DEF(bswap32_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap32_i32))
 100DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32))
 101DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32))
 102DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32))
 103DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32))
 104DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32))
 105DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32))
 106DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32))
 107DEF(clz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_clz_i32))
 108DEF(ctz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_ctz_i32))
 109DEF(ctpop_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ctpop_i32))
 110
 111DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
 112DEF(movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
 113DEF(setcond_i64, 1, 2, 1, IMPL64)
 114DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64))
 115/* load/store */
 116DEF(ld8u_i64, 1, 1, 1, IMPL64)
 117DEF(ld8s_i64, 1, 1, 1, IMPL64)
 118DEF(ld16u_i64, 1, 1, 1, IMPL64)
 119DEF(ld16s_i64, 1, 1, 1, IMPL64)
 120DEF(ld32u_i64, 1, 1, 1, IMPL64)
 121DEF(ld32s_i64, 1, 1, 1, IMPL64)
 122DEF(ld_i64, 1, 1, 1, IMPL64)
 123DEF(st8_i64, 0, 2, 1, IMPL64)
 124DEF(st16_i64, 0, 2, 1, IMPL64)
 125DEF(st32_i64, 0, 2, 1, IMPL64)
 126DEF(st_i64, 0, 2, 1, IMPL64)
 127/* arith */
 128DEF(add_i64, 1, 2, 0, IMPL64)
 129DEF(sub_i64, 1, 2, 0, IMPL64)
 130DEF(mul_i64, 1, 2, 0, IMPL64)
 131DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
 132DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
 133DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
 134DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
 135DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
 136DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
 137DEF(and_i64, 1, 2, 0, IMPL64)
 138DEF(or_i64, 1, 2, 0, IMPL64)
 139DEF(xor_i64, 1, 2, 0, IMPL64)
 140/* shifts/rotates */
 141DEF(shl_i64, 1, 2, 0, IMPL64)
 142DEF(shr_i64, 1, 2, 0, IMPL64)
 143DEF(sar_i64, 1, 2, 0, IMPL64)
 144DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
 145DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
 146DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
 147DEF(extract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_extract_i64))
 148DEF(sextract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_sextract_i64))
 149
 150/* size changing ops */
 151DEF(ext_i32_i64, 1, 1, 0, IMPL64)
 152DEF(extu_i32_i64, 1, 1, 0, IMPL64)
 153DEF(extrl_i64_i32, 1, 1, 0,
 154    IMPL(TCG_TARGET_HAS_extrl_i64_i32)
 155    | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
 156DEF(extrh_i64_i32, 1, 1, 0,
 157    IMPL(TCG_TARGET_HAS_extrh_i64_i32)
 158    | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
 159
 160DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | IMPL64)
 161DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64))
 162DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64))
 163DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64))
 164DEF(ext8u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8u_i64))
 165DEF(ext16u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16u_i64))
 166DEF(ext32u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32u_i64))
 167DEF(bswap16_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64))
 168DEF(bswap32_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64))
 169DEF(bswap64_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64))
 170DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64))
 171DEF(neg_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_neg_i64))
 172DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64))
 173DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc_i64))
 174DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64))
 175DEF(nand_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nand_i64))
 176DEF(nor_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nor_i64))
 177DEF(clz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_clz_i64))
 178DEF(ctz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctz_i64))
 179DEF(ctpop_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctpop_i64))
 180
 181DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64))
 182DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64))
 183DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64))
 184DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64))
 185DEF(muluh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muluh_i64))
 186DEF(mulsh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulsh_i64))
 187
 188#define TLADDR_ARGS  (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2)
 189#define DATA64_ARGS  (TCG_TARGET_REG_BITS == 64 ? 1 : 2)
 190
 191/* QEMU specific */
 192DEF(insn_start, 0, 0, TLADDR_ARGS * TARGET_INSN_START_WORDS,
 193    TCG_OPF_NOT_PRESENT)
 194DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END)
 195DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END)
 196DEF(goto_ptr, 0, 1, 0, TCG_OPF_BB_END | IMPL(TCG_TARGET_HAS_goto_ptr))
 197
 198DEF(qemu_ld_i32, 1, TLADDR_ARGS, 1,
 199    TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 200DEF(qemu_st_i32, 0, TLADDR_ARGS + 1, 1,
 201    TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 202DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 1,
 203    TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
 204DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1,
 205    TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
 206
 207/* Host vector support.  */
 208
 209#define IMPLVEC  TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec)
 210
 211DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT)
 212DEF(dupi_vec, 1, 0, 1, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT)
 213
 214DEF(dup_vec, 1, 1, 0, IMPLVEC)
 215DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BITS == 32))
 216
 217DEF(ld_vec, 1, 1, 1, IMPLVEC)
 218DEF(st_vec, 0, 2, 1, IMPLVEC)
 219
 220DEF(add_vec, 1, 2, 0, IMPLVEC)
 221DEF(sub_vec, 1, 2, 0, IMPLVEC)
 222DEF(mul_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_mul_vec))
 223DEF(neg_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_neg_vec))
 224
 225DEF(and_vec, 1, 2, 0, IMPLVEC)
 226DEF(or_vec, 1, 2, 0, IMPLVEC)
 227DEF(xor_vec, 1, 2, 0, IMPLVEC)
 228DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec))
 229DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec))
 230DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))
 231
 232DEF(shli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
 233DEF(shri_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
 234DEF(sari_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
 235
 236DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
 237DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
 238DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
 239
 240DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
 241DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
 242DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
 243
 244DEF(cmp_vec, 1, 2, 1, IMPLVEC)
 245
 246DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
 247
 248#if TCG_TARGET_MAYBE_vec
 249#include "tcg-target.opc.h"
 250#endif
 251
 252#undef TLADDR_ARGS
 253#undef DATA64_ARGS
 254#undef IMPL
 255#undef IMPL64
 256#undef IMPLVEC
 257#undef DEF
 258