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15#include "qemu/osdep.h"
16#include "qemu/bitops.h"
17#include "qemu/main-loop.h"
18#include "trace.h"
19#include "gicv3_internal.h"
20#include "cpu.h"
21
22void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s)
23{
24 ARMCPU *arm_cpu = ARM_CPU(cpu);
25 CPUARMState *env = &arm_cpu->env;
26
27 env->gicv3state = (void *)s;
28};
29
30static GICv3CPUState *icc_cs_from_env(CPUARMState *env)
31{
32 return env->gicv3state;
33}
34
35static bool gicv3_use_ns_bank(CPUARMState *env)
36{
37
38
39
40
41
42 return !arm_is_secure_below_el3(env);
43}
44
45
46static inline int icv_min_vbpr(GICv3CPUState *cs)
47{
48 return 7 - cs->vprebits;
49}
50
51
52static uint32_t ich_lr_vintid(uint64_t lr)
53{
54 return extract64(lr, ICH_LR_EL2_VINTID_SHIFT, ICH_LR_EL2_VINTID_LENGTH);
55}
56
57static uint32_t ich_lr_pintid(uint64_t lr)
58{
59 return extract64(lr, ICH_LR_EL2_PINTID_SHIFT, ICH_LR_EL2_PINTID_LENGTH);
60}
61
62static uint32_t ich_lr_prio(uint64_t lr)
63{
64 return extract64(lr, ICH_LR_EL2_PRIORITY_SHIFT, ICH_LR_EL2_PRIORITY_LENGTH);
65}
66
67static int ich_lr_state(uint64_t lr)
68{
69 return extract64(lr, ICH_LR_EL2_STATE_SHIFT, ICH_LR_EL2_STATE_LENGTH);
70}
71
72static bool icv_access(CPUARMState *env, int hcr_flags)
73{
74
75
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85
86
87
88 bool flagmatch = ((hcr_flags & HCR_IMO) && arm_hcr_el2_imo(env)) ||
89 ((hcr_flags & HCR_FMO) && arm_hcr_el2_fmo(env));
90
91 return flagmatch && arm_current_el(env) == 1
92 && !arm_is_secure_below_el3(env);
93}
94
95static int read_vbpr(GICv3CPUState *cs, int grp)
96{
97
98
99
100 if (grp == GICV3_G0) {
101 return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT,
102 ICH_VMCR_EL2_VBPR0_LENGTH);
103 } else {
104 return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR1_SHIFT,
105 ICH_VMCR_EL2_VBPR1_LENGTH);
106 }
107}
108
109static void write_vbpr(GICv3CPUState *cs, int grp, int value)
110{
111
112
113
114 int min = icv_min_vbpr(cs);
115
116 if (grp != GICV3_G0) {
117 min++;
118 }
119
120 value = MAX(value, min);
121
122 if (grp == GICV3_G0) {
123 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT,
124 ICH_VMCR_EL2_VBPR0_LENGTH, value);
125 } else {
126 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR1_SHIFT,
127 ICH_VMCR_EL2_VBPR1_LENGTH, value);
128 }
129}
130
131static uint32_t icv_fullprio_mask(GICv3CPUState *cs)
132{
133
134
135
136
137
138 return ~0U << (8 - cs->vpribits);
139}
140
141static int ich_highest_active_virt_prio(GICv3CPUState *cs)
142{
143
144
145
146 int i;
147 int aprmax = 1 << (cs->vprebits - 5);
148
149 assert(aprmax <= ARRAY_SIZE(cs->ich_apr[0]));
150
151 for (i = 0; i < aprmax; i++) {
152 uint32_t apr = cs->ich_apr[GICV3_G0][i] |
153 cs->ich_apr[GICV3_G1NS][i];
154
155 if (!apr) {
156 continue;
157 }
158 return (i * 32 + ctz32(apr)) << (icv_min_vbpr(cs) + 1);
159 }
160
161 return 0xff;
162}
163
164static int hppvi_index(GICv3CPUState *cs)
165{
166
167
168
169
170 int idx = -1;
171 int i;
172
173
174
175
176 int prio = 0xff;
177
178 if (!(cs->ich_vmcr_el2 & (ICH_VMCR_EL2_VENG0 | ICH_VMCR_EL2_VENG1))) {
179
180 return idx;
181 }
182
183 for (i = 0; i < cs->num_list_regs; i++) {
184 uint64_t lr = cs->ich_lr_el2[i];
185 int thisprio;
186
187 if (ich_lr_state(lr) != ICH_LR_EL2_STATE_PENDING) {
188
189 continue;
190 }
191
192
193 if (lr & ICH_LR_EL2_GROUP) {
194 if (!(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
195 continue;
196 }
197 } else {
198 if (!(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG0)) {
199 continue;
200 }
201 }
202
203 thisprio = ich_lr_prio(lr);
204
205 if (thisprio < prio) {
206 prio = thisprio;
207 idx = i;
208 }
209 }
210
211 return idx;
212}
213
214static uint32_t icv_gprio_mask(GICv3CPUState *cs, int group)
215{
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234 int bpr;
235
236 if (group == GICV3_G1NS && cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR) {
237 group = GICV3_G0;
238 }
239
240 bpr = read_vbpr(cs, group);
241 if (group == GICV3_G1NS) {
242 assert(bpr > 0);
243 bpr--;
244 }
245
246 return ~0U << (bpr + 1);
247}
248
249static bool icv_hppi_can_preempt(GICv3CPUState *cs, uint64_t lr)
250{
251
252
253
254
255
256
257 int grp;
258 uint32_t mask, prio, rprio, vpmr;
259
260 if (!(cs->ich_hcr_el2 & ICH_HCR_EL2_EN)) {
261
262 return false;
263 }
264
265
266
267
268
269 prio = ich_lr_prio(lr);
270 vpmr = extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT,
271 ICH_VMCR_EL2_VPMR_LENGTH);
272
273 if (prio >= vpmr) {
274
275 return false;
276 }
277
278 rprio = ich_highest_active_virt_prio(cs);
279 if (rprio == 0xff) {
280
281 return true;
282 }
283
284 grp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0;
285
286 mask = icv_gprio_mask(cs, grp);
287
288
289
290
291 if ((prio & mask) < (rprio & mask)) {
292 return true;
293 }
294
295 return false;
296}
297
298static uint32_t eoi_maintenance_interrupt_state(GICv3CPUState *cs,
299 uint32_t *misr)
300{
301
302
303
304
305
306
307
308 uint32_t value = 0;
309 int validcount = 0;
310 bool seenpending = false;
311 int i;
312
313 for (i = 0; i < cs->num_list_regs; i++) {
314 uint64_t lr = cs->ich_lr_el2[i];
315
316 if ((lr & (ICH_LR_EL2_STATE_MASK | ICH_LR_EL2_HW | ICH_LR_EL2_EOI))
317 == ICH_LR_EL2_EOI) {
318 value |= (1 << i);
319 }
320 if ((lr & ICH_LR_EL2_STATE_MASK)) {
321 validcount++;
322 }
323 if (ich_lr_state(lr) == ICH_LR_EL2_STATE_PENDING) {
324 seenpending = true;
325 }
326 }
327
328 if (misr) {
329 if (validcount < 2 && (cs->ich_hcr_el2 & ICH_HCR_EL2_UIE)) {
330 *misr |= ICH_MISR_EL2_U;
331 }
332 if (!seenpending && (cs->ich_hcr_el2 & ICH_HCR_EL2_NPIE)) {
333 *misr |= ICH_MISR_EL2_NP;
334 }
335 if (value) {
336 *misr |= ICH_MISR_EL2_EOI;
337 }
338 }
339 return value;
340}
341
342static uint32_t maintenance_interrupt_state(GICv3CPUState *cs)
343{
344
345
346
347 uint32_t value = 0;
348
349
350 eoi_maintenance_interrupt_state(cs, &value);
351
352 if (cs->ich_hcr_el2 & (ICH_HCR_EL2_LRENPIE | ICH_HCR_EL2_EOICOUNT_MASK)) {
353 value |= ICH_MISR_EL2_LRENP;
354 }
355
356 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_VGRP0EIE) &&
357 (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG0)) {
358 value |= ICH_MISR_EL2_VGRP0E;
359 }
360
361 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_VGRP0DIE) &&
362 !(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
363 value |= ICH_MISR_EL2_VGRP0D;
364 }
365 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_VGRP1EIE) &&
366 (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
367 value |= ICH_MISR_EL2_VGRP1E;
368 }
369
370 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_VGRP1DIE) &&
371 !(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
372 value |= ICH_MISR_EL2_VGRP1D;
373 }
374
375 return value;
376}
377
378static void gicv3_cpuif_virt_update(GICv3CPUState *cs)
379{
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395
396
397 int idx;
398 int irqlevel = 0;
399 int fiqlevel = 0;
400 int maintlevel = 0;
401
402 idx = hppvi_index(cs);
403 trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx);
404 if (idx >= 0) {
405 uint64_t lr = cs->ich_lr_el2[idx];
406
407 if (icv_hppi_can_preempt(cs, lr)) {
408
409 if (lr & ICH_LR_EL2_GROUP) {
410 irqlevel = 1;
411 } else {
412 fiqlevel = 1;
413 }
414 }
415 }
416
417 if (cs->ich_hcr_el2 & ICH_HCR_EL2_EN) {
418 maintlevel = maintenance_interrupt_state(cs);
419 }
420
421 trace_gicv3_cpuif_virt_set_irqs(gicv3_redist_affid(cs), fiqlevel,
422 irqlevel, maintlevel);
423
424 qemu_set_irq(cs->parent_vfiq, fiqlevel);
425 qemu_set_irq(cs->parent_virq, irqlevel);
426 qemu_set_irq(cs->maintenance_irq, maintlevel);
427}
428
429static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
430{
431 GICv3CPUState *cs = icc_cs_from_env(env);
432 int regno = ri->opc2 & 3;
433 int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
434 uint64_t value = cs->ich_apr[grp][regno];
435
436 trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
437 return value;
438}
439
440static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
441 uint64_t value)
442{
443 GICv3CPUState *cs = icc_cs_from_env(env);
444 int regno = ri->opc2 & 3;
445 int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
446
447 trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
448
449 cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU;
450
451 gicv3_cpuif_virt_update(cs);
452 return;
453}
454
455static uint64_t icv_bpr_read(CPUARMState *env, const ARMCPRegInfo *ri)
456{
457 GICv3CPUState *cs = icc_cs_from_env(env);
458 int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1NS;
459 uint64_t bpr;
460 bool satinc = false;
461
462 if (grp == GICV3_G1NS && (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) {
463
464 grp = GICV3_G0;
465 satinc = true;
466 }
467
468 bpr = read_vbpr(cs, grp);
469
470 if (satinc) {
471 bpr++;
472 bpr = MIN(bpr, 7);
473 }
474
475 trace_gicv3_icv_bpr_read(ri->crm == 8 ? 0 : 1, gicv3_redist_affid(cs), bpr);
476
477 return bpr;
478}
479
480static void icv_bpr_write(CPUARMState *env, const ARMCPRegInfo *ri,
481 uint64_t value)
482{
483 GICv3CPUState *cs = icc_cs_from_env(env);
484 int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1NS;
485
486 trace_gicv3_icv_bpr_write(ri->crm == 8 ? 0 : 1,
487 gicv3_redist_affid(cs), value);
488
489 if (grp == GICV3_G1NS && (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) {
490
491 return;
492 }
493
494 write_vbpr(cs, grp, value);
495
496 gicv3_cpuif_virt_update(cs);
497}
498
499static uint64_t icv_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri)
500{
501 GICv3CPUState *cs = icc_cs_from_env(env);
502 uint64_t value;
503
504 value = extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT,
505 ICH_VMCR_EL2_VPMR_LENGTH);
506
507 trace_gicv3_icv_pmr_read(gicv3_redist_affid(cs), value);
508 return value;
509}
510
511static void icv_pmr_write(CPUARMState *env, const ARMCPRegInfo *ri,
512 uint64_t value)
513{
514 GICv3CPUState *cs = icc_cs_from_env(env);
515
516 trace_gicv3_icv_pmr_write(gicv3_redist_affid(cs), value);
517
518 value &= icv_fullprio_mask(cs);
519
520 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT,
521 ICH_VMCR_EL2_VPMR_LENGTH, value);
522
523 gicv3_cpuif_virt_update(cs);
524}
525
526static uint64_t icv_igrpen_read(CPUARMState *env, const ARMCPRegInfo *ri)
527{
528 GICv3CPUState *cs = icc_cs_from_env(env);
529 int enbit;
530 uint64_t value;
531
532 enbit = ri->opc2 & 1 ? ICH_VMCR_EL2_VENG1_SHIFT : ICH_VMCR_EL2_VENG0_SHIFT;
533 value = extract64(cs->ich_vmcr_el2, enbit, 1);
534
535 trace_gicv3_icv_igrpen_read(ri->opc2 & 1 ? 1 : 0,
536 gicv3_redist_affid(cs), value);
537 return value;
538}
539
540static void icv_igrpen_write(CPUARMState *env, const ARMCPRegInfo *ri,
541 uint64_t value)
542{
543 GICv3CPUState *cs = icc_cs_from_env(env);
544 int enbit;
545
546 trace_gicv3_icv_igrpen_write(ri->opc2 & 1 ? 1 : 0,
547 gicv3_redist_affid(cs), value);
548
549 enbit = ri->opc2 & 1 ? ICH_VMCR_EL2_VENG1_SHIFT : ICH_VMCR_EL2_VENG0_SHIFT;
550
551 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, enbit, 1, value);
552 gicv3_cpuif_virt_update(cs);
553}
554
555static uint64_t icv_ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
556{
557 GICv3CPUState *cs = icc_cs_from_env(env);
558 uint64_t value;
559
560
561
562
563 value = ICC_CTLR_EL1_A3V | (1 << ICC_CTLR_EL1_IDBITS_SHIFT) |
564 (7 << ICC_CTLR_EL1_PRIBITS_SHIFT);
565
566 if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VEOIM) {
567 value |= ICC_CTLR_EL1_EOIMODE;
568 }
569
570 if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR) {
571 value |= ICC_CTLR_EL1_CBPR;
572 }
573
574 trace_gicv3_icv_ctlr_read(gicv3_redist_affid(cs), value);
575 return value;
576}
577
578static void icv_ctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
579 uint64_t value)
580{
581 GICv3CPUState *cs = icc_cs_from_env(env);
582
583 trace_gicv3_icv_ctlr_write(gicv3_redist_affid(cs), value);
584
585 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VCBPR_SHIFT,
586 1, value & ICC_CTLR_EL1_CBPR ? 1 : 0);
587 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VEOIM_SHIFT,
588 1, value & ICC_CTLR_EL1_EOIMODE ? 1 : 0);
589
590 gicv3_cpuif_virt_update(cs);
591}
592
593static uint64_t icv_rpr_read(CPUARMState *env, const ARMCPRegInfo *ri)
594{
595 GICv3CPUState *cs = icc_cs_from_env(env);
596 int prio = ich_highest_active_virt_prio(cs);
597
598 trace_gicv3_icv_rpr_read(gicv3_redist_affid(cs), prio);
599 return prio;
600}
601
602static uint64_t icv_hppir_read(CPUARMState *env, const ARMCPRegInfo *ri)
603{
604 GICv3CPUState *cs = icc_cs_from_env(env);
605 int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS;
606 int idx = hppvi_index(cs);
607 uint64_t value = INTID_SPURIOUS;
608
609 if (idx >= 0) {
610 uint64_t lr = cs->ich_lr_el2[idx];
611 int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0;
612
613 if (grp == thisgrp) {
614 value = ich_lr_vintid(lr);
615 }
616 }
617
618 trace_gicv3_icv_hppir_read(grp, gicv3_redist_affid(cs), value);
619 return value;
620}
621
622static void icv_activate_irq(GICv3CPUState *cs, int idx, int grp)
623{
624
625
626
627
628 uint32_t mask = icv_gprio_mask(cs, grp);
629 int prio = ich_lr_prio(cs->ich_lr_el2[idx]) & mask;
630 int aprbit = prio >> (8 - cs->vprebits);
631 int regno = aprbit / 32;
632 int regbit = aprbit % 32;
633
634 cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT;
635 cs->ich_lr_el2[idx] |= ICH_LR_EL2_STATE_ACTIVE_BIT;
636 cs->ich_apr[grp][regno] |= (1 << regbit);
637}
638
639static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri)
640{
641 GICv3CPUState *cs = icc_cs_from_env(env);
642 int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS;
643 int idx = hppvi_index(cs);
644 uint64_t intid = INTID_SPURIOUS;
645
646 if (idx >= 0) {
647 uint64_t lr = cs->ich_lr_el2[idx];
648 int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0;
649
650 if (thisgrp == grp && icv_hppi_can_preempt(cs, lr)) {
651 intid = ich_lr_vintid(lr);
652 if (intid < INTID_SECURE) {
653 icv_activate_irq(cs, idx, grp);
654 } else {
655
656 cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT;
657
658
659
660 }
661 }
662 }
663
664 trace_gicv3_icv_iar_read(ri->crm == 8 ? 0 : 1,
665 gicv3_redist_affid(cs), intid);
666 return intid;
667}
668
669static int icc_highest_active_prio(GICv3CPUState *cs)
670{
671
672
673
674 int i;
675
676 for (i = 0; i < ARRAY_SIZE(cs->icc_apr[0]); i++) {
677 uint32_t apr = cs->icc_apr[GICV3_G0][i] |
678 cs->icc_apr[GICV3_G1][i] | cs->icc_apr[GICV3_G1NS][i];
679
680 if (!apr) {
681 continue;
682 }
683 return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1);
684 }
685
686 return 0xff;
687}
688
689static uint32_t icc_gprio_mask(GICv3CPUState *cs, int group)
690{
691
692
693
694
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696
697
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705
706
707
708 int bpr;
709
710 if ((group == GICV3_G1 && cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_CBPR) ||
711 (group == GICV3_G1NS &&
712 cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR)) {
713 group = GICV3_G0;
714 }
715
716 bpr = cs->icc_bpr[group] & 7;
717
718 if (group == GICV3_G1NS) {
719 assert(bpr > 0);
720 bpr--;
721 }
722
723 return ~0U << (bpr + 1);
724}
725
726static bool icc_no_enabled_hppi(GICv3CPUState *cs)
727{
728
729
730
731
732 return cs->hppi.prio == 0xff || (cs->icc_igrpen[cs->hppi.grp] == 0);
733}
734
735static bool icc_hppi_can_preempt(GICv3CPUState *cs)
736{
737
738
739
740 int rprio;
741 uint32_t mask;
742
743 if (icc_no_enabled_hppi(cs)) {
744 return false;
745 }
746
747 if (cs->hppi.prio >= cs->icc_pmr_el1) {
748
749 return false;
750 }
751
752 rprio = icc_highest_active_prio(cs);
753 if (rprio == 0xff) {
754
755 return true;
756 }
757
758 mask = icc_gprio_mask(cs, cs->hppi.grp);
759
760
761
762
763 if ((cs->hppi.prio & mask) < (rprio & mask)) {
764 return true;
765 }
766
767 return false;
768}
769
770void gicv3_cpuif_update(GICv3CPUState *cs)
771{
772
773 int irqlevel = 0;
774 int fiqlevel = 0;
775 ARMCPU *cpu = ARM_CPU(cs->cpu);
776 CPUARMState *env = &cpu->env;
777
778 g_assert(qemu_mutex_iothread_locked());
779
780 trace_gicv3_cpuif_update(gicv3_redist_affid(cs), cs->hppi.irq,
781 cs->hppi.grp, cs->hppi.prio);
782
783 if (cs->hppi.grp == GICV3_G1 && !arm_feature(env, ARM_FEATURE_EL3)) {
784
785
786
787 cs->hppi.grp = GICV3_G0;
788 }
789
790 if (icc_hppi_can_preempt(cs)) {
791
792
793
794 bool isfiq;
795
796 switch (cs->hppi.grp) {
797 case GICV3_G0:
798 isfiq = true;
799 break;
800 case GICV3_G1:
801 isfiq = (!arm_is_secure(env) ||
802 (arm_current_el(env) == 3 && arm_el_is_aa64(env, 3)));
803 break;
804 case GICV3_G1NS:
805 isfiq = arm_is_secure(env);
806 break;
807 default:
808 g_assert_not_reached();
809 }
810
811 if (isfiq) {
812 fiqlevel = 1;
813 } else {
814 irqlevel = 1;
815 }
816 }
817
818 trace_gicv3_cpuif_set_irqs(gicv3_redist_affid(cs), fiqlevel, irqlevel);
819
820 qemu_set_irq(cs->parent_fiq, fiqlevel);
821 qemu_set_irq(cs->parent_irq, irqlevel);
822}
823
824static uint64_t icc_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri)
825{
826 GICv3CPUState *cs = icc_cs_from_env(env);
827 uint32_t value = cs->icc_pmr_el1;
828
829 if (icv_access(env, HCR_FMO | HCR_IMO)) {
830 return icv_pmr_read(env, ri);
831 }
832
833 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env) &&
834 (env->cp15.scr_el3 & SCR_FIQ)) {
835
836
837
838 if ((value & 0x80) == 0) {
839
840 value = 0;
841 } else if (value != 0xff) {
842 value = (value << 1) & 0xff;
843 }
844 }
845
846 trace_gicv3_icc_pmr_read(gicv3_redist_affid(cs), value);
847
848 return value;
849}
850
851static void icc_pmr_write(CPUARMState *env, const ARMCPRegInfo *ri,
852 uint64_t value)
853{
854 GICv3CPUState *cs = icc_cs_from_env(env);
855
856 if (icv_access(env, HCR_FMO | HCR_IMO)) {
857 return icv_pmr_write(env, ri, value);
858 }
859
860 trace_gicv3_icc_pmr_write(gicv3_redist_affid(cs), value);
861
862 value &= 0xff;
863
864 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env) &&
865 (env->cp15.scr_el3 & SCR_FIQ)) {
866
867
868
869 if (!(cs->icc_pmr_el1 & 0x80)) {
870
871 return;
872 }
873 value = (value >> 1) | 0x80;
874 }
875 cs->icc_pmr_el1 = value;
876 gicv3_cpuif_update(cs);
877}
878
879static void icc_activate_irq(GICv3CPUState *cs, int irq)
880{
881
882
883
884 uint32_t mask = icc_gprio_mask(cs, cs->hppi.grp);
885 int prio = cs->hppi.prio & mask;
886 int aprbit = prio >> 1;
887 int regno = aprbit / 32;
888 int regbit = aprbit % 32;
889
890 cs->icc_apr[cs->hppi.grp][regno] |= (1 << regbit);
891
892 if (irq < GIC_INTERNAL) {
893 cs->gicr_iactiver0 = deposit32(cs->gicr_iactiver0, irq, 1, 1);
894 cs->gicr_ipendr0 = deposit32(cs->gicr_ipendr0, irq, 1, 0);
895 gicv3_redist_update(cs);
896 } else {
897 gicv3_gicd_active_set(cs->gic, irq);
898 gicv3_gicd_pending_clear(cs->gic, irq);
899 gicv3_update(cs->gic, irq, 1);
900 }
901}
902
903static uint64_t icc_hppir0_value(GICv3CPUState *cs, CPUARMState *env)
904{
905
906
907
908 bool irq_is_secure;
909
910 if (cs->hppi.prio == 0xff) {
911 return INTID_SPURIOUS;
912 }
913
914
915
916
917
918
919 irq_is_secure = (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) &&
920 (cs->hppi.grp != GICV3_G1NS));
921
922 if (cs->hppi.grp != GICV3_G0 && !arm_is_el3_or_mon(env)) {
923 return INTID_SPURIOUS;
924 }
925 if (irq_is_secure && !arm_is_secure(env)) {
926
927 return INTID_SPURIOUS;
928 }
929
930 if (cs->hppi.grp != GICV3_G0) {
931
932
933
934 return irq_is_secure ? INTID_SECURE : INTID_NONSECURE;
935 }
936
937 return cs->hppi.irq;
938}
939
940static uint64_t icc_hppir1_value(GICv3CPUState *cs, CPUARMState *env)
941{
942
943
944
945 bool irq_is_secure;
946
947 if (cs->hppi.prio == 0xff) {
948 return INTID_SPURIOUS;
949 }
950
951
952
953
954
955
956 irq_is_secure = (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) &&
957 (cs->hppi.grp != GICV3_G1NS));
958
959 if (cs->hppi.grp == GICV3_G0) {
960
961 return INTID_SPURIOUS;
962 }
963 if (irq_is_secure) {
964 if (!arm_is_secure(env)) {
965
966 return INTID_SPURIOUS;
967 }
968 } else if (!arm_is_el3_or_mon(env) && arm_is_secure(env)) {
969
970 return INTID_SPURIOUS;
971 }
972
973 return cs->hppi.irq;
974}
975
976static uint64_t icc_iar0_read(CPUARMState *env, const ARMCPRegInfo *ri)
977{
978 GICv3CPUState *cs = icc_cs_from_env(env);
979 uint64_t intid;
980
981 if (icv_access(env, HCR_FMO)) {
982 return icv_iar_read(env, ri);
983 }
984
985 if (!icc_hppi_can_preempt(cs)) {
986 intid = INTID_SPURIOUS;
987 } else {
988 intid = icc_hppir0_value(cs, env);
989 }
990
991 if (!(intid >= INTID_SECURE && intid <= INTID_SPURIOUS)) {
992 icc_activate_irq(cs, intid);
993 }
994
995 trace_gicv3_icc_iar0_read(gicv3_redist_affid(cs), intid);
996 return intid;
997}
998
999static uint64_t icc_iar1_read(CPUARMState *env, const ARMCPRegInfo *ri)
1000{
1001 GICv3CPUState *cs = icc_cs_from_env(env);
1002 uint64_t intid;
1003
1004 if (icv_access(env, HCR_IMO)) {
1005 return icv_iar_read(env, ri);
1006 }
1007
1008 if (!icc_hppi_can_preempt(cs)) {
1009 intid = INTID_SPURIOUS;
1010 } else {
1011 intid = icc_hppir1_value(cs, env);
1012 }
1013
1014 if (!(intid >= INTID_SECURE && intid <= INTID_SPURIOUS)) {
1015 icc_activate_irq(cs, intid);
1016 }
1017
1018 trace_gicv3_icc_iar1_read(gicv3_redist_affid(cs), intid);
1019 return intid;
1020}
1021
1022static void icc_drop_prio(GICv3CPUState *cs, int grp)
1023{
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040 int i;
1041
1042 for (i = 0; i < ARRAY_SIZE(cs->icc_apr[grp]); i++) {
1043 uint64_t *papr = &cs->icc_apr[grp][i];
1044
1045 if (!*papr) {
1046 continue;
1047 }
1048
1049 *papr &= *papr - 1;
1050 break;
1051 }
1052
1053
1054 gicv3_cpuif_update(cs);
1055}
1056
1057static bool icc_eoi_split(CPUARMState *env, GICv3CPUState *cs)
1058{
1059
1060
1061
1062 if (arm_is_el3_or_mon(env)) {
1063 return cs->icc_ctlr_el3 & ICC_CTLR_EL3_EOIMODE_EL3;
1064 }
1065 if (arm_is_secure_below_el3(env)) {
1066 return cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_EOIMODE;
1067 } else {
1068 return cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE;
1069 }
1070}
1071
1072static int icc_highest_active_group(GICv3CPUState *cs)
1073{
1074
1075
1076
1077
1078
1079
1080 int i;
1081
1082 for (i = 0; i < ARRAY_SIZE(cs->icc_apr[0]); i++) {
1083 int g0ctz = ctz32(cs->icc_apr[GICV3_G0][i]);
1084 int g1ctz = ctz32(cs->icc_apr[GICV3_G1][i]);
1085 int g1nsctz = ctz32(cs->icc_apr[GICV3_G1NS][i]);
1086
1087 if (g1nsctz < g0ctz && g1nsctz < g1ctz) {
1088 return GICV3_G1NS;
1089 }
1090 if (g1ctz < g0ctz) {
1091 return GICV3_G1;
1092 }
1093 if (g0ctz < 32) {
1094 return GICV3_G0;
1095 }
1096 }
1097
1098
1099
1100 return -1;
1101}
1102
1103static void icc_deactivate_irq(GICv3CPUState *cs, int irq)
1104{
1105 if (irq < GIC_INTERNAL) {
1106 cs->gicr_iactiver0 = deposit32(cs->gicr_iactiver0, irq, 1, 0);
1107 gicv3_redist_update(cs);
1108 } else {
1109 gicv3_gicd_active_clear(cs->gic, irq);
1110 gicv3_update(cs->gic, irq, 1);
1111 }
1112}
1113
1114static bool icv_eoi_split(CPUARMState *env, GICv3CPUState *cs)
1115{
1116
1117
1118
1119 return cs->ich_vmcr_el2 & ICH_VMCR_EL2_VEOIM;
1120}
1121
1122static int icv_find_active(GICv3CPUState *cs, int irq)
1123{
1124
1125
1126
1127
1128 int i;
1129
1130 for (i = 0; i < cs->num_list_regs; i++) {
1131 uint64_t lr = cs->ich_lr_el2[i];
1132
1133 if ((lr & ICH_LR_EL2_STATE_ACTIVE_BIT) && ich_lr_vintid(lr) == irq) {
1134 return i;
1135 }
1136 }
1137
1138 return -1;
1139}
1140
1141static void icv_deactivate_irq(GICv3CPUState *cs, int idx)
1142{
1143
1144 uint64_t lr = cs->ich_lr_el2[idx];
1145
1146 if (lr & ICH_LR_EL2_HW) {
1147
1148 int pirq = ich_lr_pintid(lr);
1149
1150 if (pirq < INTID_SECURE) {
1151 icc_deactivate_irq(cs, pirq);
1152 }
1153 }
1154
1155
1156
1157
1158 lr &= ~ICH_LR_EL2_STATE_ACTIVE_BIT;
1159 cs->ich_lr_el2[idx] = lr;
1160}
1161
1162static void icv_increment_eoicount(GICv3CPUState *cs)
1163{
1164
1165 int eoicount = extract64(cs->ich_hcr_el2, ICH_HCR_EL2_EOICOUNT_SHIFT,
1166 ICH_HCR_EL2_EOICOUNT_LENGTH);
1167
1168 cs->ich_hcr_el2 = deposit64(cs->ich_hcr_el2, ICH_HCR_EL2_EOICOUNT_SHIFT,
1169 ICH_HCR_EL2_EOICOUNT_LENGTH, eoicount + 1);
1170}
1171
1172static int icv_drop_prio(GICv3CPUState *cs)
1173{
1174
1175
1176
1177
1178
1179
1180
1181
1182 int i;
1183 int aprmax = 1 << (cs->vprebits - 5);
1184
1185 assert(aprmax <= ARRAY_SIZE(cs->ich_apr[0]));
1186
1187 for (i = 0; i < aprmax; i++) {
1188 uint64_t *papr0 = &cs->ich_apr[GICV3_G0][i];
1189 uint64_t *papr1 = &cs->ich_apr[GICV3_G1NS][i];
1190 int apr0count, apr1count;
1191
1192 if (!*papr0 && !*papr1) {
1193 continue;
1194 }
1195
1196
1197
1198
1199
1200 apr0count = ctz32(*papr0);
1201 apr1count = ctz32(*papr1);
1202
1203 if (apr0count <= apr1count) {
1204 *papr0 &= *papr0 - 1;
1205 return (apr0count + i * 32) << (icv_min_vbpr(cs) + 1);
1206 } else {
1207 *papr1 &= *papr1 - 1;
1208 return (apr1count + i * 32) << (icv_min_vbpr(cs) + 1);
1209 }
1210 }
1211 return 0xff;
1212}
1213
1214static void icv_dir_write(CPUARMState *env, const ARMCPRegInfo *ri,
1215 uint64_t value)
1216{
1217
1218 GICv3CPUState *cs = icc_cs_from_env(env);
1219 int idx;
1220 int irq = value & 0xffffff;
1221
1222 trace_gicv3_icv_dir_write(gicv3_redist_affid(cs), value);
1223
1224 if (irq >= cs->gic->num_irq) {
1225
1226 return;
1227 }
1228
1229 if (!icv_eoi_split(env, cs)) {
1230 return;
1231 }
1232
1233 idx = icv_find_active(cs, irq);
1234
1235 if (idx < 0) {
1236
1237
1238
1239 icv_increment_eoicount(cs);
1240 } else {
1241 icv_deactivate_irq(cs, idx);
1242 }
1243
1244 gicv3_cpuif_virt_update(cs);
1245}
1246
1247static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri,
1248 uint64_t value)
1249{
1250
1251 GICv3CPUState *cs = icc_cs_from_env(env);
1252 int irq = value & 0xffffff;
1253 int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS;
1254 int idx, dropprio;
1255
1256 trace_gicv3_icv_eoir_write(ri->crm == 8 ? 0 : 1,
1257 gicv3_redist_affid(cs), value);
1258
1259 if (irq >= cs->gic->num_irq) {
1260
1261 return;
1262 }
1263
1264
1265
1266
1267
1268 dropprio = icv_drop_prio(cs);
1269 if (dropprio == 0xff) {
1270
1271
1272
1273
1274 return;
1275 }
1276
1277 idx = icv_find_active(cs, irq);
1278
1279 if (idx < 0) {
1280
1281 icv_increment_eoicount(cs);
1282 } else {
1283 uint64_t lr = cs->ich_lr_el2[idx];
1284 int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0;
1285 int lr_gprio = ich_lr_prio(lr) & icv_gprio_mask(cs, grp);
1286
1287 if (thisgrp == grp && lr_gprio == dropprio) {
1288 if (!icv_eoi_split(env, cs)) {
1289
1290 icv_deactivate_irq(cs, idx);
1291 }
1292 }
1293 }
1294
1295 gicv3_cpuif_virt_update(cs);
1296}
1297
1298static void icc_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri,
1299 uint64_t value)
1300{
1301
1302 GICv3CPUState *cs = icc_cs_from_env(env);
1303 int irq = value & 0xffffff;
1304 int grp;
1305
1306 if (icv_access(env, ri->crm == 8 ? HCR_FMO : HCR_IMO)) {
1307 icv_eoir_write(env, ri, value);
1308 return;
1309 }
1310
1311 trace_gicv3_icc_eoir_write(ri->crm == 8 ? 0 : 1,
1312 gicv3_redist_affid(cs), value);
1313
1314 if (ri->crm == 8) {
1315
1316 grp = GICV3_G0;
1317 } else {
1318
1319 if (arm_is_secure(env)) {
1320 grp = GICV3_G1;
1321 } else {
1322 grp = GICV3_G1NS;
1323 }
1324 }
1325
1326 if (irq >= cs->gic->num_irq) {
1327
1328
1329
1330
1331
1332
1333
1334
1335 return;
1336 }
1337
1338 if (icc_highest_active_group(cs) != grp) {
1339 return;
1340 }
1341
1342 icc_drop_prio(cs, grp);
1343
1344 if (!icc_eoi_split(env, cs)) {
1345
1346 icc_deactivate_irq(cs, irq);
1347 }
1348}
1349
1350static uint64_t icc_hppir0_read(CPUARMState *env, const ARMCPRegInfo *ri)
1351{
1352 GICv3CPUState *cs = icc_cs_from_env(env);
1353 uint64_t value;
1354
1355 if (icv_access(env, HCR_FMO)) {
1356 return icv_hppir_read(env, ri);
1357 }
1358
1359 value = icc_hppir0_value(cs, env);
1360 trace_gicv3_icc_hppir0_read(gicv3_redist_affid(cs), value);
1361 return value;
1362}
1363
1364static uint64_t icc_hppir1_read(CPUARMState *env, const ARMCPRegInfo *ri)
1365{
1366 GICv3CPUState *cs = icc_cs_from_env(env);
1367 uint64_t value;
1368
1369 if (icv_access(env, HCR_IMO)) {
1370 return icv_hppir_read(env, ri);
1371 }
1372
1373 value = icc_hppir1_value(cs, env);
1374 trace_gicv3_icc_hppir1_read(gicv3_redist_affid(cs), value);
1375 return value;
1376}
1377
1378static uint64_t icc_bpr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1379{
1380 GICv3CPUState *cs = icc_cs_from_env(env);
1381 int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1;
1382 bool satinc = false;
1383 uint64_t bpr;
1384
1385 if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
1386 return icv_bpr_read(env, ri);
1387 }
1388
1389 if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) {
1390 grp = GICV3_G1NS;
1391 }
1392
1393 if (grp == GICV3_G1 && !arm_is_el3_or_mon(env) &&
1394 (cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_CBPR)) {
1395
1396
1397
1398 grp = GICV3_G0;
1399 }
1400
1401 if (grp == GICV3_G1NS && arm_current_el(env) < 3 &&
1402 (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR)) {
1403
1404 grp = GICV3_G0;
1405 satinc = true;
1406 }
1407
1408 bpr = cs->icc_bpr[grp];
1409 if (satinc) {
1410 bpr++;
1411 bpr = MIN(bpr, 7);
1412 }
1413
1414 trace_gicv3_icc_bpr_read(ri->crm == 8 ? 0 : 1, gicv3_redist_affid(cs), bpr);
1415
1416 return bpr;
1417}
1418
1419static void icc_bpr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1420 uint64_t value)
1421{
1422 GICv3CPUState *cs = icc_cs_from_env(env);
1423 int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1;
1424 uint64_t minval;
1425
1426 if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
1427 icv_bpr_write(env, ri, value);
1428 return;
1429 }
1430
1431 trace_gicv3_icc_bpr_write(ri->crm == 8 ? 0 : 1,
1432 gicv3_redist_affid(cs), value);
1433
1434 if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) {
1435 grp = GICV3_G1NS;
1436 }
1437
1438 if (grp == GICV3_G1 && !arm_is_el3_or_mon(env) &&
1439 (cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_CBPR)) {
1440
1441
1442
1443 grp = GICV3_G0;
1444 }
1445
1446 if (grp == GICV3_G1NS && arm_current_el(env) < 3 &&
1447 (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR)) {
1448
1449 return;
1450 }
1451
1452 minval = (grp == GICV3_G1NS) ? GIC_MIN_BPR_NS : GIC_MIN_BPR;
1453 if (value < minval) {
1454 value = minval;
1455 }
1456
1457 cs->icc_bpr[grp] = value & 7;
1458 gicv3_cpuif_update(cs);
1459}
1460
1461static uint64_t icc_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1462{
1463 GICv3CPUState *cs = icc_cs_from_env(env);
1464 uint64_t value;
1465
1466 int regno = ri->opc2 & 3;
1467 int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
1468
1469 if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
1470 return icv_ap_read(env, ri);
1471 }
1472
1473 if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) {
1474 grp = GICV3_G1NS;
1475 }
1476
1477 value = cs->icc_apr[grp][regno];
1478
1479 trace_gicv3_icc_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
1480 return value;
1481}
1482
1483static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1484 uint64_t value)
1485{
1486 GICv3CPUState *cs = icc_cs_from_env(env);
1487
1488 int regno = ri->opc2 & 3;
1489 int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
1490
1491 if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
1492 icv_ap_write(env, ri, value);
1493 return;
1494 }
1495
1496 trace_gicv3_icc_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
1497
1498 if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) {
1499 grp = GICV3_G1NS;
1500 }
1501
1502
1503
1504
1505
1506
1507 if (grp == GICV3_G1NS && regno < 2 && arm_feature(env, ARM_FEATURE_EL3)) {
1508 return;
1509 }
1510
1511 cs->icc_apr[grp][regno] = value & 0xFFFFFFFFU;
1512 gicv3_cpuif_update(cs);
1513}
1514
1515static void icc_dir_write(CPUARMState *env, const ARMCPRegInfo *ri,
1516 uint64_t value)
1517{
1518
1519 GICv3CPUState *cs = icc_cs_from_env(env);
1520 int irq = value & 0xffffff;
1521 bool irq_is_secure, single_sec_state, irq_is_grp0;
1522 bool route_fiq_to_el3, route_irq_to_el3, route_fiq_to_el2, route_irq_to_el2;
1523
1524 if (icv_access(env, HCR_FMO | HCR_IMO)) {
1525 icv_dir_write(env, ri, value);
1526 return;
1527 }
1528
1529 trace_gicv3_icc_dir_write(gicv3_redist_affid(cs), value);
1530
1531 if (irq >= cs->gic->num_irq) {
1532
1533 return;
1534 }
1535
1536 if (!icc_eoi_split(env, cs)) {
1537 return;
1538 }
1539
1540 int grp = gicv3_irq_group(cs->gic, cs, irq);
1541
1542 single_sec_state = cs->gic->gicd_ctlr & GICD_CTLR_DS;
1543 irq_is_secure = !single_sec_state && (grp != GICV3_G1NS);
1544 irq_is_grp0 = grp == GICV3_G0;
1545
1546
1547
1548
1549
1550 route_fiq_to_el3 = env->cp15.scr_el3 & SCR_FIQ;
1551 route_irq_to_el3 = env->cp15.scr_el3 & SCR_IRQ;
1552
1553
1554
1555 route_fiq_to_el2 = arm_hcr_el2_fmo(env);
1556 route_irq_to_el2 = arm_hcr_el2_imo(env);
1557
1558 switch (arm_current_el(env)) {
1559 case 3:
1560 break;
1561 case 2:
1562 if (single_sec_state && irq_is_grp0 && !route_fiq_to_el3) {
1563 break;
1564 }
1565 if (!irq_is_secure && !irq_is_grp0 && !route_irq_to_el3) {
1566 break;
1567 }
1568 return;
1569 case 1:
1570 if (!arm_is_secure_below_el3(env)) {
1571 if (single_sec_state && irq_is_grp0 &&
1572 !route_fiq_to_el3 && !route_fiq_to_el2) {
1573 break;
1574 }
1575 if (!irq_is_secure && !irq_is_grp0 &&
1576 !route_irq_to_el3 && !route_irq_to_el2) {
1577 break;
1578 }
1579 } else {
1580 if (irq_is_grp0 && !route_fiq_to_el3) {
1581 break;
1582 }
1583 if (!irq_is_grp0 &&
1584 (!irq_is_secure || !single_sec_state) &&
1585 !route_irq_to_el3) {
1586 break;
1587 }
1588 }
1589 return;
1590 default:
1591 g_assert_not_reached();
1592 }
1593
1594 icc_deactivate_irq(cs, irq);
1595}
1596
1597static uint64_t icc_rpr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1598{
1599 GICv3CPUState *cs = icc_cs_from_env(env);
1600 int prio;
1601
1602 if (icv_access(env, HCR_FMO | HCR_IMO)) {
1603 return icv_rpr_read(env, ri);
1604 }
1605
1606 prio = icc_highest_active_prio(cs);
1607
1608 if (arm_feature(env, ARM_FEATURE_EL3) &&
1609 !arm_is_secure(env) && (env->cp15.scr_el3 & SCR_FIQ)) {
1610
1611 if ((prio & 0x80) == 0) {
1612
1613 prio = 0;
1614 } else if (prio != 0xff) {
1615
1616 prio = (prio << 1) & 0xff;
1617 }
1618 }
1619
1620 trace_gicv3_icc_rpr_read(gicv3_redist_affid(cs), prio);
1621 return prio;
1622}
1623
1624static void icc_generate_sgi(CPUARMState *env, GICv3CPUState *cs,
1625 uint64_t value, int grp, bool ns)
1626{
1627 GICv3State *s = cs->gic;
1628
1629
1630 uint64_t aff = extract64(value, 48, 8) << 16 |
1631 extract64(value, 32, 8) << 8 |
1632 extract64(value, 16, 8);
1633 uint32_t targetlist = extract64(value, 0, 16);
1634 uint32_t irq = extract64(value, 24, 4);
1635 bool irm = extract64(value, 40, 1);
1636 int i;
1637
1638 if (grp == GICV3_G1 && s->gicd_ctlr & GICD_CTLR_DS) {
1639
1640
1641
1642
1643 grp = GICV3_G0;
1644 }
1645
1646 trace_gicv3_icc_generate_sgi(gicv3_redist_affid(cs), irq, irm,
1647 aff, targetlist);
1648
1649 for (i = 0; i < s->num_cpu; i++) {
1650 GICv3CPUState *ocs = &s->cpu[i];
1651
1652 if (irm) {
1653
1654 if (cs == ocs) {
1655 continue;
1656 }
1657 } else {
1658
1659
1660
1661 int aff0;
1662
1663 if (ocs->gicr_typer >> 40 != aff) {
1664 continue;
1665 }
1666 aff0 = extract64(ocs->gicr_typer, 32, 8);
1667 if (aff0 > 15 || extract32(targetlist, aff0, 1) == 0) {
1668 continue;
1669 }
1670 }
1671
1672
1673 gicv3_redist_send_sgi(ocs, grp, irq, ns);
1674 }
1675}
1676
1677static void icc_sgi0r_write(CPUARMState *env, const ARMCPRegInfo *ri,
1678 uint64_t value)
1679{
1680
1681 GICv3CPUState *cs = icc_cs_from_env(env);
1682 bool ns = !arm_is_secure(env);
1683
1684 icc_generate_sgi(env, cs, value, GICV3_G0, ns);
1685}
1686
1687static void icc_sgi1r_write(CPUARMState *env, const ARMCPRegInfo *ri,
1688 uint64_t value)
1689{
1690
1691 GICv3CPUState *cs = icc_cs_from_env(env);
1692 int grp;
1693 bool ns = !arm_is_secure(env);
1694
1695 grp = ns ? GICV3_G1NS : GICV3_G1;
1696 icc_generate_sgi(env, cs, value, grp, ns);
1697}
1698
1699static void icc_asgi1r_write(CPUARMState *env, const ARMCPRegInfo *ri,
1700 uint64_t value)
1701{
1702
1703
1704
1705 GICv3CPUState *cs = icc_cs_from_env(env);
1706 int grp;
1707 bool ns = !arm_is_secure(env);
1708
1709 grp = ns ? GICV3_G1 : GICV3_G1NS;
1710 icc_generate_sgi(env, cs, value, grp, ns);
1711}
1712
1713static uint64_t icc_igrpen_read(CPUARMState *env, const ARMCPRegInfo *ri)
1714{
1715 GICv3CPUState *cs = icc_cs_from_env(env);
1716 int grp = ri->opc2 & 1 ? GICV3_G1 : GICV3_G0;
1717 uint64_t value;
1718
1719 if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
1720 return icv_igrpen_read(env, ri);
1721 }
1722
1723 if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) {
1724 grp = GICV3_G1NS;
1725 }
1726
1727 value = cs->icc_igrpen[grp];
1728 trace_gicv3_icc_igrpen_read(ri->opc2 & 1 ? 1 : 0,
1729 gicv3_redist_affid(cs), value);
1730 return value;
1731}
1732
1733static void icc_igrpen_write(CPUARMState *env, const ARMCPRegInfo *ri,
1734 uint64_t value)
1735{
1736 GICv3CPUState *cs = icc_cs_from_env(env);
1737 int grp = ri->opc2 & 1 ? GICV3_G1 : GICV3_G0;
1738
1739 if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
1740 icv_igrpen_write(env, ri, value);
1741 return;
1742 }
1743
1744 trace_gicv3_icc_igrpen_write(ri->opc2 & 1 ? 1 : 0,
1745 gicv3_redist_affid(cs), value);
1746
1747 if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) {
1748 grp = GICV3_G1NS;
1749 }
1750
1751 cs->icc_igrpen[grp] = value & ICC_IGRPEN_ENABLE;
1752 gicv3_cpuif_update(cs);
1753}
1754
1755static uint64_t icc_igrpen1_el3_read(CPUARMState *env, const ARMCPRegInfo *ri)
1756{
1757 GICv3CPUState *cs = icc_cs_from_env(env);
1758 uint64_t value;
1759
1760
1761 value = cs->icc_igrpen[GICV3_G1NS] | (cs->icc_igrpen[GICV3_G1] << 1);
1762 trace_gicv3_icc_igrpen1_el3_read(gicv3_redist_affid(cs), value);
1763 return value;
1764}
1765
1766static void icc_igrpen1_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
1767 uint64_t value)
1768{
1769 GICv3CPUState *cs = icc_cs_from_env(env);
1770
1771 trace_gicv3_icc_igrpen1_el3_write(gicv3_redist_affid(cs), value);
1772
1773
1774 cs->icc_igrpen[GICV3_G1NS] = extract32(value, 0, 1);
1775 cs->icc_igrpen[GICV3_G1] = extract32(value, 1, 1);
1776 gicv3_cpuif_update(cs);
1777}
1778
1779static uint64_t icc_ctlr_el1_read(CPUARMState *env, const ARMCPRegInfo *ri)
1780{
1781 GICv3CPUState *cs = icc_cs_from_env(env);
1782 int bank = gicv3_use_ns_bank(env) ? GICV3_NS : GICV3_S;
1783 uint64_t value;
1784
1785 if (icv_access(env, HCR_FMO | HCR_IMO)) {
1786 return icv_ctlr_read(env, ri);
1787 }
1788
1789 value = cs->icc_ctlr_el1[bank];
1790 trace_gicv3_icc_ctlr_read(gicv3_redist_affid(cs), value);
1791 return value;
1792}
1793
1794static void icc_ctlr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
1795 uint64_t value)
1796{
1797 GICv3CPUState *cs = icc_cs_from_env(env);
1798 int bank = gicv3_use_ns_bank(env) ? GICV3_NS : GICV3_S;
1799 uint64_t mask;
1800
1801 if (icv_access(env, HCR_FMO | HCR_IMO)) {
1802 icv_ctlr_write(env, ri, value);
1803 return;
1804 }
1805
1806 trace_gicv3_icc_ctlr_write(gicv3_redist_affid(cs), value);
1807
1808
1809
1810
1811
1812
1813 if (arm_feature(env, ARM_FEATURE_EL3) &&
1814 ((cs->gic->gicd_ctlr & GICD_CTLR_DS) == 0)) {
1815 mask = ICC_CTLR_EL1_EOIMODE;
1816 } else {
1817 mask = ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE;
1818 }
1819
1820 cs->icc_ctlr_el1[bank] &= ~mask;
1821 cs->icc_ctlr_el1[bank] |= (value & mask);
1822 gicv3_cpuif_update(cs);
1823}
1824
1825
1826static uint64_t icc_ctlr_el3_read(CPUARMState *env, const ARMCPRegInfo *ri)
1827{
1828 GICv3CPUState *cs = icc_cs_from_env(env);
1829 uint64_t value;
1830
1831 value = cs->icc_ctlr_el3;
1832 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) {
1833 value |= ICC_CTLR_EL3_EOIMODE_EL1NS;
1834 }
1835 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR) {
1836 value |= ICC_CTLR_EL3_CBPR_EL1NS;
1837 }
1838 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) {
1839 value |= ICC_CTLR_EL3_EOIMODE_EL1S;
1840 }
1841 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR) {
1842 value |= ICC_CTLR_EL3_CBPR_EL1S;
1843 }
1844
1845 trace_gicv3_icc_ctlr_el3_read(gicv3_redist_affid(cs), value);
1846 return value;
1847}
1848
1849static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
1850 uint64_t value)
1851{
1852 GICv3CPUState *cs = icc_cs_from_env(env);
1853 uint64_t mask;
1854
1855 trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value);
1856
1857
1858 cs->icc_ctlr_el1[GICV3_NS] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
1859 if (value & ICC_CTLR_EL3_EOIMODE_EL1NS) {
1860 cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE;
1861 }
1862 if (value & ICC_CTLR_EL3_CBPR_EL1NS) {
1863 cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR;
1864 }
1865
1866 cs->icc_ctlr_el1[GICV3_S] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
1867 if (value & ICC_CTLR_EL3_EOIMODE_EL1S) {
1868 cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE;
1869 }
1870 if (value & ICC_CTLR_EL3_CBPR_EL1S) {
1871 cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_CBPR;
1872 }
1873
1874
1875 mask = ICC_CTLR_EL3_EOIMODE_EL3;
1876
1877 cs->icc_ctlr_el3 &= ~mask;
1878 cs->icc_ctlr_el3 |= (value & mask);
1879 gicv3_cpuif_update(cs);
1880}
1881
1882static CPAccessResult gicv3_irqfiq_access(CPUARMState *env,
1883 const ARMCPRegInfo *ri, bool isread)
1884{
1885 CPAccessResult r = CP_ACCESS_OK;
1886 GICv3CPUState *cs = icc_cs_from_env(env);
1887 int el = arm_current_el(env);
1888
1889 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_TC) &&
1890 el == 1 && !arm_is_secure_below_el3(env)) {
1891
1892 return CP_ACCESS_TRAP_EL2;
1893 }
1894
1895 if ((env->cp15.scr_el3 & (SCR_FIQ | SCR_IRQ)) == (SCR_FIQ | SCR_IRQ)) {
1896 switch (el) {
1897 case 1:
1898 if (arm_is_secure_below_el3(env) ||
1899 (arm_hcr_el2_imo(env) == 0 && arm_hcr_el2_fmo(env) == 0)) {
1900 r = CP_ACCESS_TRAP_EL3;
1901 }
1902 break;
1903 case 2:
1904 r = CP_ACCESS_TRAP_EL3;
1905 break;
1906 case 3:
1907 if (!is_a64(env) && !arm_is_el3_or_mon(env)) {
1908 r = CP_ACCESS_TRAP_EL3;
1909 }
1910 break;
1911 default:
1912 g_assert_not_reached();
1913 }
1914 }
1915
1916 if (r == CP_ACCESS_TRAP_EL3 && !arm_el_is_aa64(env, 3)) {
1917 r = CP_ACCESS_TRAP;
1918 }
1919 return r;
1920}
1921
1922static CPAccessResult gicv3_dir_access(CPUARMState *env,
1923 const ARMCPRegInfo *ri, bool isread)
1924{
1925 GICv3CPUState *cs = icc_cs_from_env(env);
1926
1927 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_TDIR) &&
1928 arm_current_el(env) == 1 && !arm_is_secure_below_el3(env)) {
1929
1930 return CP_ACCESS_TRAP_EL2;
1931 }
1932
1933 return gicv3_irqfiq_access(env, ri, isread);
1934}
1935
1936static CPAccessResult gicv3_sgi_access(CPUARMState *env,
1937 const ARMCPRegInfo *ri, bool isread)
1938{
1939 if ((arm_hcr_el2_imo(env) || arm_hcr_el2_fmo(env)) &&
1940 arm_current_el(env) == 1 && !arm_is_secure_below_el3(env)) {
1941
1942 return CP_ACCESS_TRAP_EL2;
1943 }
1944
1945 return gicv3_irqfiq_access(env, ri, isread);
1946}
1947
1948static CPAccessResult gicv3_fiq_access(CPUARMState *env,
1949 const ARMCPRegInfo *ri, bool isread)
1950{
1951 CPAccessResult r = CP_ACCESS_OK;
1952 GICv3CPUState *cs = icc_cs_from_env(env);
1953 int el = arm_current_el(env);
1954
1955 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_TALL0) &&
1956 el == 1 && !arm_is_secure_below_el3(env)) {
1957
1958 return CP_ACCESS_TRAP_EL2;
1959 }
1960
1961 if (env->cp15.scr_el3 & SCR_FIQ) {
1962 switch (el) {
1963 case 1:
1964 if (arm_is_secure_below_el3(env) || !arm_hcr_el2_fmo(env)) {
1965 r = CP_ACCESS_TRAP_EL3;
1966 }
1967 break;
1968 case 2:
1969 r = CP_ACCESS_TRAP_EL3;
1970 break;
1971 case 3:
1972 if (!is_a64(env) && !arm_is_el3_or_mon(env)) {
1973 r = CP_ACCESS_TRAP_EL3;
1974 }
1975 break;
1976 default:
1977 g_assert_not_reached();
1978 }
1979 }
1980
1981 if (r == CP_ACCESS_TRAP_EL3 && !arm_el_is_aa64(env, 3)) {
1982 r = CP_ACCESS_TRAP;
1983 }
1984 return r;
1985}
1986
1987static CPAccessResult gicv3_irq_access(CPUARMState *env,
1988 const ARMCPRegInfo *ri, bool isread)
1989{
1990 CPAccessResult r = CP_ACCESS_OK;
1991 GICv3CPUState *cs = icc_cs_from_env(env);
1992 int el = arm_current_el(env);
1993
1994 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_TALL1) &&
1995 el == 1 && !arm_is_secure_below_el3(env)) {
1996
1997 return CP_ACCESS_TRAP_EL2;
1998 }
1999
2000 if (env->cp15.scr_el3 & SCR_IRQ) {
2001 switch (el) {
2002 case 1:
2003 if (arm_is_secure_below_el3(env) || !arm_hcr_el2_imo(env)) {
2004 r = CP_ACCESS_TRAP_EL3;
2005 }
2006 break;
2007 case 2:
2008 r = CP_ACCESS_TRAP_EL3;
2009 break;
2010 case 3:
2011 if (!is_a64(env) && !arm_is_el3_or_mon(env)) {
2012 r = CP_ACCESS_TRAP_EL3;
2013 }
2014 break;
2015 default:
2016 g_assert_not_reached();
2017 }
2018 }
2019
2020 if (r == CP_ACCESS_TRAP_EL3 && !arm_el_is_aa64(env, 3)) {
2021 r = CP_ACCESS_TRAP;
2022 }
2023 return r;
2024}
2025
2026static void icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2027{
2028 GICv3CPUState *cs = icc_cs_from_env(env);
2029
2030 cs->icc_ctlr_el1[GICV3_S] = ICC_CTLR_EL1_A3V |
2031 (1 << ICC_CTLR_EL1_IDBITS_SHIFT) |
2032 (7 << ICC_CTLR_EL1_PRIBITS_SHIFT);
2033 cs->icc_ctlr_el1[GICV3_NS] = ICC_CTLR_EL1_A3V |
2034 (1 << ICC_CTLR_EL1_IDBITS_SHIFT) |
2035 (7 << ICC_CTLR_EL1_PRIBITS_SHIFT);
2036 cs->icc_pmr_el1 = 0;
2037 cs->icc_bpr[GICV3_G0] = GIC_MIN_BPR;
2038 cs->icc_bpr[GICV3_G1] = GIC_MIN_BPR;
2039 cs->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR_NS;
2040 memset(cs->icc_apr, 0, sizeof(cs->icc_apr));
2041 memset(cs->icc_igrpen, 0, sizeof(cs->icc_igrpen));
2042 cs->icc_ctlr_el3 = ICC_CTLR_EL3_NDS | ICC_CTLR_EL3_A3V |
2043 (1 << ICC_CTLR_EL3_IDBITS_SHIFT) |
2044 (7 << ICC_CTLR_EL3_PRIBITS_SHIFT);
2045
2046 memset(cs->ich_apr, 0, sizeof(cs->ich_apr));
2047 cs->ich_hcr_el2 = 0;
2048 memset(cs->ich_lr_el2, 0, sizeof(cs->ich_lr_el2));
2049 cs->ich_vmcr_el2 = ICH_VMCR_EL2_VFIQEN |
2050 ((icv_min_vbpr(cs) + 1) << ICH_VMCR_EL2_VBPR1_SHIFT) |
2051 (icv_min_vbpr(cs) << ICH_VMCR_EL2_VBPR0_SHIFT);
2052}
2053
2054static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
2055 { .name = "ICC_PMR_EL1", .state = ARM_CP_STATE_BOTH,
2056 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 6, .opc2 = 0,
2057 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2058 .access = PL1_RW, .accessfn = gicv3_irqfiq_access,
2059 .readfn = icc_pmr_read,
2060 .writefn = icc_pmr_write,
2061
2062
2063
2064
2065 .resetfn = icc_reset,
2066 },
2067 { .name = "ICC_IAR0_EL1", .state = ARM_CP_STATE_BOTH,
2068 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 0,
2069 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2070 .access = PL1_R, .accessfn = gicv3_fiq_access,
2071 .readfn = icc_iar0_read,
2072 },
2073 { .name = "ICC_EOIR0_EL1", .state = ARM_CP_STATE_BOTH,
2074 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 1,
2075 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2076 .access = PL1_W, .accessfn = gicv3_fiq_access,
2077 .writefn = icc_eoir_write,
2078 },
2079 { .name = "ICC_HPPIR0_EL1", .state = ARM_CP_STATE_BOTH,
2080 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 2,
2081 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2082 .access = PL1_R, .accessfn = gicv3_fiq_access,
2083 .readfn = icc_hppir0_read,
2084 },
2085 { .name = "ICC_BPR0_EL1", .state = ARM_CP_STATE_BOTH,
2086 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 3,
2087 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2088 .access = PL1_RW, .accessfn = gicv3_fiq_access,
2089 .readfn = icc_bpr_read,
2090 .writefn = icc_bpr_write,
2091 },
2092 { .name = "ICC_AP0R0_EL1", .state = ARM_CP_STATE_BOTH,
2093 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 4,
2094 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2095 .access = PL1_RW, .accessfn = gicv3_fiq_access,
2096 .readfn = icc_ap_read,
2097 .writefn = icc_ap_write,
2098 },
2099 { .name = "ICC_AP0R1_EL1", .state = ARM_CP_STATE_BOTH,
2100 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 5,
2101 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2102 .access = PL1_RW, .accessfn = gicv3_fiq_access,
2103 .readfn = icc_ap_read,
2104 .writefn = icc_ap_write,
2105 },
2106 { .name = "ICC_AP0R2_EL1", .state = ARM_CP_STATE_BOTH,
2107 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 6,
2108 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2109 .access = PL1_RW, .accessfn = gicv3_fiq_access,
2110 .readfn = icc_ap_read,
2111 .writefn = icc_ap_write,
2112 },
2113 { .name = "ICC_AP0R3_EL1", .state = ARM_CP_STATE_BOTH,
2114 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 7,
2115 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2116 .access = PL1_RW, .accessfn = gicv3_fiq_access,
2117 .readfn = icc_ap_read,
2118 .writefn = icc_ap_write,
2119 },
2120
2121 { .name = "ICC_AP1R0_EL1", .state = ARM_CP_STATE_BOTH,
2122 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 0,
2123 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2124 .access = PL1_RW, .accessfn = gicv3_irq_access,
2125 .readfn = icc_ap_read,
2126 .writefn = icc_ap_write,
2127 },
2128 { .name = "ICC_AP1R1_EL1", .state = ARM_CP_STATE_BOTH,
2129 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 1,
2130 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2131 .access = PL1_RW, .accessfn = gicv3_irq_access,
2132 .readfn = icc_ap_read,
2133 .writefn = icc_ap_write,
2134 },
2135 { .name = "ICC_AP1R2_EL1", .state = ARM_CP_STATE_BOTH,
2136 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 2,
2137 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2138 .access = PL1_RW, .accessfn = gicv3_irq_access,
2139 .readfn = icc_ap_read,
2140 .writefn = icc_ap_write,
2141 },
2142 { .name = "ICC_AP1R3_EL1", .state = ARM_CP_STATE_BOTH,
2143 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 3,
2144 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2145 .access = PL1_RW, .accessfn = gicv3_irq_access,
2146 .readfn = icc_ap_read,
2147 .writefn = icc_ap_write,
2148 },
2149 { .name = "ICC_DIR_EL1", .state = ARM_CP_STATE_BOTH,
2150 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 1,
2151 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2152 .access = PL1_W, .accessfn = gicv3_dir_access,
2153 .writefn = icc_dir_write,
2154 },
2155 { .name = "ICC_RPR_EL1", .state = ARM_CP_STATE_BOTH,
2156 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 3,
2157 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2158 .access = PL1_R, .accessfn = gicv3_irqfiq_access,
2159 .readfn = icc_rpr_read,
2160 },
2161 { .name = "ICC_SGI1R_EL1", .state = ARM_CP_STATE_AA64,
2162 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 5,
2163 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2164 .access = PL1_W, .accessfn = gicv3_sgi_access,
2165 .writefn = icc_sgi1r_write,
2166 },
2167 { .name = "ICC_SGI1R",
2168 .cp = 15, .opc1 = 0, .crm = 12,
2169 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_RAW,
2170 .access = PL1_W, .accessfn = gicv3_sgi_access,
2171 .writefn = icc_sgi1r_write,
2172 },
2173 { .name = "ICC_ASGI1R_EL1", .state = ARM_CP_STATE_AA64,
2174 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 6,
2175 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2176 .access = PL1_W, .accessfn = gicv3_sgi_access,
2177 .writefn = icc_asgi1r_write,
2178 },
2179 { .name = "ICC_ASGI1R",
2180 .cp = 15, .opc1 = 1, .crm = 12,
2181 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_RAW,
2182 .access = PL1_W, .accessfn = gicv3_sgi_access,
2183 .writefn = icc_asgi1r_write,
2184 },
2185 { .name = "ICC_SGI0R_EL1", .state = ARM_CP_STATE_AA64,
2186 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 7,
2187 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2188 .access = PL1_W, .accessfn = gicv3_sgi_access,
2189 .writefn = icc_sgi0r_write,
2190 },
2191 { .name = "ICC_SGI0R",
2192 .cp = 15, .opc1 = 2, .crm = 12,
2193 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_RAW,
2194 .access = PL1_W, .accessfn = gicv3_sgi_access,
2195 .writefn = icc_sgi0r_write,
2196 },
2197 { .name = "ICC_IAR1_EL1", .state = ARM_CP_STATE_BOTH,
2198 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 0,
2199 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2200 .access = PL1_R, .accessfn = gicv3_irq_access,
2201 .readfn = icc_iar1_read,
2202 },
2203 { .name = "ICC_EOIR1_EL1", .state = ARM_CP_STATE_BOTH,
2204 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 1,
2205 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2206 .access = PL1_W, .accessfn = gicv3_irq_access,
2207 .writefn = icc_eoir_write,
2208 },
2209 { .name = "ICC_HPPIR1_EL1", .state = ARM_CP_STATE_BOTH,
2210 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 2,
2211 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2212 .access = PL1_R, .accessfn = gicv3_irq_access,
2213 .readfn = icc_hppir1_read,
2214 },
2215
2216 { .name = "ICC_BPR1_EL1", .state = ARM_CP_STATE_BOTH,
2217 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 3,
2218 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2219 .access = PL1_RW, .accessfn = gicv3_irq_access,
2220 .readfn = icc_bpr_read,
2221 .writefn = icc_bpr_write,
2222 },
2223
2224 { .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH,
2225 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4,
2226 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2227 .access = PL1_RW, .accessfn = gicv3_irqfiq_access,
2228 .readfn = icc_ctlr_el1_read,
2229 .writefn = icc_ctlr_el1_write,
2230 },
2231 { .name = "ICC_SRE_EL1", .state = ARM_CP_STATE_BOTH,
2232 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 5,
2233 .type = ARM_CP_NO_RAW | ARM_CP_CONST,
2234 .access = PL1_RW,
2235
2236
2237
2238
2239
2240 .resetvalue = 0x7,
2241 },
2242 { .name = "ICC_IGRPEN0_EL1", .state = ARM_CP_STATE_BOTH,
2243 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 6,
2244 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2245 .access = PL1_RW, .accessfn = gicv3_fiq_access,
2246 .readfn = icc_igrpen_read,
2247 .writefn = icc_igrpen_write,
2248 },
2249
2250 { .name = "ICC_IGRPEN1_EL1", .state = ARM_CP_STATE_BOTH,
2251 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 7,
2252 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2253 .access = PL1_RW, .accessfn = gicv3_irq_access,
2254 .readfn = icc_igrpen_read,
2255 .writefn = icc_igrpen_write,
2256 },
2257 { .name = "ICC_SRE_EL2", .state = ARM_CP_STATE_BOTH,
2258 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 5,
2259 .type = ARM_CP_NO_RAW | ARM_CP_CONST,
2260 .access = PL2_RW,
2261
2262
2263
2264 .resetvalue = 0xf,
2265 },
2266 { .name = "ICC_CTLR_EL3", .state = ARM_CP_STATE_BOTH,
2267 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 12, .opc2 = 4,
2268 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2269 .access = PL3_RW,
2270 .readfn = icc_ctlr_el3_read,
2271 .writefn = icc_ctlr_el3_write,
2272 },
2273 { .name = "ICC_SRE_EL3", .state = ARM_CP_STATE_BOTH,
2274 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 12, .opc2 = 5,
2275 .type = ARM_CP_NO_RAW | ARM_CP_CONST,
2276 .access = PL3_RW,
2277
2278
2279
2280 .resetvalue = 0xf,
2281 },
2282 { .name = "ICC_IGRPEN1_EL3", .state = ARM_CP_STATE_BOTH,
2283 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 12, .opc2 = 7,
2284 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2285 .access = PL3_RW,
2286 .readfn = icc_igrpen1_el3_read,
2287 .writefn = icc_igrpen1_el3_write,
2288 },
2289 REGINFO_SENTINEL
2290};
2291
2292static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2293{
2294 GICv3CPUState *cs = icc_cs_from_env(env);
2295 int regno = ri->opc2 & 3;
2296 int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
2297 uint64_t value;
2298
2299 value = cs->ich_apr[grp][regno];
2300 trace_gicv3_ich_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
2301 return value;
2302}
2303
2304static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2305 uint64_t value)
2306{
2307 GICv3CPUState *cs = icc_cs_from_env(env);
2308 int regno = ri->opc2 & 3;
2309 int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
2310
2311 trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
2312
2313 cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU;
2314 gicv3_cpuif_virt_update(cs);
2315}
2316
2317static uint64_t ich_hcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2318{
2319 GICv3CPUState *cs = icc_cs_from_env(env);
2320 uint64_t value = cs->ich_hcr_el2;
2321
2322 trace_gicv3_ich_hcr_read(gicv3_redist_affid(cs), value);
2323 return value;
2324}
2325
2326static void ich_hcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2327 uint64_t value)
2328{
2329 GICv3CPUState *cs = icc_cs_from_env(env);
2330
2331 trace_gicv3_ich_hcr_write(gicv3_redist_affid(cs), value);
2332
2333 value &= ICH_HCR_EL2_EN | ICH_HCR_EL2_UIE | ICH_HCR_EL2_LRENPIE |
2334 ICH_HCR_EL2_NPIE | ICH_HCR_EL2_VGRP0EIE | ICH_HCR_EL2_VGRP0DIE |
2335 ICH_HCR_EL2_VGRP1EIE | ICH_HCR_EL2_VGRP1DIE | ICH_HCR_EL2_TC |
2336 ICH_HCR_EL2_TALL0 | ICH_HCR_EL2_TALL1 | ICH_HCR_EL2_TSEI |
2337 ICH_HCR_EL2_TDIR | ICH_HCR_EL2_EOICOUNT_MASK;
2338
2339 cs->ich_hcr_el2 = value;
2340 gicv3_cpuif_virt_update(cs);
2341}
2342
2343static uint64_t ich_vmcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2344{
2345 GICv3CPUState *cs = icc_cs_from_env(env);
2346 uint64_t value = cs->ich_vmcr_el2;
2347
2348 trace_gicv3_ich_vmcr_read(gicv3_redist_affid(cs), value);
2349 return value;
2350}
2351
2352static void ich_vmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2353 uint64_t value)
2354{
2355 GICv3CPUState *cs = icc_cs_from_env(env);
2356
2357 trace_gicv3_ich_vmcr_write(gicv3_redist_affid(cs), value);
2358
2359 value &= ICH_VMCR_EL2_VENG0 | ICH_VMCR_EL2_VENG1 | ICH_VMCR_EL2_VCBPR |
2360 ICH_VMCR_EL2_VEOIM | ICH_VMCR_EL2_VBPR1_MASK |
2361 ICH_VMCR_EL2_VBPR0_MASK | ICH_VMCR_EL2_VPMR_MASK;
2362 value |= ICH_VMCR_EL2_VFIQEN;
2363
2364 cs->ich_vmcr_el2 = value;
2365
2366
2367
2368 write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G0));
2369 write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G1));
2370
2371 gicv3_cpuif_virt_update(cs);
2372}
2373
2374static uint64_t ich_lr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2375{
2376 GICv3CPUState *cs = icc_cs_from_env(env);
2377 int regno = ri->opc2 | ((ri->crm & 1) << 3);
2378 uint64_t value;
2379
2380
2381
2382
2383
2384
2385 if (ri->state == ARM_CP_STATE_AA32) {
2386 if (ri->crm >= 14) {
2387 value = extract64(cs->ich_lr_el2[regno], 32, 32);
2388 trace_gicv3_ich_lrc_read(regno, gicv3_redist_affid(cs), value);
2389 } else {
2390 value = extract64(cs->ich_lr_el2[regno], 0, 32);
2391 trace_gicv3_ich_lr32_read(regno, gicv3_redist_affid(cs), value);
2392 }
2393 } else {
2394 value = cs->ich_lr_el2[regno];
2395 trace_gicv3_ich_lr_read(regno, gicv3_redist_affid(cs), value);
2396 }
2397
2398 return value;
2399}
2400
2401static void ich_lr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2402 uint64_t value)
2403{
2404 GICv3CPUState *cs = icc_cs_from_env(env);
2405 int regno = ri->opc2 | ((ri->crm & 1) << 3);
2406
2407
2408
2409
2410
2411
2412 if (ri->state == ARM_CP_STATE_AA32) {
2413 if (ri->crm >= 14) {
2414 trace_gicv3_ich_lrc_write(regno, gicv3_redist_affid(cs), value);
2415 value = deposit64(cs->ich_lr_el2[regno], 32, 32, value);
2416 } else {
2417 trace_gicv3_ich_lr32_write(regno, gicv3_redist_affid(cs), value);
2418 value = deposit64(cs->ich_lr_el2[regno], 0, 32, value);
2419 }
2420 } else {
2421 trace_gicv3_ich_lr_write(regno, gicv3_redist_affid(cs), value);
2422 }
2423
2424
2425 if (cs->vpribits < 8) {
2426 value = deposit64(value, ICH_LR_EL2_PRIORITY_SHIFT,
2427 8 - cs->vpribits, 0);
2428 }
2429
2430 cs->ich_lr_el2[regno] = value;
2431 gicv3_cpuif_virt_update(cs);
2432}
2433
2434static uint64_t ich_vtr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2435{
2436 GICv3CPUState *cs = icc_cs_from_env(env);
2437 uint64_t value;
2438
2439 value = ((cs->num_list_regs - 1) << ICH_VTR_EL2_LISTREGS_SHIFT)
2440 | ICH_VTR_EL2_TDS | ICH_VTR_EL2_NV4 | ICH_VTR_EL2_A3V
2441 | (1 << ICH_VTR_EL2_IDBITS_SHIFT)
2442 | ((cs->vprebits - 1) << ICH_VTR_EL2_PREBITS_SHIFT)
2443 | ((cs->vpribits - 1) << ICH_VTR_EL2_PRIBITS_SHIFT);
2444
2445 trace_gicv3_ich_vtr_read(gicv3_redist_affid(cs), value);
2446 return value;
2447}
2448
2449static uint64_t ich_misr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2450{
2451 GICv3CPUState *cs = icc_cs_from_env(env);
2452 uint64_t value = maintenance_interrupt_state(cs);
2453
2454 trace_gicv3_ich_misr_read(gicv3_redist_affid(cs), value);
2455 return value;
2456}
2457
2458static uint64_t ich_eisr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2459{
2460 GICv3CPUState *cs = icc_cs_from_env(env);
2461 uint64_t value = eoi_maintenance_interrupt_state(cs, NULL);
2462
2463 trace_gicv3_ich_eisr_read(gicv3_redist_affid(cs), value);
2464 return value;
2465}
2466
2467static uint64_t ich_elrsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2468{
2469 GICv3CPUState *cs = icc_cs_from_env(env);
2470 uint64_t value = 0;
2471 int i;
2472
2473 for (i = 0; i < cs->num_list_regs; i++) {
2474 uint64_t lr = cs->ich_lr_el2[i];
2475
2476 if ((lr & ICH_LR_EL2_STATE_MASK) == 0 &&
2477 ((lr & ICH_LR_EL2_HW) != 0 || (lr & ICH_LR_EL2_EOI) == 0)) {
2478 value |= (1 << i);
2479 }
2480 }
2481
2482 trace_gicv3_ich_elrsr_read(gicv3_redist_affid(cs), value);
2483 return value;
2484}
2485
2486static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = {
2487 { .name = "ICH_AP0R0_EL2", .state = ARM_CP_STATE_BOTH,
2488 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 8, .opc2 = 0,
2489 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2490 .access = PL2_RW,
2491 .readfn = ich_ap_read,
2492 .writefn = ich_ap_write,
2493 },
2494 { .name = "ICH_AP1R0_EL2", .state = ARM_CP_STATE_BOTH,
2495 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 0,
2496 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2497 .access = PL2_RW,
2498 .readfn = ich_ap_read,
2499 .writefn = ich_ap_write,
2500 },
2501 { .name = "ICH_HCR_EL2", .state = ARM_CP_STATE_BOTH,
2502 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 0,
2503 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2504 .access = PL2_RW,
2505 .readfn = ich_hcr_read,
2506 .writefn = ich_hcr_write,
2507 },
2508 { .name = "ICH_VTR_EL2", .state = ARM_CP_STATE_BOTH,
2509 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 1,
2510 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2511 .access = PL2_R,
2512 .readfn = ich_vtr_read,
2513 },
2514 { .name = "ICH_MISR_EL2", .state = ARM_CP_STATE_BOTH,
2515 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 2,
2516 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2517 .access = PL2_R,
2518 .readfn = ich_misr_read,
2519 },
2520 { .name = "ICH_EISR_EL2", .state = ARM_CP_STATE_BOTH,
2521 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 3,
2522 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2523 .access = PL2_R,
2524 .readfn = ich_eisr_read,
2525 },
2526 { .name = "ICH_ELRSR_EL2", .state = ARM_CP_STATE_BOTH,
2527 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 5,
2528 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2529 .access = PL2_R,
2530 .readfn = ich_elrsr_read,
2531 },
2532 { .name = "ICH_VMCR_EL2", .state = ARM_CP_STATE_BOTH,
2533 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 7,
2534 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2535 .access = PL2_RW,
2536 .readfn = ich_vmcr_read,
2537 .writefn = ich_vmcr_write,
2538 },
2539 REGINFO_SENTINEL
2540};
2541
2542static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = {
2543 { .name = "ICH_AP0R1_EL2", .state = ARM_CP_STATE_BOTH,
2544 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 8, .opc2 = 1,
2545 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2546 .access = PL2_RW,
2547 .readfn = ich_ap_read,
2548 .writefn = ich_ap_write,
2549 },
2550 { .name = "ICH_AP1R1_EL2", .state = ARM_CP_STATE_BOTH,
2551 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 1,
2552 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2553 .access = PL2_RW,
2554 .readfn = ich_ap_read,
2555 .writefn = ich_ap_write,
2556 },
2557 REGINFO_SENTINEL
2558};
2559
2560static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = {
2561 { .name = "ICH_AP0R2_EL2", .state = ARM_CP_STATE_BOTH,
2562 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 8, .opc2 = 2,
2563 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2564 .access = PL2_RW,
2565 .readfn = ich_ap_read,
2566 .writefn = ich_ap_write,
2567 },
2568 { .name = "ICH_AP0R3_EL2", .state = ARM_CP_STATE_BOTH,
2569 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 8, .opc2 = 3,
2570 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2571 .access = PL2_RW,
2572 .readfn = ich_ap_read,
2573 .writefn = ich_ap_write,
2574 },
2575 { .name = "ICH_AP1R2_EL2", .state = ARM_CP_STATE_BOTH,
2576 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 2,
2577 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2578 .access = PL2_RW,
2579 .readfn = ich_ap_read,
2580 .writefn = ich_ap_write,
2581 },
2582 { .name = "ICH_AP1R3_EL2", .state = ARM_CP_STATE_BOTH,
2583 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 3,
2584 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2585 .access = PL2_RW,
2586 .readfn = ich_ap_read,
2587 .writefn = ich_ap_write,
2588 },
2589 REGINFO_SENTINEL
2590};
2591
2592static void gicv3_cpuif_el_change_hook(ARMCPU *cpu, void *opaque)
2593{
2594 GICv3CPUState *cs = opaque;
2595
2596 gicv3_cpuif_update(cs);
2597}
2598
2599void gicv3_init_cpuif(GICv3State *s)
2600{
2601
2602
2603
2604 int i;
2605
2606 for (i = 0; i < s->num_cpu; i++) {
2607 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));
2608 GICv3CPUState *cs = &s->cpu[i];
2609
2610
2611
2612
2613
2614
2615
2616
2617 define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
2618 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)
2619 && cpu->gic_num_lrs) {
2620 int j;
2621
2622 cs->maintenance_irq = cpu->gicv3_maintenance_interrupt;
2623
2624 cs->num_list_regs = cpu->gic_num_lrs;
2625 cs->vpribits = cpu->gic_vpribits;
2626 cs->vprebits = cpu->gic_vprebits;
2627
2628
2629
2630
2631
2632 g_assert(cs->vprebits <= cs->vpribits);
2633 g_assert(cs->vprebits >= 5 && cs->vprebits <= 7);
2634 g_assert(cs->vpribits >= 5 && cs->vpribits <= 8);
2635
2636 define_arm_cp_regs(cpu, gicv3_cpuif_hcr_reginfo);
2637
2638 for (j = 0; j < cs->num_list_regs; j++) {
2639
2640
2641
2642
2643 ARMCPRegInfo lr_regset[] = {
2644 { .name = "ICH_LRn_EL2", .state = ARM_CP_STATE_BOTH,
2645 .opc0 = 3, .opc1 = 4, .crn = 12,
2646 .crm = 12 + (j >> 3), .opc2 = j & 7,
2647 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2648 .access = PL2_RW,
2649 .readfn = ich_lr_read,
2650 .writefn = ich_lr_write,
2651 },
2652 { .name = "ICH_LRCn_EL2", .state = ARM_CP_STATE_AA32,
2653 .cp = 15, .opc1 = 4, .crn = 12,
2654 .crm = 14 + (j >> 3), .opc2 = j & 7,
2655 .type = ARM_CP_IO | ARM_CP_NO_RAW,
2656 .access = PL2_RW,
2657 .readfn = ich_lr_read,
2658 .writefn = ich_lr_write,
2659 },
2660 REGINFO_SENTINEL
2661 };
2662 define_arm_cp_regs(cpu, lr_regset);
2663 }
2664 if (cs->vprebits >= 6) {
2665 define_arm_cp_regs(cpu, gicv3_cpuif_ich_apxr1_reginfo);
2666 }
2667 if (cs->vprebits == 7) {
2668 define_arm_cp_regs(cpu, gicv3_cpuif_ich_apxr23_reginfo);
2669 }
2670 }
2671 arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, cs);
2672 }
2673}
2674