1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22#include "qemu/osdep.h"
23#include "hw/pci/pci_ids.h"
24#include "hw/pci/msi.h"
25#include "hw/pci/pcie.h"
26#include "hw/pci/pcie_port.h"
27#include "qapi/error.h"
28
29#define PCI_DEVICE_ID_TI_XIO3130D 0x8233
30#define XIO3130_REVISION 0x1
31#define XIO3130_MSI_OFFSET 0x70
32#define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT
33#define XIO3130_MSI_NR_VECTOR 1
34#define XIO3130_SSVID_OFFSET 0x80
35#define XIO3130_SSVID_SVID 0
36#define XIO3130_SSVID_SSID 0
37#define XIO3130_EXP_OFFSET 0x90
38#define XIO3130_AER_OFFSET 0x100
39
40static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address,
41 uint32_t val, int len)
42{
43 pci_bridge_write_config(d, address, val, len);
44 pcie_cap_flr_write_config(d, address, val, len);
45 pcie_cap_slot_write_config(d, address, val, len);
46 pcie_aer_write_config(d, address, val, len);
47}
48
49static void xio3130_downstream_reset(DeviceState *qdev)
50{
51 PCIDevice *d = PCI_DEVICE(qdev);
52
53 pcie_cap_deverr_reset(d);
54 pcie_cap_slot_reset(d);
55 pcie_cap_arifwd_reset(d);
56 pci_bridge_reset(qdev);
57}
58
59static void xio3130_downstream_realize(PCIDevice *d, Error **errp)
60{
61 PCIEPort *p = PCIE_PORT(d);
62 PCIESlot *s = PCIE_SLOT(d);
63 int rc;
64
65 pci_bridge_initfn(d, TYPE_PCIE_BUS);
66 pcie_port_init_reg(d);
67
68 rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
69 XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
70 XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT,
71 errp);
72 if (rc < 0) {
73 assert(rc == -ENOTSUP);
74 goto err_bridge;
75 }
76
77 rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
78 XIO3130_SSVID_SVID, XIO3130_SSVID_SSID,
79 errp);
80 if (rc < 0) {
81 goto err_bridge;
82 }
83
84 rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM,
85 p->port, errp);
86 if (rc < 0) {
87 goto err_msi;
88 }
89 pcie_cap_flr_init(d);
90 pcie_cap_deverr_init(d);
91 pcie_cap_slot_init(d, s->slot);
92 pcie_cap_arifwd_init(d);
93
94 pcie_chassis_create(s->chassis);
95 rc = pcie_chassis_add_slot(s);
96 if (rc < 0) {
97 error_setg(errp, "Can't add chassis slot, error %d", rc);
98 goto err_pcie_cap;
99 }
100
101 rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET,
102 PCI_ERR_SIZEOF, errp);
103 if (rc < 0) {
104 goto err;
105 }
106
107 return;
108
109err:
110 pcie_chassis_del_slot(s);
111err_pcie_cap:
112 pcie_cap_exit(d);
113err_msi:
114 msi_uninit(d);
115err_bridge:
116 pci_bridge_exitfn(d);
117}
118
119static void xio3130_downstream_exitfn(PCIDevice *d)
120{
121 PCIESlot *s = PCIE_SLOT(d);
122
123 pcie_aer_exit(d);
124 pcie_chassis_del_slot(s);
125 pcie_cap_exit(d);
126 msi_uninit(d);
127 pci_bridge_exitfn(d);
128}
129
130static Property xio3130_downstream_props[] = {
131 DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
132 QEMU_PCIE_SLTCAP_PCP_BITNR, true),
133 DEFINE_PROP_END_OF_LIST()
134};
135
136static const VMStateDescription vmstate_xio3130_downstream = {
137 .name = "xio3130-express-downstream-port",
138 .priority = MIG_PRI_PCI_BUS,
139 .version_id = 1,
140 .minimum_version_id = 1,
141 .post_load = pcie_cap_slot_post_load,
142 .fields = (VMStateField[]) {
143 VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
144 VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
145 PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
146 VMSTATE_END_OF_LIST()
147 }
148};
149
150static void xio3130_downstream_class_init(ObjectClass *klass, void *data)
151{
152 DeviceClass *dc = DEVICE_CLASS(klass);
153 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
154
155 k->is_bridge = 1;
156 k->config_write = xio3130_downstream_write_config;
157 k->realize = xio3130_downstream_realize;
158 k->exit = xio3130_downstream_exitfn;
159 k->vendor_id = PCI_VENDOR_ID_TI;
160 k->device_id = PCI_DEVICE_ID_TI_XIO3130D;
161 k->revision = XIO3130_REVISION;
162 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
163 dc->desc = "TI X3130 Downstream Port of PCI Express Switch";
164 dc->reset = xio3130_downstream_reset;
165 dc->vmsd = &vmstate_xio3130_downstream;
166 dc->props = xio3130_downstream_props;
167}
168
169static const TypeInfo xio3130_downstream_info = {
170 .name = "xio3130-downstream",
171 .parent = TYPE_PCIE_SLOT,
172 .class_init = xio3130_downstream_class_init,
173 .interfaces = (InterfaceInfo[]) {
174 { INTERFACE_PCIE_DEVICE },
175 { }
176 },
177};
178
179static void xio3130_downstream_register_types(void)
180{
181 type_register_static(&xio3130_downstream_info);
182}
183
184type_init(xio3130_downstream_register_types)
185