1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26#include "qemu/osdep.h"
27#include "qemu/units.h"
28#include "qapi/error.h"
29#include "hw/hw.h"
30#include "hw/pci/pci.h"
31#include "hw/pci/pci_bus.h"
32#include "hw/pci/pci_host.h"
33#include "hw/i386/pc.h"
34#include "hw/loader.h"
35#include "hw/or-irq.h"
36#include "exec/address-spaces.h"
37#include "elf.h"
38
39#define TYPE_RAVEN_PCI_DEVICE "raven"
40#define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost"
41
42#define RAVEN_PCI_DEVICE(obj) \
43 OBJECT_CHECK(RavenPCIState, (obj), TYPE_RAVEN_PCI_DEVICE)
44
45typedef struct RavenPCIState {
46 PCIDevice dev;
47
48 uint32_t elf_machine;
49 char *bios_name;
50 MemoryRegion bios;
51} RavenPCIState;
52
53#define RAVEN_PCI_HOST_BRIDGE(obj) \
54 OBJECT_CHECK(PREPPCIState, (obj), TYPE_RAVEN_PCI_HOST_BRIDGE)
55
56typedef struct PRePPCIState {
57 PCIHostState parent_obj;
58
59 qemu_or_irq *or_irq;
60 qemu_irq pci_irqs[PCI_NUM_PINS];
61 PCIBus pci_bus;
62 AddressSpace pci_io_as;
63 MemoryRegion pci_io;
64 MemoryRegion pci_io_non_contiguous;
65 MemoryRegion pci_memory;
66 MemoryRegion pci_intack;
67 MemoryRegion bm;
68 MemoryRegion bm_ram_alias;
69 MemoryRegion bm_pci_memory_alias;
70 AddressSpace bm_as;
71 RavenPCIState pci_dev;
72
73 int contiguous_map;
74 bool is_legacy_prep;
75} PREPPCIState;
76
77#define BIOS_SIZE (1 * MiB)
78
79static inline uint32_t raven_pci_io_config(hwaddr addr)
80{
81 int i;
82
83 for (i = 0; i < 11; i++) {
84 if ((addr & (1 << (11 + i))) != 0) {
85 break;
86 }
87 }
88 return (addr & 0x7ff) | (i << 11);
89}
90
91static void raven_pci_io_write(void *opaque, hwaddr addr,
92 uint64_t val, unsigned int size)
93{
94 PREPPCIState *s = opaque;
95 PCIHostState *phb = PCI_HOST_BRIDGE(s);
96 pci_data_write(phb->bus, raven_pci_io_config(addr), val, size);
97}
98
99static uint64_t raven_pci_io_read(void *opaque, hwaddr addr,
100 unsigned int size)
101{
102 PREPPCIState *s = opaque;
103 PCIHostState *phb = PCI_HOST_BRIDGE(s);
104 return pci_data_read(phb->bus, raven_pci_io_config(addr), size);
105}
106
107static const MemoryRegionOps raven_pci_io_ops = {
108 .read = raven_pci_io_read,
109 .write = raven_pci_io_write,
110 .endianness = DEVICE_LITTLE_ENDIAN,
111};
112
113static uint64_t raven_intack_read(void *opaque, hwaddr addr,
114 unsigned int size)
115{
116 return pic_read_irq(isa_pic);
117}
118
119static const MemoryRegionOps raven_intack_ops = {
120 .read = raven_intack_read,
121 .valid = {
122 .max_access_size = 1,
123 },
124};
125
126static inline hwaddr raven_io_address(PREPPCIState *s,
127 hwaddr addr)
128{
129 if (s->contiguous_map == 0) {
130
131 addr &= 0xFFFF;
132 } else {
133
134 addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
135 }
136
137
138
139 return addr;
140}
141
142static uint64_t raven_io_read(void *opaque, hwaddr addr,
143 unsigned int size)
144{
145 PREPPCIState *s = opaque;
146 uint8_t buf[4];
147
148 addr = raven_io_address(s, addr);
149 address_space_read(&s->pci_io_as, addr + 0x80000000,
150 MEMTXATTRS_UNSPECIFIED, buf, size);
151
152 if (size == 1) {
153 return buf[0];
154 } else if (size == 2) {
155 return lduw_le_p(buf);
156 } else if (size == 4) {
157 return ldl_le_p(buf);
158 } else {
159 g_assert_not_reached();
160 }
161}
162
163static void raven_io_write(void *opaque, hwaddr addr,
164 uint64_t val, unsigned int size)
165{
166 PREPPCIState *s = opaque;
167 uint8_t buf[4];
168
169 addr = raven_io_address(s, addr);
170
171 if (size == 1) {
172 buf[0] = val;
173 } else if (size == 2) {
174 stw_le_p(buf, val);
175 } else if (size == 4) {
176 stl_le_p(buf, val);
177 } else {
178 g_assert_not_reached();
179 }
180
181 address_space_write(&s->pci_io_as, addr + 0x80000000,
182 MEMTXATTRS_UNSPECIFIED, buf, size);
183}
184
185static const MemoryRegionOps raven_io_ops = {
186 .read = raven_io_read,
187 .write = raven_io_write,
188 .endianness = DEVICE_LITTLE_ENDIAN,
189 .impl.max_access_size = 4,
190 .valid.unaligned = true,
191};
192
193static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
194{
195 return (irq_num + (pci_dev->devfn >> 3)) & 1;
196}
197
198static void raven_set_irq(void *opaque, int irq_num, int level)
199{
200 PREPPCIState *s = opaque;
201
202 qemu_set_irq(s->pci_irqs[irq_num], level);
203}
204
205static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
206 int devfn)
207{
208 PREPPCIState *s = opaque;
209
210 return &s->bm_as;
211}
212
213static void raven_change_gpio(void *opaque, int n, int level)
214{
215 PREPPCIState *s = opaque;
216
217 s->contiguous_map = level;
218}
219
220static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
221{
222 SysBusDevice *dev = SYS_BUS_DEVICE(d);
223 PCIHostState *h = PCI_HOST_BRIDGE(dev);
224 PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev);
225 MemoryRegion *address_space_mem = get_system_memory();
226 int i;
227
228 if (s->is_legacy_prep) {
229 for (i = 0; i < PCI_NUM_PINS; i++) {
230 sysbus_init_irq(dev, &s->pci_irqs[i]);
231 }
232 } else {
233
234
235 s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ));
236 object_property_set_int(OBJECT(s->or_irq), PCI_NUM_PINS, "num-lines",
237 &error_fatal);
238 object_property_set_bool(OBJECT(s->or_irq), true, "realized",
239 &error_fatal);
240 sysbus_init_irq(dev, &s->or_irq->out_irq);
241
242 for (i = 0; i < PCI_NUM_PINS; i++) {
243 s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i);
244 }
245 }
246
247 qdev_init_gpio_in(d, raven_change_gpio, 1);
248
249 pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s, PCI_NUM_PINS);
250
251 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s,
252 "pci-conf-idx", 4);
253 memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem);
254
255 memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s,
256 "pci-conf-data", 4);
257 memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem);
258
259 memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s,
260 "pciio", 0x00400000);
261 memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
262
263 memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s,
264 "pci-intack", 1);
265 memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack);
266
267
268 object_property_set_bool(OBJECT(&s->pci_bus), true, "realized", errp);
269 object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp);
270}
271
272static void raven_pcihost_initfn(Object *obj)
273{
274 PCIHostState *h = PCI_HOST_BRIDGE(obj);
275 PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj);
276 MemoryRegion *address_space_mem = get_system_memory();
277 DeviceState *pci_dev;
278
279 memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000);
280 memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s,
281 "pci-io-non-contiguous", 0x00800000);
282 memory_region_init(&s->pci_memory, obj, "pci-memory", 0x3f000000);
283 address_space_init(&s->pci_io_as, &s->pci_io, "raven-io");
284
285
286 memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io);
287 memory_region_add_subregion_overlap(address_space_mem, 0x80000000,
288 &s->pci_io_non_contiguous, 1);
289 memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);
290 pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
291 &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
292
293
294 memory_region_init(&s->bm, obj, "bm-raven", UINT32_MAX);
295 memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory",
296 &s->pci_memory, 0,
297 memory_region_size(&s->pci_memory));
298 memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system",
299 get_system_memory(), 0, 0x80000000);
300 memory_region_add_subregion(&s->bm, 0 , &s->bm_pci_memory_alias);
301 memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias);
302 address_space_init(&s->bm_as, &s->bm, "raven-bm");
303 pci_setup_iommu(&s->pci_bus, raven_pcihost_set_iommu, s);
304
305 h->bus = &s->pci_bus;
306
307 object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE);
308 pci_dev = DEVICE(&s->pci_dev);
309 qdev_set_parent_bus(pci_dev, BUS(&s->pci_bus));
310 object_property_set_int(OBJECT(&s->pci_dev), PCI_DEVFN(0, 0), "addr",
311 NULL);
312 qdev_prop_set_bit(pci_dev, "multifunction", false);
313}
314
315static void raven_realize(PCIDevice *d, Error **errp)
316{
317 RavenPCIState *s = RAVEN_PCI_DEVICE(d);
318 char *filename;
319 int bios_size = -1;
320
321 d->config[0x0C] = 0x08;
322 d->config[0x0D] = 0x10;
323 d->config[0x34] = 0x00;
324
325 memory_region_init_ram_nomigrate(&s->bios, OBJECT(s), "bios", BIOS_SIZE,
326 &error_fatal);
327 memory_region_set_readonly(&s->bios, true);
328 memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE),
329 &s->bios);
330 if (s->bios_name) {
331 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name);
332 if (filename) {
333 if (s->elf_machine != EM_NONE) {
334 bios_size = load_elf(filename, NULL, NULL, NULL,
335 NULL, NULL, 1, s->elf_machine, 0, 0);
336 }
337 if (bios_size < 0) {
338 bios_size = get_image_size(filename);
339 if (bios_size > 0 && bios_size <= BIOS_SIZE) {
340 hwaddr bios_addr;
341 bios_size = (bios_size + 0xfff) & ~0xfff;
342 bios_addr = (uint32_t)(-BIOS_SIZE);
343 bios_size = load_image_targphys(filename, bios_addr,
344 bios_size);
345 }
346 }
347 }
348 g_free(filename);
349 if (bios_size < 0 || bios_size > BIOS_SIZE) {
350 memory_region_del_subregion(get_system_memory(), &s->bios);
351 error_setg(errp, "Could not load bios image '%s'", s->bios_name);
352 return;
353 }
354 }
355
356 vmstate_register_ram_global(&s->bios);
357}
358
359static const VMStateDescription vmstate_raven = {
360 .name = "raven",
361 .version_id = 0,
362 .minimum_version_id = 0,
363 .fields = (VMStateField[]) {
364 VMSTATE_PCI_DEVICE(dev, RavenPCIState),
365 VMSTATE_END_OF_LIST()
366 },
367};
368
369static void raven_class_init(ObjectClass *klass, void *data)
370{
371 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
372 DeviceClass *dc = DEVICE_CLASS(klass);
373
374 k->realize = raven_realize;
375 k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
376 k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN;
377 k->revision = 0x00;
378 k->class_id = PCI_CLASS_BRIDGE_HOST;
379 dc->desc = "PReP Host Bridge - Motorola Raven";
380 dc->vmsd = &vmstate_raven;
381
382
383
384
385 dc->user_creatable = false;
386}
387
388static const TypeInfo raven_info = {
389 .name = TYPE_RAVEN_PCI_DEVICE,
390 .parent = TYPE_PCI_DEVICE,
391 .instance_size = sizeof(RavenPCIState),
392 .class_init = raven_class_init,
393 .interfaces = (InterfaceInfo[]) {
394 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
395 { },
396 },
397};
398
399static Property raven_pcihost_properties[] = {
400 DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
401 EM_NONE),
402 DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),
403
404 DEFINE_PROP_BOOL("is-legacy-prep", PREPPCIState, is_legacy_prep,
405 false),
406 DEFINE_PROP_END_OF_LIST()
407};
408
409static void raven_pcihost_class_init(ObjectClass *klass, void *data)
410{
411 DeviceClass *dc = DEVICE_CLASS(klass);
412
413 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
414 dc->realize = raven_pcihost_realizefn;
415 dc->props = raven_pcihost_properties;
416 dc->fw_name = "pci";
417}
418
419static const TypeInfo raven_pcihost_info = {
420 .name = TYPE_RAVEN_PCI_HOST_BRIDGE,
421 .parent = TYPE_PCI_HOST_BRIDGE,
422 .instance_size = sizeof(PREPPCIState),
423 .instance_init = raven_pcihost_initfn,
424 .class_init = raven_pcihost_class_init,
425};
426
427static void raven_register_types(void)
428{
429 type_register_static(&raven_pcihost_info);
430 type_register_static(&raven_info);
431}
432
433type_init(raven_register_types)
434
