qemu/hw/pci/pci_bridge.c
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   1/*
   2 * QEMU PCI bus manager
   3 *
   4 * Copyright (c) 2004 Fabrice Bellard
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to dea
   8
   9 * in the Software without restriction, including without limitation the rights
  10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11 * copies of the Software, and to permit persons to whom the Software is
  12 * furnished to do so, subject to the following conditions:
  13 *
  14 * The above copyright notice and this permission notice shall be included in
  15 * all copies or substantial portions of the Software.
  16 *
  17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM
  22
  23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24 * THE SOFTWARE.
  25 */
  26/*
  27 * split out from pci.c
  28 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
  29 *                    VA Linux Systems Japan K.K.
  30 */
  31
  32#include "qemu/osdep.h"
  33#include "hw/pci/pci_bridge.h"
  34#include "hw/pci/pci_bus.h"
  35#include "qemu/range.h"
  36#include "qapi/error.h"
  37
  38/* PCI bridge subsystem vendor ID helper functions */
  39#define PCI_SSVID_SIZEOF        8
  40#define PCI_SSVID_SVID          4
  41#define PCI_SSVID_SSID          6
  42
  43int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
  44                          uint16_t svid, uint16_t ssid,
  45                          Error **errp)
  46{
  47    int pos;
  48
  49    pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset,
  50                             PCI_SSVID_SIZEOF, errp);
  51    if (pos < 0) {
  52        return pos;
  53    }
  54
  55    pci_set_word(dev->config + pos + PCI_SSVID_SVID, svid);
  56    pci_set_word(dev->config + pos + PCI_SSVID_SSID, ssid);
  57    return pos;
  58}
  59
  60/* Accessor function to get parent bridge device from pci bus. */
  61PCIDevice *pci_bridge_get_device(PCIBus *bus)
  62{
  63    return bus->parent_dev;
  64}
  65
  66/* Accessor function to get secondary bus from pci-to-pci bridge device */
  67PCIBus *pci_bridge_get_sec_bus(PCIBridge *br)
  68{
  69    return &br->sec_bus;
  70}
  71
  72static uint32_t pci_config_get_io_base(const PCIDevice *d,
  73                                       uint32_t base, uint32_t base_upper16)
  74{
  75    uint32_t val;
  76
  77    val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
  78    if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
  79        val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
  80    }
  81    return val;
  82}
  83
  84static pcibus_t pci_config_get_memory_base(const PCIDevice *d, uint32_t base)
  85{
  86    return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
  87        << 16;
  88}
  89
  90static pcibus_t pci_config_get_pref_base(const PCIDevice *d,
  91                                         uint32_t base, uint32_t upper)
  92{
  93    pcibus_t tmp;
  94    pcibus_t val;
  95
  96    tmp = (pcibus_t)pci_get_word(d->config + base);
  97    val = (tmp & PCI_PREF_RANGE_MASK) << 16;
  98    if (tmp & PCI_PREF_RANGE_TYPE_64) {
  99        val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
 100    }
 101    return val;
 102}
 103
 104/* accessor function to get bridge filtering base address */
 105pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type)
 106{
 107    pcibus_t base;
 108    if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 109        base = pci_config_get_io_base(bridge,
 110                                      PCI_IO_BASE, PCI_IO_BASE_UPPER16);
 111    } else {
 112        if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 113            base = pci_config_get_pref_base(
 114                bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
 115        } else {
 116            base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
 117        }
 118    }
 119
 120    return base;
 121}
 122
 123/* accessor function to get bridge filtering limit */
 124pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type)
 125{
 126    pcibus_t limit;
 127    if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 128        limit = pci_config_get_io_base(bridge,
 129                                      PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
 130        limit |= 0xfff;         /* PCI bridge spec 3.2.5.6. */
 131    } else {
 132        if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 133            limit = pci_config_get_pref_base(
 134                bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
 135        } else {
 136            limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
 137        }
 138        limit |= 0xfffff;       /* PCI bridge spec 3.2.5.{1, 8}. */
 139    }
 140    return limit;
 141}
 142
 143static void pci_bridge_init_alias(PCIBridge *bridge, MemoryRegion *alias,
 144                                  uint8_t type, const char *name,
 145                                  MemoryRegion *space,
 146                                  MemoryRegion *parent_space,
 147                                  bool enabled)
 148{
 149    PCIDevice *bridge_dev = PCI_DEVICE(bridge);
 150    pcibus_t base = pci_bridge_get_base(bridge_dev, type);
 151    pcibus_t limit = pci_bridge_get_limit(bridge_dev, type);
 152    /* TODO: this doesn't handle base = 0 limit = 2^64 - 1 correctly.
 153     * Apparently no way to do this with existing memory APIs. */
 154    pcibus_t size = enabled && limit >= base ? limit + 1 - base : 0;
 155
 156    memory_region_init_alias(alias, OBJECT(bridge), name, space, base, size);
 157    memory_region_add_subregion_overlap(parent_space, base, alias, 1);
 158}
 159
 160static void pci_bridge_init_vga_aliases(PCIBridge *br, PCIBus *parent,
 161                                        MemoryRegion *alias_vga)
 162{
 163    PCIDevice *pd = PCI_DEVICE(br);
 164    uint16_t brctl = pci_get_word(pd->config + PCI_BRIDGE_CONTROL);
 165
 166    memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_LO], OBJECT(br),
 167                             "pci_bridge_vga_io_lo", &br->address_space_io,
 168                             QEMU_PCI_VGA_IO_LO_BASE, QEMU_PCI_VGA_IO_LO_SIZE);
 169    memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_HI], OBJECT(br),
 170                             "pci_bridge_vga_io_hi", &br->address_space_io,
 171                             QEMU_PCI_VGA_IO_HI_BASE, QEMU_PCI_VGA_IO_HI_SIZE);
 172    memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_MEM], OBJECT(br),
 173                             "pci_bridge_vga_mem", &br->address_space_mem,
 174                             QEMU_PCI_VGA_MEM_BASE, QEMU_PCI_VGA_MEM_SIZE);
 175
 176    if (brctl & PCI_BRIDGE_CTL_VGA) {
 177        pci_register_vga(pd, &alias_vga[QEMU_PCI_VGA_MEM],
 178                         &alias_vga[QEMU_PCI_VGA_IO_LO],
 179                         &alias_vga[QEMU_PCI_VGA_IO_HI]);
 180    }
 181}
 182
 183static PCIBridgeWindows *pci_bridge_region_init(PCIBridge *br)
 184{
 185    PCIDevice *pd = PCI_DEVICE(br);
 186    PCIBus *parent = pci_get_bus(pd);
 187    PCIBridgeWindows *w = g_new(PCIBridgeWindows, 1);
 188    uint16_t cmd = pci_get_word(pd->config + PCI_COMMAND);
 189
 190    pci_bridge_init_alias(br, &w->alias_pref_mem,
 191                          PCI_BASE_ADDRESS_MEM_PREFETCH,
 192                          "pci_bridge_pref_mem",
 193                          &br->address_space_mem,
 194                          parent->address_space_mem,
 195                          cmd & PCI_COMMAND_MEMORY);
 196    pci_bridge_init_alias(br, &w->alias_mem,
 197                          PCI_BASE_ADDRESS_SPACE_MEMORY,
 198                          "pci_bridge_mem",
 199                          &br->address_space_mem,
 200                          parent->address_space_mem,
 201                          cmd & PCI_COMMAND_MEMORY);
 202    pci_bridge_init_alias(br, &w->alias_io,
 203                          PCI_BASE_ADDRESS_SPACE_IO,
 204                          "pci_bridge_io",
 205                          &br->address_space_io,
 206                          parent->address_space_io,
 207                          cmd & PCI_COMMAND_IO);
 208
 209    pci_bridge_init_vga_aliases(br, parent, w->alias_vga);
 210
 211    return w;
 212}
 213
 214static void pci_bridge_region_del(PCIBridge *br, PCIBridgeWindows *w)
 215{
 216    PCIDevice *pd = PCI_DEVICE(br);
 217    PCIBus *parent = pci_get_bus(pd);
 218
 219    memory_region_del_subregion(parent->address_space_io, &w->alias_io);
 220    memory_region_del_subregion(parent->address_space_mem, &w->alias_mem);
 221    memory_region_del_subregion(parent->address_space_mem, &w->alias_pref_mem);
 222    pci_unregister_vga(pd);
 223}
 224
 225static void pci_bridge_region_cleanup(PCIBridge *br, PCIBridgeWindows *w)
 226{
 227    object_unparent(OBJECT(&w->alias_io));
 228    object_unparent(OBJECT(&w->alias_mem));
 229    object_unparent(OBJECT(&w->alias_pref_mem));
 230    object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_IO_LO]));
 231    object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_IO_HI]));
 232    object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_MEM]));
 233    g_free(w);
 234}
 235
 236void pci_bridge_update_mappings(PCIBridge *br)
 237{
 238    PCIBridgeWindows *w = br->windows;
 239
 240    /* Make updates atomic to: handle the case of one VCPU updating the bridge
 241     * while another accesses an unaffected region. */
 242    memory_region_transaction_begin();
 243    pci_bridge_region_del(br, br->windows);
 244    br->windows = pci_bridge_region_init(br);
 245    memory_region_transaction_commit();
 246    pci_bridge_region_cleanup(br, w);
 247}
 248
 249/* default write_config function for PCI-to-PCI bridge */
 250void pci_bridge_write_config(PCIDevice *d,
 251                             uint32_t address, uint32_t val, int len)
 252{
 253    PCIBridge *s = PCI_BRIDGE(d);
 254    uint16_t oldctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
 255    uint16_t newctl;
 256
 257    pci_default_write_config(d, address, val, len);
 258
 259    if (ranges_overlap(address, len, PCI_COMMAND, 2) ||
 260
 261        /* io base/limit */
 262        ranges_overlap(address, len, PCI_IO_BASE, 2) ||
 263
 264        /* memory base/limit, prefetchable base/limit and
 265           io base/limit upper 16 */
 266        ranges_overlap(address, len, PCI_MEMORY_BASE, 20) ||
 267
 268        /* vga enable */
 269        ranges_overlap(address, len, PCI_BRIDGE_CONTROL, 2)) {
 270        pci_bridge_update_mappings(s);
 271    }
 272
 273    newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
 274    if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) {
 275        /* Trigger hot reset on 0->1 transition. */
 276        qbus_reset_all(&s->sec_bus.qbus);
 277    }
 278}
 279
 280void pci_bridge_disable_base_limit(PCIDevice *dev)
 281{
 282    uint8_t *conf = dev->config;
 283
 284    pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
 285                               PCI_IO_RANGE_MASK & 0xff);
 286    pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
 287                                 PCI_IO_RANGE_MASK & 0xff);
 288    pci_word_test_and_set_mask(conf + PCI_MEMORY_BASE,
 289                               PCI_MEMORY_RANGE_MASK & 0xffff);
 290    pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
 291                                 PCI_MEMORY_RANGE_MASK & 0xffff);
 292    pci_word_test_and_set_mask(conf + PCI_PREF_MEMORY_BASE,
 293                               PCI_PREF_RANGE_MASK & 0xffff);
 294    pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
 295                                 PCI_PREF_RANGE_MASK & 0xffff);
 296    pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
 297    pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);
 298}
 299
 300/* reset bridge specific configuration registers */
 301void pci_bridge_reset(DeviceState *qdev)
 302{
 303    PCIDevice *dev = PCI_DEVICE(qdev);
 304    uint8_t *conf = dev->config;
 305
 306    conf[PCI_PRIMARY_BUS] = 0;
 307    conf[PCI_SECONDARY_BUS] = 0;
 308    conf[PCI_SUBORDINATE_BUS] = 0;
 309    conf[PCI_SEC_LATENCY_TIMER] = 0;
 310
 311    /*
 312     * the default values for base/limit registers aren't specified
 313     * in the PCI-to-PCI-bridge spec. So we don't thouch them here.
 314     * Each implementation can override it.
 315     * typical implementation does
 316     * zero base/limit registers or
 317     * disable forwarding: pci_bridge_disable_base_limit()
 318     * If disable forwarding is wanted, call pci_bridge_disable_base_limit()
 319     * after this function.
 320     */
 321    pci_byte_test_and_clear_mask(conf + PCI_IO_BASE,
 322                                 PCI_IO_RANGE_MASK & 0xff);
 323    pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
 324                                 PCI_IO_RANGE_MASK & 0xff);
 325    pci_word_test_and_clear_mask(conf + PCI_MEMORY_BASE,
 326                                 PCI_MEMORY_RANGE_MASK & 0xffff);
 327    pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
 328                                 PCI_MEMORY_RANGE_MASK & 0xffff);
 329    pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_BASE,
 330                                 PCI_PREF_RANGE_MASK & 0xffff);
 331    pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
 332                                 PCI_PREF_RANGE_MASK & 0xffff);
 333    pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
 334    pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);
 335
 336    pci_set_word(conf + PCI_BRIDGE_CONTROL, 0);
 337}
 338
 339/* default qdev initialization function for PCI-to-PCI bridge */
 340void pci_bridge_initfn(PCIDevice *dev, const char *typename)
 341{
 342    PCIBus *parent = pci_get_bus(dev);
 343    PCIBridge *br = PCI_BRIDGE(dev);
 344    PCIBus *sec_bus = &br->sec_bus;
 345
 346    pci_word_test_and_set_mask(dev->config + PCI_STATUS,
 347                               PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
 348
 349    /*
 350     * TODO: We implement VGA Enable in the Bridge Control Register
 351     * therefore per the PCI to PCI bridge spec we must also implement
 352     * VGA Palette Snooping.  When done, set this bit writable:
 353     *
 354     * pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND,
 355     *                            PCI_COMMAND_VGA_PALETTE);
 356     */
 357
 358    pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
 359    dev->config[PCI_HEADER_TYPE] =
 360        (dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
 361        PCI_HEADER_TYPE_BRIDGE;
 362    pci_set_word(dev->config + PCI_SEC_STATUS,
 363                 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
 364
 365    /*
 366     * If we don't specify the name, the bus will be addressed as <id>.0, where
 367     * id is the device id.
 368     * Since PCI Bridge devices have a single bus each, we don't need the index:
 369     * let users address the bus using the device name.
 370     */
 371    if (!br->bus_name && dev->qdev.id && *dev->qdev.id) {
 372            br->bus_name = dev->qdev.id;
 373    }
 374
 375    qbus_create_inplace(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev),
 376                        br->bus_name);
 377    sec_bus->parent_dev = dev;
 378    sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn;
 379    sec_bus->address_space_mem = &br->address_space_mem;
 380    memory_region_init(&br->address_space_mem, OBJECT(br), "pci_bridge_pci", UINT64_MAX);
 381    sec_bus->address_space_io = &br->address_space_io;
 382    memory_region_init(&br->address_space_io, OBJECT(br), "pci_bridge_io",
 383                       UINT32_MAX);
 384    br->windows = pci_bridge_region_init(br);
 385    QLIST_INIT(&sec_bus->child);
 386    QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling);
 387}
 388
 389/* default qdev clean up function for PCI-to-PCI bridge */
 390void pci_bridge_exitfn(PCIDevice *pci_dev)
 391{
 392    PCIBridge *s = PCI_BRIDGE(pci_dev);
 393    assert(QLIST_EMPTY(&s->sec_bus.child));
 394    QLIST_REMOVE(&s->sec_bus, sibling);
 395    pci_bridge_region_del(s, s->windows);
 396    pci_bridge_region_cleanup(s, s->windows);
 397    /* object_unparent() is called automatically during device deletion */
 398}
 399
 400/*
 401 * before qdev initialization(qdev_init()), this function sets bus_name and
 402 * map_irq callback which are necessary for pci_bridge_initfn() to
 403 * initialize bus.
 404 */
 405void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
 406                        pci_map_irq_fn map_irq)
 407{
 408    br->map_irq = map_irq;
 409    br->bus_name = bus_name;
 410}
 411
 412
 413int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
 414                                     PCIResReserve res_reserve, Error **errp)
 415{
 416    if (res_reserve.mem_pref_32 != (uint64_t)-1 &&
 417        res_reserve.mem_pref_64 != (uint64_t)-1) {
 418        error_setg(errp,
 419                   "PCI resource reserve cap: PREF32 and PREF64 conflict");
 420        return -EINVAL;
 421    }
 422
 423    if (res_reserve.mem_non_pref != (uint64_t)-1 &&
 424        res_reserve.mem_non_pref >= (1ULL << 32)) {
 425        error_setg(errp,
 426                   "PCI resource reserve cap: mem-reserve must be less than 4G");
 427        return -EINVAL;
 428    }
 429
 430    if (res_reserve.mem_pref_32 != (uint64_t)-1 &&
 431        res_reserve.mem_pref_32 >= (1ULL << 32)) {
 432        error_setg(errp,
 433                   "PCI resource reserve cap: pref32-reserve  must be less than 4G");
 434        return -EINVAL;
 435    }
 436
 437    if (res_reserve.bus == (uint32_t)-1 &&
 438        res_reserve.io == (uint64_t)-1 &&
 439        res_reserve.mem_non_pref == (uint64_t)-1 &&
 440        res_reserve.mem_pref_32 == (uint64_t)-1 &&
 441        res_reserve.mem_pref_64 == (uint64_t)-1) {
 442        return 0;
 443    }
 444
 445    size_t cap_len = sizeof(PCIBridgeQemuCap);
 446    PCIBridgeQemuCap cap = {
 447            .len = cap_len,
 448            .type = REDHAT_PCI_CAP_RESOURCE_RESERVE,
 449            .bus_res = res_reserve.bus,
 450            .io = res_reserve.io,
 451            .mem = res_reserve.mem_non_pref,
 452            .mem_pref_32 = res_reserve.mem_pref_32,
 453            .mem_pref_64 = res_reserve.mem_pref_64
 454    };
 455
 456    int offset = pci_add_capability(dev, PCI_CAP_ID_VNDR,
 457                                    cap_offset, cap_len, errp);
 458    if (offset < 0) {
 459        return offset;
 460    }
 461
 462    memcpy(dev->config + offset + PCI_CAP_FLAGS,
 463           (char *)&cap + PCI_CAP_FLAGS,
 464           cap_len - PCI_CAP_FLAGS);
 465    return 0;
 466}
 467
 468static const TypeInfo pci_bridge_type_info = {
 469    .name = TYPE_PCI_BRIDGE,
 470    .parent = TYPE_PCI_DEVICE,
 471    .instance_size = sizeof(PCIBridge),
 472    .abstract = true,
 473};
 474
 475static void pci_bridge_register_types(void)
 476{
 477    type_register_static(&pci_bridge_type_info);
 478}
 479
 480type_init(pci_bridge_register_types)
 481