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16#include "qemu/osdep.h"
17#include "qapi/error.h"
18#include "hw/hw.h"
19#include "hw/pci/pci.h"
20#include "hw/pci/pci_ids.h"
21#include "hw/pci/msi.h"
22#include "hw/pci/msix.h"
23#include "hw/qdev-core.h"
24#include "hw/qdev-properties.h"
25#include "cpu.h"
26#include "trace.h"
27
28#include "../rdma_rm.h"
29#include "../rdma_backend.h"
30#include "../rdma_utils.h"
31
32#include <infiniband/verbs.h>
33#include "pvrdma.h"
34#include "standard-headers/rdma/vmw_pvrdma-abi.h"
35#include "standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h"
36#include "pvrdma_qp_ops.h"
37
38static Property pvrdma_dev_properties[] = {
39 DEFINE_PROP_STRING("backend-dev", PVRDMADev, backend_device_name),
40 DEFINE_PROP_UINT8("backend-port", PVRDMADev, backend_port_num, 1),
41 DEFINE_PROP_UINT8("backend-gid-idx", PVRDMADev, backend_gid_idx, 0),
42 DEFINE_PROP_UINT64("dev-caps-max-mr-size", PVRDMADev, dev_attr.max_mr_size,
43 MAX_MR_SIZE),
44 DEFINE_PROP_INT32("dev-caps-max-qp", PVRDMADev, dev_attr.max_qp, MAX_QP),
45 DEFINE_PROP_INT32("dev-caps-max-sge", PVRDMADev, dev_attr.max_sge, MAX_SGE),
46 DEFINE_PROP_INT32("dev-caps-max-cq", PVRDMADev, dev_attr.max_cq, MAX_CQ),
47 DEFINE_PROP_INT32("dev-caps-max-mr", PVRDMADev, dev_attr.max_mr, MAX_MR),
48 DEFINE_PROP_INT32("dev-caps-max-pd", PVRDMADev, dev_attr.max_pd, MAX_PD),
49 DEFINE_PROP_INT32("dev-caps-qp-rd-atom", PVRDMADev, dev_attr.max_qp_rd_atom,
50 MAX_QP_RD_ATOM),
51 DEFINE_PROP_INT32("dev-caps-max-qp-init-rd-atom", PVRDMADev,
52 dev_attr.max_qp_init_rd_atom, MAX_QP_INIT_RD_ATOM),
53 DEFINE_PROP_INT32("dev-caps-max-ah", PVRDMADev, dev_attr.max_ah, MAX_AH),
54 DEFINE_PROP_END_OF_LIST(),
55};
56
57static void free_dev_ring(PCIDevice *pci_dev, PvrdmaRing *ring,
58 void *ring_state)
59{
60 pvrdma_ring_free(ring);
61 rdma_pci_dma_unmap(pci_dev, ring_state, TARGET_PAGE_SIZE);
62}
63
64static int init_dev_ring(PvrdmaRing *ring, struct pvrdma_ring **ring_state,
65 const char *name, PCIDevice *pci_dev,
66 dma_addr_t dir_addr, uint32_t num_pages)
67{
68 uint64_t *dir, *tbl;
69 int rc = 0;
70
71 pr_dbg("Initializing device ring %s\n", name);
72 pr_dbg("pdir_dma=0x%llx\n", (long long unsigned int)dir_addr);
73 pr_dbg("num_pages=%d\n", num_pages);
74 dir = rdma_pci_dma_map(pci_dev, dir_addr, TARGET_PAGE_SIZE);
75 if (!dir) {
76 pr_err("Failed to map to page directory\n");
77 rc = -ENOMEM;
78 goto out;
79 }
80 tbl = rdma_pci_dma_map(pci_dev, dir[0], TARGET_PAGE_SIZE);
81 if (!tbl) {
82 pr_err("Failed to map to page table\n");
83 rc = -ENOMEM;
84 goto out_free_dir;
85 }
86
87 *ring_state = rdma_pci_dma_map(pci_dev, tbl[0], TARGET_PAGE_SIZE);
88 if (!*ring_state) {
89 pr_err("Failed to map to ring state\n");
90 rc = -ENOMEM;
91 goto out_free_tbl;
92 }
93
94 (*ring_state)++;
95 rc = pvrdma_ring_init(ring, name, pci_dev,
96 (struct pvrdma_ring *)*ring_state,
97 (num_pages - 1) * TARGET_PAGE_SIZE /
98 sizeof(struct pvrdma_cqne),
99 sizeof(struct pvrdma_cqne),
100 (dma_addr_t *)&tbl[1], (dma_addr_t)num_pages - 1);
101 if (rc) {
102 pr_err("Failed to initialize ring\n");
103 rc = -ENOMEM;
104 goto out_free_ring_state;
105 }
106
107 goto out_free_tbl;
108
109out_free_ring_state:
110 rdma_pci_dma_unmap(pci_dev, *ring_state, TARGET_PAGE_SIZE);
111
112out_free_tbl:
113 rdma_pci_dma_unmap(pci_dev, tbl, TARGET_PAGE_SIZE);
114
115out_free_dir:
116 rdma_pci_dma_unmap(pci_dev, dir, TARGET_PAGE_SIZE);
117
118out:
119 return rc;
120}
121
122static void free_dsr(PVRDMADev *dev)
123{
124 PCIDevice *pci_dev = PCI_DEVICE(dev);
125
126 if (!dev->dsr_info.dsr) {
127 return;
128 }
129
130 free_dev_ring(pci_dev, &dev->dsr_info.async,
131 dev->dsr_info.async_ring_state);
132
133 free_dev_ring(pci_dev, &dev->dsr_info.cq, dev->dsr_info.cq_ring_state);
134
135 rdma_pci_dma_unmap(pci_dev, dev->dsr_info.req,
136 sizeof(union pvrdma_cmd_req));
137
138 rdma_pci_dma_unmap(pci_dev, dev->dsr_info.rsp,
139 sizeof(union pvrdma_cmd_resp));
140
141 rdma_pci_dma_unmap(pci_dev, dev->dsr_info.dsr,
142 sizeof(struct pvrdma_device_shared_region));
143
144 dev->dsr_info.dsr = NULL;
145}
146
147static int load_dsr(PVRDMADev *dev)
148{
149 int rc = 0;
150 PCIDevice *pci_dev = PCI_DEVICE(dev);
151 DSRInfo *dsr_info;
152 struct pvrdma_device_shared_region *dsr;
153
154 free_dsr(dev);
155
156
157 pr_dbg("dsr_dma=0x%llx\n", (long long unsigned int)dev->dsr_info.dma);
158 dev->dsr_info.dsr = rdma_pci_dma_map(pci_dev, dev->dsr_info.dma,
159 sizeof(struct pvrdma_device_shared_region));
160 if (!dev->dsr_info.dsr) {
161 pr_err("Failed to map to DSR\n");
162 rc = -ENOMEM;
163 goto out;
164 }
165
166
167 dsr_info = &dev->dsr_info;
168 dsr = dsr_info->dsr;
169
170
171 pr_dbg("cmd_dma=0x%llx\n", (long long unsigned int)dsr->cmd_slot_dma);
172 dsr_info->req = rdma_pci_dma_map(pci_dev, dsr->cmd_slot_dma,
173 sizeof(union pvrdma_cmd_req));
174 if (!dsr_info->req) {
175 pr_err("Failed to map to command slot address\n");
176 rc = -ENOMEM;
177 goto out_free_dsr;
178 }
179
180
181 pr_dbg("rsp_dma=0x%llx\n", (long long unsigned int)dsr->resp_slot_dma);
182 dsr_info->rsp = rdma_pci_dma_map(pci_dev, dsr->resp_slot_dma,
183 sizeof(union pvrdma_cmd_resp));
184 if (!dsr_info->rsp) {
185 pr_err("Failed to map to response slot address\n");
186 rc = -ENOMEM;
187 goto out_free_req;
188 }
189
190
191 rc = init_dev_ring(&dsr_info->cq, &dsr_info->cq_ring_state, "dev_cq",
192 pci_dev, dsr->cq_ring_pages.pdir_dma,
193 dsr->cq_ring_pages.num_pages);
194 if (rc) {
195 pr_err("Failed to map to initialize CQ ring\n");
196 rc = -ENOMEM;
197 goto out_free_rsp;
198 }
199
200
201 rc = init_dev_ring(&dsr_info->async, &dsr_info->async_ring_state,
202 "dev_async", pci_dev, dsr->async_ring_pages.pdir_dma,
203 dsr->async_ring_pages.num_pages);
204 if (rc) {
205 pr_err("Failed to map to initialize event ring\n");
206 rc = -ENOMEM;
207 goto out_free_rsp;
208 }
209
210 goto out;
211
212out_free_rsp:
213 rdma_pci_dma_unmap(pci_dev, dsr_info->rsp, sizeof(union pvrdma_cmd_resp));
214
215out_free_req:
216 rdma_pci_dma_unmap(pci_dev, dsr_info->req, sizeof(union pvrdma_cmd_req));
217
218out_free_dsr:
219 rdma_pci_dma_unmap(pci_dev, dsr_info->dsr,
220 sizeof(struct pvrdma_device_shared_region));
221 dsr_info->dsr = NULL;
222
223out:
224 return rc;
225}
226
227static void init_dsr_dev_caps(PVRDMADev *dev)
228{
229 struct pvrdma_device_shared_region *dsr;
230
231 if (dev->dsr_info.dsr == NULL) {
232 pr_err("Can't initialized DSR\n");
233 return;
234 }
235
236 dsr = dev->dsr_info.dsr;
237
238 dsr->caps.fw_ver = PVRDMA_FW_VERSION;
239 pr_dbg("fw_ver=0x%" PRIx64 "\n", dsr->caps.fw_ver);
240
241 dsr->caps.mode = PVRDMA_DEVICE_MODE_ROCE;
242 pr_dbg("mode=%d\n", dsr->caps.mode);
243
244 dsr->caps.gid_types |= PVRDMA_GID_TYPE_FLAG_ROCE_V1;
245 pr_dbg("gid_types=0x%x\n", dsr->caps.gid_types);
246
247 dsr->caps.max_uar = RDMA_BAR2_UAR_SIZE;
248 pr_dbg("max_uar=%d\n", dsr->caps.max_uar);
249
250 dsr->caps.max_mr_size = dev->dev_attr.max_mr_size;
251 dsr->caps.max_qp = dev->dev_attr.max_qp;
252 dsr->caps.max_qp_wr = dev->dev_attr.max_qp_wr;
253 dsr->caps.max_sge = dev->dev_attr.max_sge;
254 dsr->caps.max_cq = dev->dev_attr.max_cq;
255 dsr->caps.max_cqe = dev->dev_attr.max_cqe;
256 dsr->caps.max_mr = dev->dev_attr.max_mr;
257 dsr->caps.max_pd = dev->dev_attr.max_pd;
258 dsr->caps.max_ah = dev->dev_attr.max_ah;
259
260 dsr->caps.gid_tbl_len = MAX_GIDS;
261 pr_dbg("gid_tbl_len=%d\n", dsr->caps.gid_tbl_len);
262
263 dsr->caps.sys_image_guid = 0;
264 pr_dbg("sys_image_guid=%" PRIx64 "\n", dsr->caps.sys_image_guid);
265
266 dsr->caps.node_guid = cpu_to_be64(dev->node_guid);
267 pr_dbg("node_guid=%" PRIx64 "\n", be64_to_cpu(dsr->caps.node_guid));
268
269 dsr->caps.phys_port_cnt = MAX_PORTS;
270 pr_dbg("phys_port_cnt=%d\n", dsr->caps.phys_port_cnt);
271
272 dsr->caps.max_pkeys = MAX_PKEYS;
273 pr_dbg("max_pkeys=%d\n", dsr->caps.max_pkeys);
274
275 pr_dbg("Initialized\n");
276}
277
278static void init_ports(PVRDMADev *dev, Error **errp)
279{
280 int i;
281
282 memset(dev->rdma_dev_res.ports, 0, sizeof(dev->rdma_dev_res.ports));
283
284 for (i = 0; i < MAX_PORTS; i++) {
285 dev->rdma_dev_res.ports[i].state = IBV_PORT_DOWN;
286 }
287}
288
289static void uninit_msix(PCIDevice *pdev, int used_vectors)
290{
291 PVRDMADev *dev = PVRDMA_DEV(pdev);
292 int i;
293
294 for (i = 0; i < used_vectors; i++) {
295 msix_vector_unuse(pdev, i);
296 }
297
298 msix_uninit(pdev, &dev->msix, &dev->msix);
299}
300
301static int init_msix(PCIDevice *pdev, Error **errp)
302{
303 PVRDMADev *dev = PVRDMA_DEV(pdev);
304 int i;
305 int rc;
306
307 rc = msix_init(pdev, RDMA_MAX_INTRS, &dev->msix, RDMA_MSIX_BAR_IDX,
308 RDMA_MSIX_TABLE, &dev->msix, RDMA_MSIX_BAR_IDX,
309 RDMA_MSIX_PBA, 0, NULL);
310
311 if (rc < 0) {
312 error_setg(errp, "Failed to initialize MSI-X");
313 return rc;
314 }
315
316 for (i = 0; i < RDMA_MAX_INTRS; i++) {
317 rc = msix_vector_use(PCI_DEVICE(dev), i);
318 if (rc < 0) {
319 error_setg(errp, "Fail mark MSI-X vector %d", i);
320 uninit_msix(pdev, i);
321 return rc;
322 }
323 }
324
325 return 0;
326}
327
328static void pvrdma_fini(PCIDevice *pdev)
329{
330 PVRDMADev *dev = PVRDMA_DEV(pdev);
331
332 pr_dbg("Closing device %s %x.%x\n", pdev->name, PCI_SLOT(pdev->devfn),
333 PCI_FUNC(pdev->devfn));
334
335 pvrdma_qp_ops_fini();
336
337 rdma_rm_fini(&dev->rdma_dev_res);
338
339 rdma_backend_fini(&dev->backend_dev);
340
341 free_dsr(dev);
342
343 if (msix_enabled(pdev)) {
344 uninit_msix(pdev, RDMA_MAX_INTRS);
345 }
346}
347
348static void pvrdma_stop(PVRDMADev *dev)
349{
350 rdma_backend_stop(&dev->backend_dev);
351}
352
353static void pvrdma_start(PVRDMADev *dev)
354{
355 rdma_backend_start(&dev->backend_dev);
356}
357
358static void activate_device(PVRDMADev *dev)
359{
360 pvrdma_start(dev);
361 set_reg_val(dev, PVRDMA_REG_ERR, 0);
362 pr_dbg("Device activated\n");
363}
364
365static int unquiesce_device(PVRDMADev *dev)
366{
367 pr_dbg("Device unquiesced\n");
368 return 0;
369}
370
371static int reset_device(PVRDMADev *dev)
372{
373 pvrdma_stop(dev);
374
375 pr_dbg("Device reset complete\n");
376
377 return 0;
378}
379
380static uint64_t regs_read(void *opaque, hwaddr addr, unsigned size)
381{
382 PVRDMADev *dev = opaque;
383 uint32_t val;
384
385
386
387 if (get_reg_val(dev, addr, &val)) {
388 pr_dbg("Error trying to read REG value from address 0x%x\n",
389 (uint32_t)addr);
390 return -EINVAL;
391 }
392
393 trace_pvrdma_regs_read(addr, val);
394
395 return val;
396}
397
398static void regs_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
399{
400 PVRDMADev *dev = opaque;
401
402
403
404 if (set_reg_val(dev, addr, val)) {
405 pr_err("Fail to set REG value, addr=0x%" PRIx64 ", val=0x%" PRIx64 "\n",
406 addr, val);
407 return;
408 }
409
410 trace_pvrdma_regs_write(addr, val);
411
412 switch (addr) {
413 case PVRDMA_REG_DSRLOW:
414 dev->dsr_info.dma = val;
415 break;
416 case PVRDMA_REG_DSRHIGH:
417 dev->dsr_info.dma |= val << 32;
418 load_dsr(dev);
419 init_dsr_dev_caps(dev);
420 break;
421 case PVRDMA_REG_CTL:
422 switch (val) {
423 case PVRDMA_DEVICE_CTL_ACTIVATE:
424 activate_device(dev);
425 break;
426 case PVRDMA_DEVICE_CTL_UNQUIESCE:
427 unquiesce_device(dev);
428 break;
429 case PVRDMA_DEVICE_CTL_RESET:
430 reset_device(dev);
431 break;
432 }
433 break;
434 case PVRDMA_REG_IMR:
435 pr_dbg("Interrupt mask=0x%" PRIx64 "\n", val);
436 dev->interrupt_mask = val;
437 break;
438 case PVRDMA_REG_REQUEST:
439 if (val == 0) {
440 execute_command(dev);
441 }
442 break;
443 default:
444 break;
445 }
446}
447
448static const MemoryRegionOps regs_ops = {
449 .read = regs_read,
450 .write = regs_write,
451 .endianness = DEVICE_LITTLE_ENDIAN,
452 .impl = {
453 .min_access_size = sizeof(uint32_t),
454 .max_access_size = sizeof(uint32_t),
455 },
456};
457
458static uint64_t uar_read(void *opaque, hwaddr addr, unsigned size)
459{
460 return 0xffffffff;
461}
462
463static void uar_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
464{
465 PVRDMADev *dev = opaque;
466
467
468
469 switch (addr & 0xFFF) {
470 case PVRDMA_UAR_QP_OFFSET:
471 pr_dbg("UAR QP command, addr=0x%" PRIx64 ", val=0x%" PRIx64 "\n",
472 (uint64_t)addr, val);
473 if (val & PVRDMA_UAR_QP_SEND) {
474 pvrdma_qp_send(dev, val & PVRDMA_UAR_HANDLE_MASK);
475 }
476 if (val & PVRDMA_UAR_QP_RECV) {
477 pvrdma_qp_recv(dev, val & PVRDMA_UAR_HANDLE_MASK);
478 }
479 break;
480 case PVRDMA_UAR_CQ_OFFSET:
481
482 if (val & PVRDMA_UAR_CQ_ARM) {
483 rdma_rm_req_notify_cq(&dev->rdma_dev_res,
484 val & PVRDMA_UAR_HANDLE_MASK,
485 !!(val & PVRDMA_UAR_CQ_ARM_SOL));
486 }
487 if (val & PVRDMA_UAR_CQ_ARM_SOL) {
488 pr_dbg("UAR_CQ_ARM_SOL (%" PRIx64 ")\n",
489 val & PVRDMA_UAR_HANDLE_MASK);
490 }
491 if (val & PVRDMA_UAR_CQ_POLL) {
492 pr_dbg("UAR_CQ_POLL (%" PRIx64 ")\n", val & PVRDMA_UAR_HANDLE_MASK);
493 pvrdma_cq_poll(&dev->rdma_dev_res, val & PVRDMA_UAR_HANDLE_MASK);
494 }
495 break;
496 default:
497 pr_err("Unsupported command, addr=0x%" PRIx64 ", val=0x%" PRIx64 "\n",
498 addr, val);
499 break;
500 }
501}
502
503static const MemoryRegionOps uar_ops = {
504 .read = uar_read,
505 .write = uar_write,
506 .endianness = DEVICE_LITTLE_ENDIAN,
507 .impl = {
508 .min_access_size = sizeof(uint32_t),
509 .max_access_size = sizeof(uint32_t),
510 },
511};
512
513static void init_pci_config(PCIDevice *pdev)
514{
515 pdev->config[PCI_INTERRUPT_PIN] = 1;
516}
517
518static void init_bars(PCIDevice *pdev)
519{
520 PVRDMADev *dev = PVRDMA_DEV(pdev);
521
522
523 memory_region_init(&dev->msix, OBJECT(dev), "pvrdma-msix",
524 RDMA_BAR0_MSIX_SIZE);
525 pci_register_bar(pdev, RDMA_MSIX_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY,
526 &dev->msix);
527
528
529 memset(&dev->regs_data, 0, sizeof(dev->regs_data));
530 memory_region_init_io(&dev->regs, OBJECT(dev), ®s_ops, dev,
531 "pvrdma-regs", sizeof(dev->regs_data));
532 pci_register_bar(pdev, RDMA_REG_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY,
533 &dev->regs);
534
535
536 memset(&dev->uar_data, 0, sizeof(dev->uar_data));
537 memory_region_init_io(&dev->uar, OBJECT(dev), &uar_ops, dev, "rdma-uar",
538 sizeof(dev->uar_data));
539 pci_register_bar(pdev, RDMA_UAR_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY,
540 &dev->uar);
541}
542
543static void init_regs(PCIDevice *pdev)
544{
545 PVRDMADev *dev = PVRDMA_DEV(pdev);
546
547 set_reg_val(dev, PVRDMA_REG_VERSION, PVRDMA_HW_VERSION);
548 set_reg_val(dev, PVRDMA_REG_ERR, 0xFFFF);
549}
550
551static void init_dev_caps(PVRDMADev *dev)
552{
553 size_t pg_tbl_bytes = TARGET_PAGE_SIZE *
554 (TARGET_PAGE_SIZE / sizeof(uint64_t));
555 size_t wr_sz = MAX(sizeof(struct pvrdma_sq_wqe_hdr),
556 sizeof(struct pvrdma_rq_wqe_hdr));
557
558 dev->dev_attr.max_qp_wr = pg_tbl_bytes /
559 (wr_sz + sizeof(struct pvrdma_sge) * MAX_SGE) -
560 TARGET_PAGE_SIZE;
561 pr_dbg("max_qp_wr=%d\n", dev->dev_attr.max_qp_wr);
562
563 dev->dev_attr.max_cqe = pg_tbl_bytes / sizeof(struct pvrdma_cqe) -
564 TARGET_PAGE_SIZE;
565 pr_dbg("max_cqe=%d\n", dev->dev_attr.max_cqe);
566}
567
568static int pvrdma_check_ram_shared(Object *obj, void *opaque)
569{
570 bool *shared = opaque;
571
572 if (object_dynamic_cast(obj, "memory-backend-ram")) {
573 *shared = object_property_get_bool(obj, "share", NULL);
574 }
575
576 return 0;
577}
578
579static void pvrdma_realize(PCIDevice *pdev, Error **errp)
580{
581 int rc = 0;
582 PVRDMADev *dev = PVRDMA_DEV(pdev);
583 Object *memdev_root;
584 bool ram_shared = false;
585
586 init_pr_dbg();
587
588 pr_dbg("Initializing device %s %x.%x\n", pdev->name,
589 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
590
591 if (TARGET_PAGE_SIZE != getpagesize()) {
592 error_setg(errp, "Target page size must be the same as host page size");
593 return;
594 }
595
596 memdev_root = object_resolve_path("/objects", NULL);
597 if (memdev_root) {
598 object_child_foreach(memdev_root, pvrdma_check_ram_shared, &ram_shared);
599 }
600 if (!ram_shared) {
601 error_setg(errp, "Only shared memory backed ram is supported");
602 return;
603 }
604
605 dev->dsr_info.dsr = NULL;
606
607 init_pci_config(pdev);
608
609 init_bars(pdev);
610
611 init_regs(pdev);
612
613 init_dev_caps(dev);
614
615 rc = init_msix(pdev, errp);
616 if (rc) {
617 goto out;
618 }
619
620 rc = rdma_backend_init(&dev->backend_dev, pdev, &dev->rdma_dev_res,
621 dev->backend_device_name, dev->backend_port_num,
622 dev->backend_gid_idx, &dev->dev_attr, errp);
623 if (rc) {
624 goto out;
625 }
626
627 rc = rdma_rm_init(&dev->rdma_dev_res, &dev->dev_attr, errp);
628 if (rc) {
629 goto out;
630 }
631
632 init_ports(dev, errp);
633
634 rc = pvrdma_qp_ops_init();
635 if (rc) {
636 goto out;
637 }
638
639out:
640 if (rc) {
641 pvrdma_fini(pdev);
642 error_append_hint(errp, "Device fail to load\n");
643 }
644}
645
646static void pvrdma_exit(PCIDevice *pdev)
647{
648 pvrdma_fini(pdev);
649}
650
651static void pvrdma_class_init(ObjectClass *klass, void *data)
652{
653 DeviceClass *dc = DEVICE_CLASS(klass);
654 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
655
656 k->realize = pvrdma_realize;
657 k->exit = pvrdma_exit;
658 k->vendor_id = PCI_VENDOR_ID_VMWARE;
659 k->device_id = PCI_DEVICE_ID_VMWARE_PVRDMA;
660 k->revision = 0x00;
661 k->class_id = PCI_CLASS_NETWORK_OTHER;
662
663 dc->desc = "RDMA Device";
664 dc->props = pvrdma_dev_properties;
665 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
666}
667
668static const TypeInfo pvrdma_info = {
669 .name = PVRDMA_HW_NAME,
670 .parent = TYPE_PCI_DEVICE,
671 .instance_size = sizeof(PVRDMADev),
672 .class_init = pvrdma_class_init,
673 .interfaces = (InterfaceInfo[]) {
674 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
675 { }
676 }
677};
678
679static void register_types(void)
680{
681 type_register_static(&pvrdma_info);
682}
683
684type_init(register_types)
685
