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14#ifndef HW_S390_PCI_BUS_H
15#define HW_S390_PCI_BUS_H
16
17#include "hw/pci/pci.h"
18#include "hw/pci/pci_host.h"
19#include "hw/s390x/sclp.h"
20#include "hw/s390x/s390_flic.h"
21#include "hw/s390x/css.h"
22
23#define TYPE_S390_PCI_HOST_BRIDGE "s390-pcihost"
24#define TYPE_S390_PCI_BUS "s390-pcibus"
25#define TYPE_S390_PCI_DEVICE "zpci"
26#define TYPE_S390_PCI_IOMMU "s390-pci-iommu"
27#define TYPE_S390_IOMMU_MEMORY_REGION "s390-iommu-memory-region"
28#define FH_MASK_ENABLE 0x80000000
29#define FH_MASK_INSTANCE 0x7f000000
30#define FH_MASK_SHM 0x00ff0000
31#define FH_MASK_INDEX 0x0000ffff
32#define FH_SHM_VFIO 0x00010000
33#define FH_SHM_EMUL 0x00020000
34#define ZPCI_MAX_FID 0xffffffff
35#define ZPCI_MAX_UID 0xffff
36#define UID_UNDEFINED 0
37#define UID_CHECKING_ENABLED 0x01
38#define HOT_UNPLUG_TIMEOUT (NANOSECONDS_PER_SECOND * 60 * 5)
39
40#define S390_PCI_HOST_BRIDGE(obj) \
41 OBJECT_CHECK(S390pciState, (obj), TYPE_S390_PCI_HOST_BRIDGE)
42#define S390_PCI_BUS(obj) \
43 OBJECT_CHECK(S390PCIBus, (obj), TYPE_S390_PCI_BUS)
44#define S390_PCI_DEVICE(obj) \
45 OBJECT_CHECK(S390PCIBusDevice, (obj), TYPE_S390_PCI_DEVICE)
46#define S390_PCI_IOMMU(obj) \
47 OBJECT_CHECK(S390PCIIOMMU, (obj), TYPE_S390_PCI_IOMMU)
48
49#define HP_EVENT_TO_CONFIGURED 0x0301
50#define HP_EVENT_RESERVED_TO_STANDBY 0x0302
51#define HP_EVENT_DECONFIGURE_REQUEST 0x0303
52#define HP_EVENT_CONFIGURED_TO_STBRES 0x0304
53#define HP_EVENT_STANDBY_TO_RESERVED 0x0308
54
55#define ERR_EVENT_INVALAS 0x1
56#define ERR_EVENT_OORANGE 0x2
57#define ERR_EVENT_INVALTF 0x3
58#define ERR_EVENT_TPROTE 0x4
59#define ERR_EVENT_APROTE 0x5
60#define ERR_EVENT_KEYE 0x6
61#define ERR_EVENT_INVALTE 0x7
62#define ERR_EVENT_INVALTL 0x8
63#define ERR_EVENT_TT 0x9
64#define ERR_EVENT_INVALMS 0xa
65#define ERR_EVENT_SERR 0xb
66#define ERR_EVENT_NOMSI 0x10
67#define ERR_EVENT_INVALBV 0x11
68#define ERR_EVENT_AIBV 0x12
69#define ERR_EVENT_AIRERR 0x13
70#define ERR_EVENT_FMBA 0x2a
71#define ERR_EVENT_FMBUP 0x2b
72#define ERR_EVENT_FMBPRO 0x2c
73#define ERR_EVENT_CCONF 0x30
74#define ERR_EVENT_SERVAC 0x3a
75#define ERR_EVENT_PERMERR 0x3b
76
77#define ERR_EVENT_Q_BIT 0x2
78#define ERR_EVENT_MVN_OFFSET 16
79
80#define ZPCI_MSI_VEC_BITS 11
81#define ZPCI_MSI_VEC_MASK 0x7ff
82
83#define ZPCI_MSI_ADDR 0xfe00000000000000ULL
84#define ZPCI_SDMA_ADDR 0x100000000ULL
85#define ZPCI_EDMA_ADDR 0x1ffffffffffffffULL
86
87#define PAGE_SHIFT 12
88#define PAGE_SIZE (1 << PAGE_SHIFT)
89#define PAGE_MASK (~(PAGE_SIZE-1))
90#define PAGE_DEFAULT_ACC 0
91#define PAGE_DEFAULT_KEY (PAGE_DEFAULT_ACC << 4)
92
93
94enum ZpciIoatDtype {
95 ZPCI_IOTA_STO = 0,
96 ZPCI_IOTA_RTTO = 1,
97 ZPCI_IOTA_RSTO = 2,
98 ZPCI_IOTA_RFTO = 3,
99 ZPCI_IOTA_PFAA = 4,
100 ZPCI_IOTA_IOPFAA = 5,
101 ZPCI_IOTA_IOPTO = 7
102};
103
104#define ZPCI_IOTA_IOT_ENABLED 0x800ULL
105#define ZPCI_IOTA_DT_ST (ZPCI_IOTA_STO << 2)
106#define ZPCI_IOTA_DT_RT (ZPCI_IOTA_RTTO << 2)
107#define ZPCI_IOTA_DT_RS (ZPCI_IOTA_RSTO << 2)
108#define ZPCI_IOTA_DT_RF (ZPCI_IOTA_RFTO << 2)
109#define ZPCI_IOTA_DT_PF (ZPCI_IOTA_PFAA << 2)
110#define ZPCI_IOTA_FS_4K 0
111#define ZPCI_IOTA_FS_1M 1
112#define ZPCI_IOTA_FS_2G 2
113#define ZPCI_KEY (PAGE_DEFAULT_KEY << 5)
114
115#define ZPCI_IOTA_STO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_ST)
116#define ZPCI_IOTA_RTTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RT)
117#define ZPCI_IOTA_RSTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RS)
118#define ZPCI_IOTA_RFTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RF)
119#define ZPCI_IOTA_RFAA_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY |\
120 ZPCI_IOTA_DT_PF | ZPCI_IOTA_FS_2G)
121
122
123#define ZPCI_INDEX_MASK 0x7ffULL
124
125#define ZPCI_TABLE_TYPE_MASK 0xc
126#define ZPCI_TABLE_TYPE_RFX 0xc
127#define ZPCI_TABLE_TYPE_RSX 0x8
128#define ZPCI_TABLE_TYPE_RTX 0x4
129#define ZPCI_TABLE_TYPE_SX 0x0
130
131#define ZPCI_TABLE_LEN_RFX 0x3
132#define ZPCI_TABLE_LEN_RSX 0x3
133#define ZPCI_TABLE_LEN_RTX 0x3
134
135#define ZPCI_TABLE_OFFSET_MASK 0xc0
136#define ZPCI_TABLE_SIZE 0x4000
137#define ZPCI_TABLE_ALIGN ZPCI_TABLE_SIZE
138#define ZPCI_TABLE_ENTRY_SIZE (sizeof(unsigned long))
139#define ZPCI_TABLE_ENTRIES (ZPCI_TABLE_SIZE / ZPCI_TABLE_ENTRY_SIZE)
140
141#define ZPCI_TABLE_BITS 11
142#define ZPCI_PT_BITS 8
143#define ZPCI_ST_SHIFT (ZPCI_PT_BITS + PAGE_SHIFT)
144#define ZPCI_RT_SHIFT (ZPCI_ST_SHIFT + ZPCI_TABLE_BITS)
145
146#define ZPCI_RTE_FLAG_MASK 0x3fffULL
147#define ZPCI_RTE_ADDR_MASK (~ZPCI_RTE_FLAG_MASK)
148#define ZPCI_STE_FLAG_MASK 0x7ffULL
149#define ZPCI_STE_ADDR_MASK (~ZPCI_STE_FLAG_MASK)
150
151#define ZPCI_SFAA_MASK (~((1ULL << 20) - 1))
152
153
154#define ZPCI_PTE_VALID_MASK 0x400
155#define ZPCI_PTE_INVALID 0x400
156#define ZPCI_PTE_VALID 0x000
157#define ZPCI_PT_SIZE 0x800
158#define ZPCI_PT_ALIGN ZPCI_PT_SIZE
159#define ZPCI_PT_ENTRIES (ZPCI_PT_SIZE / ZPCI_TABLE_ENTRY_SIZE)
160#define ZPCI_PT_MASK (ZPCI_PT_ENTRIES - 1)
161
162#define ZPCI_PTE_FLAG_MASK 0xfffULL
163#define ZPCI_PTE_ADDR_MASK (~ZPCI_PTE_FLAG_MASK)
164
165
166#define ZPCI_TABLE_VALID 0x00
167#define ZPCI_TABLE_INVALID 0x20
168#define ZPCI_TABLE_PROTECTED 0x200
169#define ZPCI_TABLE_UNPROTECTED 0x000
170#define ZPCI_TABLE_FC 0x400
171
172#define ZPCI_TABLE_VALID_MASK 0x20
173#define ZPCI_TABLE_PROT_MASK 0x200
174
175#define ZPCI_ETT_RT 1
176#define ZPCI_ETT_ST 0
177#define ZPCI_ETT_PT -1
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197typedef enum {
198 ZPCI_FS_RESERVED,
199 ZPCI_FS_STANDBY,
200 ZPCI_FS_DISABLED,
201 ZPCI_FS_ENABLED,
202 ZPCI_FS_BLOCKED,
203 ZPCI_FS_ERROR,
204 ZPCI_FS_PERMANENT_ERROR,
205} ZpciState;
206
207typedef struct SeiContainer {
208 QTAILQ_ENTRY(SeiContainer) link;
209 uint32_t fid;
210 uint32_t fh;
211 uint8_t cc;
212 uint16_t pec;
213 uint64_t faddr;
214 uint32_t e;
215} SeiContainer;
216
217typedef struct PciCcdfErr {
218 uint32_t reserved1;
219 uint32_t fh;
220 uint32_t fid;
221 uint32_t e;
222 uint64_t faddr;
223 uint32_t reserved3;
224 uint16_t reserved4;
225 uint16_t pec;
226} QEMU_PACKED PciCcdfErr;
227
228typedef struct PciCcdfAvail {
229 uint32_t reserved1;
230 uint32_t fh;
231 uint32_t fid;
232 uint32_t reserved2;
233 uint32_t reserved3;
234 uint32_t reserved4;
235 uint32_t reserved5;
236 uint16_t reserved6;
237 uint16_t pec;
238} QEMU_PACKED PciCcdfAvail;
239
240typedef struct ChscSeiNt2Res {
241 uint16_t length;
242 uint16_t code;
243 uint16_t reserved1;
244 uint8_t reserved2;
245 uint8_t nt;
246 uint8_t flags;
247 uint8_t reserved3;
248 uint8_t reserved4;
249 uint8_t cc;
250 uint32_t reserved5[13];
251 uint8_t ccdf[4016];
252} QEMU_PACKED ChscSeiNt2Res;
253
254typedef struct S390MsixInfo {
255 bool available;
256 uint8_t table_bar;
257 uint8_t pba_bar;
258 uint16_t entries;
259 uint32_t table_offset;
260 uint32_t pba_offset;
261} S390MsixInfo;
262
263typedef struct S390IOTLBEntry {
264 uint64_t iova;
265 uint64_t translated_addr;
266 uint64_t len;
267 uint64_t perm;
268} S390IOTLBEntry;
269
270typedef struct S390PCIBusDevice S390PCIBusDevice;
271typedef struct S390PCIIOMMU {
272 Object parent_obj;
273 S390PCIBusDevice *pbdev;
274 AddressSpace as;
275 MemoryRegion mr;
276 IOMMUMemoryRegion iommu_mr;
277 bool enabled;
278 uint64_t g_iota;
279 uint64_t pba;
280 uint64_t pal;
281 GHashTable *iotlb;
282} S390PCIIOMMU;
283
284typedef struct S390PCIIOMMUTable {
285 uint64_t key;
286 S390PCIIOMMU *iommu[PCI_SLOT_MAX];
287} S390PCIIOMMUTable;
288
289struct S390PCIBusDevice {
290 DeviceState qdev;
291 PCIDevice *pdev;
292 ZpciState state;
293 char *target;
294 uint16_t uid;
295 uint32_t idx;
296 uint32_t fh;
297 uint32_t fid;
298 bool fid_defined;
299 uint64_t fmb_addr;
300 uint8_t isc;
301 uint16_t noi;
302 uint16_t maxstbl;
303 uint8_t sum;
304 S390MsixInfo msix;
305 AdapterRoutes routes;
306 S390PCIIOMMU *iommu;
307 MemoryRegion msix_notify_mr;
308 IndAddr *summary_ind;
309 IndAddr *indicator;
310 QEMUTimer *release_timer;
311 QTAILQ_ENTRY(S390PCIBusDevice) link;
312};
313
314typedef struct S390PCIBus {
315 BusState qbus;
316} S390PCIBus;
317
318typedef struct S390pciState {
319 PCIHostState parent_obj;
320 uint32_t next_idx;
321 int bus_no;
322 S390PCIBus *bus;
323 GHashTable *iommu_table;
324 GHashTable *zpci_table;
325 QTAILQ_HEAD(, SeiContainer) pending_sei;
326 QTAILQ_HEAD(, S390PCIBusDevice) zpci_devs;
327} S390pciState;
328
329S390pciState *s390_get_phb(void);
330int pci_chsc_sei_nt2_get_event(void *res);
331int pci_chsc_sei_nt2_have_event(void);
332void s390_pci_sclp_configure(SCCB *sccb);
333void s390_pci_sclp_deconfigure(SCCB *sccb);
334void s390_pci_iommu_enable(S390PCIIOMMU *iommu);
335void s390_pci_iommu_disable(S390PCIIOMMU *iommu);
336void s390_pci_generate_error_event(uint16_t pec, uint32_t fh, uint32_t fid,
337 uint64_t faddr, uint32_t e);
338uint16_t s390_guest_io_table_walk(uint64_t g_iota, hwaddr addr,
339 S390IOTLBEntry *entry);
340S390PCIBusDevice *s390_pci_find_dev_by_idx(S390pciState *s, uint32_t idx);
341S390PCIBusDevice *s390_pci_find_dev_by_fh(S390pciState *s, uint32_t fh);
342S390PCIBusDevice *s390_pci_find_dev_by_fid(S390pciState *s, uint32_t fid);
343S390PCIBusDevice *s390_pci_find_dev_by_target(S390pciState *s,
344 const char *target);
345S390PCIBusDevice *s390_pci_find_next_avail_dev(S390pciState *s,
346 S390PCIBusDevice *pbdev);
347
348#endif
349
