LXR qemu/include/hw/acpi/tpm.h

   1/*
   2 * tpm.h - TPM ACPI definitions
   3 *
   4 * Copyright (C) 2014 IBM Corporation
   5 *
   6 * Authors:
   7 *  Stefan Berger <stefanb@us.ibm.com>
   8 *
   9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10 * See the COPYING file in the top-level directory.
  11 *
  12 * Implementation of the TIS interface according to specs found at
  13 * http://www.trustedcomputinggroup.org
  14 *
  15 */
  16#ifndef HW_ACPI_TPM_H
  17#define HW_ACPI_TPM_H
  18
  19#include "qemu/units.h"
  20#include "hw/registerfields.h"
  21
  22#define TPM_TIS_ADDR_BASE           0xFED40000
  23#define TPM_TIS_ADDR_SIZE           0x5000
  24
  25#define TPM_TIS_IRQ                 5
  26
  27#define TPM_TIS_NUM_LOCALITIES      5     /* per spec */
  28#define TPM_TIS_LOCALITY_SHIFT      12
  29
  30/* tis registers */
  31#define TPM_TIS_REG_ACCESS                0x00
  32#define TPM_TIS_REG_INT_ENABLE            0x08
  33#define TPM_TIS_REG_INT_VECTOR            0x0c
  34#define TPM_TIS_REG_INT_STATUS            0x10
  35#define TPM_TIS_REG_INTF_CAPABILITY       0x14
  36#define TPM_TIS_REG_STS                   0x18
  37#define TPM_TIS_REG_DATA_FIFO             0x24
  38#define TPM_TIS_REG_INTERFACE_ID          0x30
  39#define TPM_TIS_REG_DATA_XFIFO            0x80
  40#define TPM_TIS_REG_DATA_XFIFO_END        0xbc
  41#define TPM_TIS_REG_DID_VID               0xf00
  42#define TPM_TIS_REG_RID                   0xf04
  43
  44/* vendor-specific registers */
  45#define TPM_TIS_REG_DEBUG                 0xf90
  46
  47#define TPM_TIS_STS_TPM_FAMILY_MASK         (0x3 << 26)/* TPM 2.0 */
  48#define TPM_TIS_STS_TPM_FAMILY1_2           (0 << 26)  /* TPM 2.0 */
  49#define TPM_TIS_STS_TPM_FAMILY2_0           (1 << 26)  /* TPM 2.0 */
  50#define TPM_TIS_STS_RESET_ESTABLISHMENT_BIT (1 << 25)  /* TPM 2.0 */
  51#define TPM_TIS_STS_COMMAND_CANCEL          (1 << 24)  /* TPM 2.0 */
  52
  53#define TPM_TIS_STS_VALID                 (1 << 7)
  54#define TPM_TIS_STS_COMMAND_READY         (1 << 6)
  55#define TPM_TIS_STS_TPM_GO                (1 << 5)
  56#define TPM_TIS_STS_DATA_AVAILABLE        (1 << 4)
  57#define TPM_TIS_STS_EXPECT                (1 << 3)
  58#define TPM_TIS_STS_SELFTEST_DONE         (1 << 2)
  59#define TPM_TIS_STS_RESPONSE_RETRY        (1 << 1)
  60
  61#define TPM_TIS_BURST_COUNT_SHIFT         8
  62#define TPM_TIS_BURST_COUNT(X) \
  63    ((X) << TPM_TIS_BURST_COUNT_SHIFT)
  64
  65#define TPM_TIS_ACCESS_TPM_REG_VALID_STS  (1 << 7)
  66#define TPM_TIS_ACCESS_ACTIVE_LOCALITY    (1 << 5)
  67#define TPM_TIS_ACCESS_BEEN_SEIZED        (1 << 4)
  68#define TPM_TIS_ACCESS_SEIZE              (1 << 3)
  69#define TPM_TIS_ACCESS_PENDING_REQUEST    (1 << 2)
  70#define TPM_TIS_ACCESS_REQUEST_USE        (1 << 1)
  71#define TPM_TIS_ACCESS_TPM_ESTABLISHMENT  (1 << 0)
  72
  73#define TPM_TIS_INT_ENABLED               (1 << 31)
  74#define TPM_TIS_INT_DATA_AVAILABLE        (1 << 0)
  75#define TPM_TIS_INT_STS_VALID             (1 << 1)
  76#define TPM_TIS_INT_LOCALITY_CHANGED      (1 << 2)
  77#define TPM_TIS_INT_COMMAND_READY         (1 << 7)
  78
  79#define TPM_TIS_INT_POLARITY_MASK         (3 << 3)
  80#define TPM_TIS_INT_POLARITY_LOW_LEVEL    (1 << 3)
  81
  82#define TPM_TIS_INTERRUPTS_SUPPORTED (TPM_TIS_INT_LOCALITY_CHANGED | \
  83                                      TPM_TIS_INT_DATA_AVAILABLE   | \
  84                                      TPM_TIS_INT_STS_VALID | \
  85                                      TPM_TIS_INT_COMMAND_READY)
  86
  87#define TPM_TIS_CAP_INTERFACE_VERSION1_3 (2 << 28)
  88#define TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 (3 << 28)
  89#define TPM_TIS_CAP_DATA_TRANSFER_64B    (3 << 9)
  90#define TPM_TIS_CAP_DATA_TRANSFER_LEGACY (0 << 9)
  91#define TPM_TIS_CAP_BURST_COUNT_DYNAMIC  (0 << 8)
  92#define TPM_TIS_CAP_INTERRUPT_LOW_LEVEL  (1 << 4) /* support is mandatory */
  93#define TPM_TIS_CAPABILITIES_SUPPORTED1_3 \
  94    (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \
  95     TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \
  96     TPM_TIS_CAP_DATA_TRANSFER_64B | \
  97     TPM_TIS_CAP_INTERFACE_VERSION1_3 | \
  98     TPM_TIS_INTERRUPTS_SUPPORTED)
  99
 100#define TPM_TIS_CAPABILITIES_SUPPORTED2_0 \
 101    (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \
 102     TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \
 103     TPM_TIS_CAP_DATA_TRANSFER_64B | \
 104     TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 | \
 105     TPM_TIS_INTERRUPTS_SUPPORTED)
 106
 107#define TPM_TIS_IFACE_ID_INTERFACE_TIS1_3   (0xf)     /* TPM 2.0 */
 108#define TPM_TIS_IFACE_ID_INTERFACE_FIFO     (0x0)     /* TPM 2.0 */
 109#define TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO (0 << 4)  /* TPM 2.0 */
 110#define TPM_TIS_IFACE_ID_CAP_5_LOCALITIES   (1 << 8)  /* TPM 2.0 */
 111#define TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED  (1 << 13) /* TPM 2.0 */
 112#define TPM_TIS_IFACE_ID_INT_SEL_LOCK       (1 << 19) /* TPM 2.0 */
 113
 114#define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS1_3 \
 115    (TPM_TIS_IFACE_ID_INTERFACE_TIS1_3 | \
 116     (~0u << 4)/* all of it is don't care */)
 117
 118/* if backend was a TPM 2.0: */
 119#define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS2_0 \
 120    (TPM_TIS_IFACE_ID_INTERFACE_FIFO | \
 121     TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO | \
 122     TPM_TIS_IFACE_ID_CAP_5_LOCALITIES | \
 123     TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED)
 124
 125#define TPM_TIS_TPM_DID       0x0001
 126#define TPM_TIS_TPM_VID       PCI_VENDOR_ID_IBM
 127#define TPM_TIS_TPM_RID       0x0001
 128
 129#define TPM_TIS_NO_DATA_BYTE  0xff
 130
 131
 132REG32(CRB_LOC_STATE, 0x00)
 133  FIELD(CRB_LOC_STATE, tpmEstablished, 0, 1)
 134  FIELD(CRB_LOC_STATE, locAssigned, 1, 1)
 135  FIELD(CRB_LOC_STATE, activeLocality, 2, 3)
 136  FIELD(CRB_LOC_STATE, reserved, 5, 2)
 137  FIELD(CRB_LOC_STATE, tpmRegValidSts, 7, 1)
 138REG32(CRB_LOC_CTRL, 0x08)
 139REG32(CRB_LOC_STS, 0x0C)
 140  FIELD(CRB_LOC_STS, Granted, 0, 1)
 141  FIELD(CRB_LOC_STS, beenSeized, 1, 1)
 142REG32(CRB_INTF_ID, 0x30)
 143  FIELD(CRB_INTF_ID, InterfaceType, 0, 4)
 144  FIELD(CRB_INTF_ID, InterfaceVersion, 4, 4)
 145  FIELD(CRB_INTF_ID, CapLocality, 8, 1)
 146  FIELD(CRB_INTF_ID, CapCRBIdleBypass, 9, 1)
 147  FIELD(CRB_INTF_ID, Reserved1, 10, 1)
 148  FIELD(CRB_INTF_ID, CapDataXferSizeSupport, 11, 2)
 149  FIELD(CRB_INTF_ID, CapFIFO, 13, 1)
 150  FIELD(CRB_INTF_ID, CapCRB, 14, 1)
 151  FIELD(CRB_INTF_ID, CapIFRes, 15, 2)
 152  FIELD(CRB_INTF_ID, InterfaceSelector, 17, 2)
 153  FIELD(CRB_INTF_ID, IntfSelLock, 19, 1)
 154  FIELD(CRB_INTF_ID, Reserved2, 20, 4)
 155  FIELD(CRB_INTF_ID, RID, 24, 8)
 156REG32(CRB_INTF_ID2, 0x34)
 157  FIELD(CRB_INTF_ID2, VID, 0, 16)
 158  FIELD(CRB_INTF_ID2, DID, 16, 16)
 159REG32(CRB_CTRL_EXT, 0x38)
 160REG32(CRB_CTRL_REQ, 0x40)
 161REG32(CRB_CTRL_STS, 0x44)
 162  FIELD(CRB_CTRL_STS, tpmSts, 0, 1)
 163  FIELD(CRB_CTRL_STS, tpmIdle, 1, 1)
 164REG32(CRB_CTRL_CANCEL, 0x48)
 165REG32(CRB_CTRL_START, 0x4C)
 166REG32(CRB_INT_ENABLED, 0x50)
 167REG32(CRB_INT_STS, 0x54)
 168REG32(CRB_CTRL_CMD_SIZE, 0x58)
 169REG32(CRB_CTRL_CMD_LADDR, 0x5C)
 170REG32(CRB_CTRL_CMD_HADDR, 0x60)
 171REG32(CRB_CTRL_RSP_SIZE, 0x64)
 172REG32(CRB_CTRL_RSP_ADDR, 0x68)
 173REG32(CRB_DATA_BUFFER, 0x80)
 174
 175#define TPM_CRB_ADDR_BASE           0xFED40000
 176#define TPM_CRB_ADDR_SIZE           0x1000
 177#define TPM_CRB_ADDR_CTRL           (TPM_CRB_ADDR_BASE + A_CRB_CTRL_REQ)
 178#define TPM_CRB_R_MAX               R_CRB_DATA_BUFFER
 179
 180#define TPM_LOG_AREA_MINIMUM_SIZE   (64 * KiB)
 181
 182#define TPM_TCPA_ACPI_CLASS_CLIENT  0
 183#define TPM_TCPA_ACPI_CLASS_SERVER  1
 184
 185#define TPM2_ACPI_CLASS_CLIENT      0
 186#define TPM2_ACPI_CLASS_SERVER      1
 187
 188#define TPM2_START_METHOD_MMIO      6
 189#define TPM2_START_METHOD_CRB       7
 190
 191#endif /* HW_ACPI_TPM_H */
 192