LXR qemu/include/hw/block/flash.h

   1#ifndef HW_FLASH_H
   2#define HW_FLASH_H
   3
   4/* NOR flash devices */
   5
   6#include "exec/memory.h"
   7
   8/* pflash_cfi01.c */
   9
  10#define TYPE_PFLASH_CFI01 "cfi.pflash01"
  11#define PFLASH_CFI01(obj) \
  12    OBJECT_CHECK(PFlashCFI01, (obj), TYPE_PFLASH_CFI01)
  13
  14typedef struct PFlashCFI01 PFlashCFI01;
  15
  16PFlashCFI01 *pflash_cfi01_register(hwaddr base,
  17                                   DeviceState *qdev, const char *name,
  18                                   hwaddr size,
  19                                   BlockBackend *blk,
  20                                   uint32_t sector_len, int nb_blocs,
  21                                   int width,
  22                                   uint16_t id0, uint16_t id1,
  23                                   uint16_t id2, uint16_t id3,
  24                                   int be);
  25MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl);
  26
  27/* pflash_cfi02.c */
  28
  29#define TYPE_PFLASH_CFI02 "cfi.pflash02"
  30#define PFLASH_CFI02(obj) \
  31    OBJECT_CHECK(PFlashCFI02, (obj), TYPE_PFLASH_CFI02)
  32
  33typedef struct PFlashCFI02 PFlashCFI02;
  34
  35PFlashCFI02 *pflash_cfi02_register(hwaddr base,
  36                                   DeviceState *qdev, const char *name,
  37                                   hwaddr size,
  38                                   BlockBackend *blk,
  39                                   uint32_t sector_len, int nb_blocs,
  40                                   int nb_mappings,
  41                                   int width,
  42                                   uint16_t id0, uint16_t id1,
  43                                   uint16_t id2, uint16_t id3,
  44                                   uint16_t unlock_addr0,
  45                                   uint16_t unlock_addr1,
  46                                   int be);
  47
  48/* nand.c */
  49DeviceState *nand_init(BlockBackend *blk, int manf_id, int chip_id);
  50void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale,
  51                  uint8_t ce, uint8_t wp, uint8_t gnd);
  52void nand_getpins(DeviceState *dev, int *rb);
  53void nand_setio(DeviceState *dev, uint32_t value);
  54uint32_t nand_getio(DeviceState *dev);
  55uint32_t nand_getbuswidth(DeviceState *dev);
  56
  57#define NAND_MFR_TOSHIBA        0x98
  58#define NAND_MFR_SAMSUNG        0xec
  59#define NAND_MFR_FUJITSU        0x04
  60#define NAND_MFR_NATIONAL       0x8f
  61#define NAND_MFR_RENESAS        0x07
  62#define NAND_MFR_STMICRO        0x20
  63#define NAND_MFR_HYNIX          0xad
  64#define NAND_MFR_MICRON         0x2c
  65
  66/* onenand.c */
  67void *onenand_raw_otp(DeviceState *onenand_device);
  68
  69/* ecc.c */
  70typedef struct {
  71    uint8_t cp;         /* Column parity */
  72    uint16_t lp[2];     /* Line parity */
  73    uint16_t count;
  74} ECCState;
  75
  76uint8_t ecc_digest(ECCState *s, uint8_t sample);
  77void ecc_reset(ECCState *s);
  78extern VMStateDescription vmstate_ecc_state;
  79
  80#endif
  81