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21#include "qemu/osdep.h"
22#include "target/arm/idau.h"
23#include "qemu/error-report.h"
24#include "qapi/error.h"
25#include "cpu.h"
26#include "internals.h"
27#include "qemu-common.h"
28#include "exec/exec-all.h"
29#include "hw/qdev-properties.h"
30#if !defined(CONFIG_USER_ONLY)
31#include "hw/loader.h"
32#endif
33#include "hw/arm/arm.h"
34#include "sysemu/sysemu.h"
35#include "sysemu/hw_accel.h"
36#include "kvm_arm.h"
37#include "disas/capstone.h"
38#include "fpu/softfloat.h"
39
40static void arm_cpu_set_pc(CPUState *cs, vaddr value)
41{
42 ARMCPU *cpu = ARM_CPU(cs);
43
44 cpu->env.regs[15] = value;
45}
46
47static bool arm_cpu_has_work(CPUState *cs)
48{
49 ARMCPU *cpu = ARM_CPU(cs);
50
51 return (cpu->power_state != PSCI_OFF)
52 && cs->interrupt_request &
53 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
54 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
55 | CPU_INTERRUPT_EXITTB);
56}
57
58void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
59 void *opaque)
60{
61 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
62
63 entry->hook = hook;
64 entry->opaque = opaque;
65
66 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node);
67}
68
69void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
70 void *opaque)
71{
72 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
73
74 entry->hook = hook;
75 entry->opaque = opaque;
76
77 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node);
78}
79
80static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
81{
82
83 ARMCPRegInfo *ri = value;
84 ARMCPU *cpu = opaque;
85
86 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
87 return;
88 }
89
90 if (ri->resetfn) {
91 ri->resetfn(&cpu->env, ri);
92 return;
93 }
94
95
96
97
98
99
100 if (!ri->fieldoffset) {
101 return;
102 }
103
104 if (cpreg_field_is_64bit(ri)) {
105 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
106 } else {
107 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
108 }
109}
110
111static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
112{
113
114
115
116
117
118 ARMCPRegInfo *ri = value;
119 ARMCPU *cpu = opaque;
120 uint64_t oldvalue, newvalue;
121
122 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
123 return;
124 }
125
126 oldvalue = read_raw_cp_reg(&cpu->env, ri);
127 cp_reg_reset(key, value, opaque);
128 newvalue = read_raw_cp_reg(&cpu->env, ri);
129 assert(oldvalue == newvalue);
130}
131
132
133static void arm_cpu_reset(CPUState *s)
134{
135 ARMCPU *cpu = ARM_CPU(s);
136 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
137 CPUARMState *env = &cpu->env;
138
139 acc->parent_reset(s);
140
141 memset(env, 0, offsetof(CPUARMState, end_reset_fields));
142
143 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
144 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
145
146 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
147 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0;
148 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1;
149 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2;
150
151 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON;
152 s->halted = cpu->start_powered_off;
153
154 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
155 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
156 }
157
158 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
159
160 env->aarch64 = 1;
161#if defined(CONFIG_USER_ONLY)
162 env->pstate = PSTATE_MODE_EL0t;
163
164 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
165
166 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
167
168 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
169 env->cp15.cptr_el[3] |= CPTR_EZ;
170
171 env->vfp.zcr_el[1] = cpu->sve_max_vq - 1;
172 env->vfp.zcr_el[2] = env->vfp.zcr_el[1];
173 env->vfp.zcr_el[3] = env->vfp.zcr_el[1];
174#else
175
176 if (arm_feature(env, ARM_FEATURE_EL3)) {
177 env->pstate = PSTATE_MODE_EL3h;
178 } else if (arm_feature(env, ARM_FEATURE_EL2)) {
179 env->pstate = PSTATE_MODE_EL2h;
180 } else {
181 env->pstate = PSTATE_MODE_EL1h;
182 }
183 env->pc = cpu->rvbar;
184#endif
185 } else {
186#if defined(CONFIG_USER_ONLY)
187
188 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
189#endif
190 }
191
192#if defined(CONFIG_USER_ONLY)
193 env->uncached_cpsr = ARM_CPU_MODE_USR;
194
195 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
196 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
197 env->cp15.c15_cpar = 3;
198 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
199 env->cp15.c15_cpar = 1;
200 }
201#else
202
203
204
205
206
207
208 if (arm_feature(env, ARM_FEATURE_EL2) &&
209 !arm_feature(env, ARM_FEATURE_EL3)) {
210 env->uncached_cpsr = ARM_CPU_MODE_HYP;
211 } else {
212 env->uncached_cpsr = ARM_CPU_MODE_SVC;
213 }
214 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
215
216 if (arm_feature(env, ARM_FEATURE_M)) {
217 uint32_t initial_msp;
218 uint32_t initial_pc;
219 uint8_t *rom;
220 uint32_t vecbase;
221
222 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
223 env->v7m.secure = true;
224 } else {
225
226
227
228
229
230 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
231 }
232
233
234
235
236
237 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK;
238 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK;
239 if (arm_feature(env, ARM_FEATURE_V8)) {
240
241 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK;
242 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK;
243 }
244 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
245 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK;
246 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
247 }
248
249
250 env->regs[14] = 0xffffffff;
251
252 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80;
253
254
255 vecbase = env->v7m.vecbase[env->v7m.secure];
256 rom = rom_ptr(vecbase, 8);
257 if (rom) {
258
259
260
261 initial_msp = ldl_p(rom);
262 initial_pc = ldl_p(rom + 4);
263 } else {
264
265
266
267
268
269 initial_msp = ldl_phys(s->as, vecbase);
270 initial_pc = ldl_phys(s->as, vecbase + 4);
271 }
272
273 env->regs[13] = initial_msp & 0xFFFFFFFC;
274 env->regs[15] = initial_pc & ~1;
275 env->thumb = initial_pc & 1;
276 }
277
278
279
280
281
282 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
283 env->regs[15] = 0xFFFF0000;
284 }
285
286
287
288
289
290 arm_clear_exclusive(env);
291
292 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
293#endif
294
295 if (arm_feature(env, ARM_FEATURE_PMSA)) {
296 if (cpu->pmsav7_dregion > 0) {
297 if (arm_feature(env, ARM_FEATURE_V8)) {
298 memset(env->pmsav8.rbar[M_REG_NS], 0,
299 sizeof(*env->pmsav8.rbar[M_REG_NS])
300 * cpu->pmsav7_dregion);
301 memset(env->pmsav8.rlar[M_REG_NS], 0,
302 sizeof(*env->pmsav8.rlar[M_REG_NS])
303 * cpu->pmsav7_dregion);
304 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
305 memset(env->pmsav8.rbar[M_REG_S], 0,
306 sizeof(*env->pmsav8.rbar[M_REG_S])
307 * cpu->pmsav7_dregion);
308 memset(env->pmsav8.rlar[M_REG_S], 0,
309 sizeof(*env->pmsav8.rlar[M_REG_S])
310 * cpu->pmsav7_dregion);
311 }
312 } else if (arm_feature(env, ARM_FEATURE_V7)) {
313 memset(env->pmsav7.drbar, 0,
314 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
315 memset(env->pmsav7.drsr, 0,
316 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
317 memset(env->pmsav7.dracr, 0,
318 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
319 }
320 }
321 env->pmsav7.rnr[M_REG_NS] = 0;
322 env->pmsav7.rnr[M_REG_S] = 0;
323 env->pmsav8.mair0[M_REG_NS] = 0;
324 env->pmsav8.mair0[M_REG_S] = 0;
325 env->pmsav8.mair1[M_REG_NS] = 0;
326 env->pmsav8.mair1[M_REG_S] = 0;
327 }
328
329 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
330 if (cpu->sau_sregion > 0) {
331 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion);
332 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion);
333 }
334 env->sau.rnr = 0;
335
336
337
338 env->sau.ctrl = 0;
339 }
340
341 set_flush_to_zero(1, &env->vfp.standard_fp_status);
342 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
343 set_default_nan_mode(1, &env->vfp.standard_fp_status);
344 set_float_detect_tininess(float_tininess_before_rounding,
345 &env->vfp.fp_status);
346 set_float_detect_tininess(float_tininess_before_rounding,
347 &env->vfp.standard_fp_status);
348 set_float_detect_tininess(float_tininess_before_rounding,
349 &env->vfp.fp_status_f16);
350#ifndef CONFIG_USER_ONLY
351 if (kvm_enabled()) {
352 kvm_arm_reset_vcpu(cpu);
353 }
354#endif
355
356 hw_breakpoint_update_all(cpu);
357 hw_watchpoint_update_all(cpu);
358}
359
360bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
361{
362 CPUClass *cc = CPU_GET_CLASS(cs);
363 CPUARMState *env = cs->env_ptr;
364 uint32_t cur_el = arm_current_el(env);
365 bool secure = arm_is_secure(env);
366 uint32_t target_el;
367 uint32_t excp_idx;
368 bool ret = false;
369
370 if (interrupt_request & CPU_INTERRUPT_FIQ) {
371 excp_idx = EXCP_FIQ;
372 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
373 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
374 cs->exception_index = excp_idx;
375 env->exception.target_el = target_el;
376 cc->do_interrupt(cs);
377 ret = true;
378 }
379 }
380 if (interrupt_request & CPU_INTERRUPT_HARD) {
381 excp_idx = EXCP_IRQ;
382 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
383 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
384 cs->exception_index = excp_idx;
385 env->exception.target_el = target_el;
386 cc->do_interrupt(cs);
387 ret = true;
388 }
389 }
390 if (interrupt_request & CPU_INTERRUPT_VIRQ) {
391 excp_idx = EXCP_VIRQ;
392 target_el = 1;
393 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
394 cs->exception_index = excp_idx;
395 env->exception.target_el = target_el;
396 cc->do_interrupt(cs);
397 ret = true;
398 }
399 }
400 if (interrupt_request & CPU_INTERRUPT_VFIQ) {
401 excp_idx = EXCP_VFIQ;
402 target_el = 1;
403 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
404 cs->exception_index = excp_idx;
405 env->exception.target_el = target_el;
406 cc->do_interrupt(cs);
407 ret = true;
408 }
409 }
410
411 return ret;
412}
413
414#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
415static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
416{
417 CPUClass *cc = CPU_GET_CLASS(cs);
418 ARMCPU *cpu = ARM_CPU(cs);
419 CPUARMState *env = &cpu->env;
420 bool ret = false;
421
422
423
424
425
426
427
428
429 if (interrupt_request & CPU_INTERRUPT_HARD
430 && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
431 cs->exception_index = EXCP_IRQ;
432 cc->do_interrupt(cs);
433 ret = true;
434 }
435 return ret;
436}
437#endif
438
439void arm_cpu_update_virq(ARMCPU *cpu)
440{
441
442
443
444
445 CPUARMState *env = &cpu->env;
446 CPUState *cs = CPU(cpu);
447
448 bool new_state = (env->cp15.hcr_el2 & HCR_VI) ||
449 (env->irq_line_state & CPU_INTERRUPT_VIRQ);
450
451 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) {
452 if (new_state) {
453 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ);
454 } else {
455 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ);
456 }
457 }
458}
459
460void arm_cpu_update_vfiq(ARMCPU *cpu)
461{
462
463
464
465
466 CPUARMState *env = &cpu->env;
467 CPUState *cs = CPU(cpu);
468
469 bool new_state = (env->cp15.hcr_el2 & HCR_VF) ||
470 (env->irq_line_state & CPU_INTERRUPT_VFIQ);
471
472 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) {
473 if (new_state) {
474 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ);
475 } else {
476 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ);
477 }
478 }
479}
480
481#ifndef CONFIG_USER_ONLY
482static void arm_cpu_set_irq(void *opaque, int irq, int level)
483{
484 ARMCPU *cpu = opaque;
485 CPUARMState *env = &cpu->env;
486 CPUState *cs = CPU(cpu);
487 static const int mask[] = {
488 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
489 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
490 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
491 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
492 };
493
494 if (level) {
495 env->irq_line_state |= mask[irq];
496 } else {
497 env->irq_line_state &= ~mask[irq];
498 }
499
500 switch (irq) {
501 case ARM_CPU_VIRQ:
502 assert(arm_feature(env, ARM_FEATURE_EL2));
503 arm_cpu_update_virq(cpu);
504 break;
505 case ARM_CPU_VFIQ:
506 assert(arm_feature(env, ARM_FEATURE_EL2));
507 arm_cpu_update_vfiq(cpu);
508 break;
509 case ARM_CPU_IRQ:
510 case ARM_CPU_FIQ:
511 if (level) {
512 cpu_interrupt(cs, mask[irq]);
513 } else {
514 cpu_reset_interrupt(cs, mask[irq]);
515 }
516 break;
517 default:
518 g_assert_not_reached();
519 }
520}
521
522static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
523{
524#ifdef CONFIG_KVM
525 ARMCPU *cpu = opaque;
526 CPUARMState *env = &cpu->env;
527 CPUState *cs = CPU(cpu);
528 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
529 uint32_t linestate_bit;
530
531 switch (irq) {
532 case ARM_CPU_IRQ:
533 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
534 linestate_bit = CPU_INTERRUPT_HARD;
535 break;
536 case ARM_CPU_FIQ:
537 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
538 linestate_bit = CPU_INTERRUPT_FIQ;
539 break;
540 default:
541 g_assert_not_reached();
542 }
543
544 if (level) {
545 env->irq_line_state |= linestate_bit;
546 } else {
547 env->irq_line_state &= ~linestate_bit;
548 }
549
550 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
551 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
552#endif
553}
554
555static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
556{
557 ARMCPU *cpu = ARM_CPU(cs);
558 CPUARMState *env = &cpu->env;
559
560 cpu_synchronize_state(cs);
561 return arm_cpu_data_is_big_endian(env);
562}
563
564#endif
565
566static inline void set_feature(CPUARMState *env, int feature)
567{
568 env->features |= 1ULL << feature;
569}
570
571static inline void unset_feature(CPUARMState *env, int feature)
572{
573 env->features &= ~(1ULL << feature);
574}
575
576static int
577print_insn_thumb1(bfd_vma pc, disassemble_info *info)
578{
579 return print_insn_arm(pc | 1, info);
580}
581
582static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
583{
584 ARMCPU *ac = ARM_CPU(cpu);
585 CPUARMState *env = &ac->env;
586 bool sctlr_b;
587
588 if (is_a64(env)) {
589
590
591
592
593#if defined(CONFIG_ARM_A64_DIS)
594 info->print_insn = print_insn_arm_a64;
595#endif
596 info->cap_arch = CS_ARCH_ARM64;
597 info->cap_insn_unit = 4;
598 info->cap_insn_split = 4;
599 } else {
600 int cap_mode;
601 if (env->thumb) {
602 info->print_insn = print_insn_thumb1;
603 info->cap_insn_unit = 2;
604 info->cap_insn_split = 4;
605 cap_mode = CS_MODE_THUMB;
606 } else {
607 info->print_insn = print_insn_arm;
608 info->cap_insn_unit = 4;
609 info->cap_insn_split = 4;
610 cap_mode = CS_MODE_ARM;
611 }
612 if (arm_feature(env, ARM_FEATURE_V8)) {
613 cap_mode |= CS_MODE_V8;
614 }
615 if (arm_feature(env, ARM_FEATURE_M)) {
616 cap_mode |= CS_MODE_MCLASS;
617 }
618 info->cap_arch = CS_ARCH_ARM;
619 info->cap_mode = cap_mode;
620 }
621
622 sctlr_b = arm_sctlr_b(env);
623 if (bswap_code(sctlr_b)) {
624#ifdef TARGET_WORDS_BIGENDIAN
625 info->endian = BFD_ENDIAN_LITTLE;
626#else
627 info->endian = BFD_ENDIAN_BIG;
628#endif
629 }
630 info->flags &= ~INSN_ARM_BE32;
631#ifndef CONFIG_USER_ONLY
632 if (sctlr_b) {
633 info->flags |= INSN_ARM_BE32;
634 }
635#endif
636}
637
638uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
639{
640 uint32_t Aff1 = idx / clustersz;
641 uint32_t Aff0 = idx % clustersz;
642 return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
643}
644
645static void arm_cpu_initfn(Object *obj)
646{
647 CPUState *cs = CPU(obj);
648 ARMCPU *cpu = ARM_CPU(obj);
649
650 cs->env_ptr = &cpu->env;
651 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
652 g_free, g_free);
653
654 QLIST_INIT(&cpu->pre_el_change_hooks);
655 QLIST_INIT(&cpu->el_change_hooks);
656
657#ifndef CONFIG_USER_ONLY
658
659 if (kvm_enabled()) {
660
661
662
663 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
664 } else {
665 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
666 }
667
668 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
669 arm_gt_ptimer_cb, cpu);
670 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
671 arm_gt_vtimer_cb, cpu);
672 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
673 arm_gt_htimer_cb, cpu);
674 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
675 arm_gt_stimer_cb, cpu);
676 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
677 ARRAY_SIZE(cpu->gt_timer_outputs));
678
679 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
680 "gicv3-maintenance-interrupt", 1);
681 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,
682 "pmu-interrupt", 1);
683#endif
684
685
686
687
688
689 cpu->dtb_compatible = "qemu,unknown";
690 cpu->psci_version = 1;
691 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
692
693 if (tcg_enabled()) {
694 cpu->psci_version = 2;
695 }
696}
697
698static Property arm_cpu_reset_cbar_property =
699 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
700
701static Property arm_cpu_reset_hivecs_property =
702 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
703
704static Property arm_cpu_rvbar_property =
705 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
706
707static Property arm_cpu_has_el2_property =
708 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
709
710static Property arm_cpu_has_el3_property =
711 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
712
713static Property arm_cpu_cfgend_property =
714 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
715
716
717static Property arm_cpu_has_pmu_property =
718 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
719
720static Property arm_cpu_has_mpu_property =
721 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
722
723
724
725
726
727
728static Property arm_cpu_pmsav7_dregion_property =
729 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU,
730 pmsav7_dregion,
731 qdev_prop_uint32, uint32_t);
732
733
734static Property arm_cpu_initsvtor_property =
735 DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0);
736
737static void arm_cpu_post_init(Object *obj)
738{
739 ARMCPU *cpu = ARM_CPU(obj);
740
741
742
743
744
745 if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
746 set_feature(&cpu->env, ARM_FEATURE_PMSA);
747 }
748
749 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
750 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
751 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
752 &error_abort);
753 }
754
755 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
756 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
757 &error_abort);
758 }
759
760 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
761 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
762 &error_abort);
763 }
764
765 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
766
767
768
769 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
770 &error_abort);
771
772#ifndef CONFIG_USER_ONLY
773 object_property_add_link(obj, "secure-memory",
774 TYPE_MEMORY_REGION,
775 (Object **)&cpu->secure_memory,
776 qdev_prop_allow_set_link_before_realize,
777 OBJ_PROP_LINK_STRONG,
778 &error_abort);
779#endif
780 }
781
782 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
783 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property,
784 &error_abort);
785 }
786
787 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
788 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property,
789 &error_abort);
790 }
791
792 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
793 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
794 &error_abort);
795 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
796 qdev_property_add_static(DEVICE(obj),
797 &arm_cpu_pmsav7_dregion_property,
798 &error_abort);
799 }
800 }
801
802 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) {
803 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau,
804 qdev_prop_allow_set_link_before_realize,
805 OBJ_PROP_LINK_STRONG,
806 &error_abort);
807 qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property,
808 &error_abort);
809 }
810
811 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
812 &error_abort);
813}
814
815static void arm_cpu_finalizefn(Object *obj)
816{
817 ARMCPU *cpu = ARM_CPU(obj);
818 ARMELChangeHook *hook, *next;
819
820 g_hash_table_destroy(cpu->cp_regs);
821
822 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
823 QLIST_REMOVE(hook, node);
824 g_free(hook);
825 }
826 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
827 QLIST_REMOVE(hook, node);
828 g_free(hook);
829 }
830}
831
832static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
833{
834 CPUState *cs = CPU(dev);
835 ARMCPU *cpu = ARM_CPU(dev);
836 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
837 CPUARMState *env = &cpu->env;
838 int pagebits;
839 Error *local_err = NULL;
840 bool no_aa32 = false;
841
842
843
844
845
846 if (cpu->host_cpu_probe_failed) {
847 if (!kvm_enabled()) {
848 error_setg(errp, "The 'host' CPU type can only be used with KVM");
849 } else {
850 error_setg(errp, "Failed to retrieve host CPU features");
851 }
852 return;
853 }
854
855#ifndef CONFIG_USER_ONLY
856
857
858
859
860 if (arm_feature(env, ARM_FEATURE_M)) {
861 if (!env->nvic) {
862 error_setg(errp, "This board cannot be used with Cortex-M CPUs");
863 return;
864 }
865 } else {
866 if (env->nvic) {
867 error_setg(errp, "This board can only be used with Cortex-M CPUs");
868 return;
869 }
870 }
871#endif
872
873 cpu_exec_realizefn(cs, &local_err);
874 if (local_err != NULL) {
875 error_propagate(errp, local_err);
876 return;
877 }
878
879
880 if (arm_feature(env, ARM_FEATURE_V8)) {
881 if (arm_feature(env, ARM_FEATURE_M)) {
882 set_feature(env, ARM_FEATURE_V7);
883 } else {
884 set_feature(env, ARM_FEATURE_V7VE);
885 }
886 }
887
888
889
890
891
892
893 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
894 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
895 }
896
897 if (arm_feature(env, ARM_FEATURE_V7VE)) {
898
899
900
901
902
903
904
905
906 assert(no_aa32 || cpu_isar_feature(arm_div, cpu));
907 set_feature(env, ARM_FEATURE_LPAE);
908 set_feature(env, ARM_FEATURE_V7);
909 }
910 if (arm_feature(env, ARM_FEATURE_V7)) {
911 set_feature(env, ARM_FEATURE_VAPA);
912 set_feature(env, ARM_FEATURE_THUMB2);
913 set_feature(env, ARM_FEATURE_MPIDR);
914 if (!arm_feature(env, ARM_FEATURE_M)) {
915 set_feature(env, ARM_FEATURE_V6K);
916 } else {
917 set_feature(env, ARM_FEATURE_V6);
918 }
919
920
921
922
923 set_feature(env, ARM_FEATURE_VBAR);
924 }
925 if (arm_feature(env, ARM_FEATURE_V6K)) {
926 set_feature(env, ARM_FEATURE_V6);
927 set_feature(env, ARM_FEATURE_MVFR);
928 }
929 if (arm_feature(env, ARM_FEATURE_V6)) {
930 set_feature(env, ARM_FEATURE_V5);
931 if (!arm_feature(env, ARM_FEATURE_M)) {
932 assert(no_aa32 || cpu_isar_feature(jazelle, cpu));
933 set_feature(env, ARM_FEATURE_AUXCR);
934 }
935 }
936 if (arm_feature(env, ARM_FEATURE_V5)) {
937 set_feature(env, ARM_FEATURE_V4T);
938 }
939 if (arm_feature(env, ARM_FEATURE_VFP4)) {
940 set_feature(env, ARM_FEATURE_VFP3);
941 set_feature(env, ARM_FEATURE_VFP_FP16);
942 }
943 if (arm_feature(env, ARM_FEATURE_VFP3)) {
944 set_feature(env, ARM_FEATURE_VFP);
945 }
946 if (arm_feature(env, ARM_FEATURE_LPAE)) {
947 set_feature(env, ARM_FEATURE_V7MP);
948 set_feature(env, ARM_FEATURE_PXN);
949 }
950 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
951 set_feature(env, ARM_FEATURE_CBAR);
952 }
953 if (arm_feature(env, ARM_FEATURE_THUMB2) &&
954 !arm_feature(env, ARM_FEATURE_M)) {
955 set_feature(env, ARM_FEATURE_THUMB_DSP);
956 }
957
958 if (arm_feature(env, ARM_FEATURE_V7) &&
959 !arm_feature(env, ARM_FEATURE_M) &&
960 !arm_feature(env, ARM_FEATURE_PMSA)) {
961
962
963
964 pagebits = 12;
965 } else {
966
967
968
969 pagebits = 10;
970 }
971 if (!set_preferred_target_page_bits(pagebits)) {
972
973
974
975
976 error_setg(errp, "This CPU requires a smaller page size than the "
977 "system is using");
978 return;
979 }
980
981
982
983
984
985
986 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
987 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index,
988 ARM_DEFAULT_CPUS_PER_CLUSTER);
989 }
990
991 if (cpu->reset_hivecs) {
992 cpu->reset_sctlr |= (1 << 13);
993 }
994
995 if (cpu->cfgend) {
996 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
997 cpu->reset_sctlr |= SCTLR_EE;
998 } else {
999 cpu->reset_sctlr |= SCTLR_B;
1000 }
1001 }
1002
1003 if (!cpu->has_el3) {
1004
1005
1006
1007 unset_feature(env, ARM_FEATURE_EL3);
1008
1009
1010
1011
1012 cpu->id_pfr1 &= ~0xf0;
1013 cpu->isar.id_aa64pfr0 &= ~0xf000;
1014 }
1015
1016 if (!cpu->has_el2) {
1017 unset_feature(env, ARM_FEATURE_EL2);
1018 }
1019
1020 if (!cpu->has_pmu) {
1021 unset_feature(env, ARM_FEATURE_PMU);
1022 cpu->id_aa64dfr0 &= ~0xf00;
1023 }
1024
1025 if (!arm_feature(env, ARM_FEATURE_EL2)) {
1026
1027
1028
1029
1030 cpu->isar.id_aa64pfr0 &= ~0xf00;
1031 cpu->id_pfr1 &= ~0xf000;
1032 }
1033
1034
1035
1036
1037 if (!cpu->has_mpu) {
1038 cpu->pmsav7_dregion = 0;
1039 }
1040 if (cpu->pmsav7_dregion == 0) {
1041 cpu->has_mpu = false;
1042 }
1043
1044 if (arm_feature(env, ARM_FEATURE_PMSA) &&
1045 arm_feature(env, ARM_FEATURE_V7)) {
1046 uint32_t nr = cpu->pmsav7_dregion;
1047
1048 if (nr > 0xff) {
1049 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
1050 return;
1051 }
1052
1053 if (nr) {
1054 if (arm_feature(env, ARM_FEATURE_V8)) {
1055
1056 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr);
1057 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr);
1058 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1059 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr);
1060 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
1061 }
1062 } else {
1063 env->pmsav7.drbar = g_new0(uint32_t, nr);
1064 env->pmsav7.drsr = g_new0(uint32_t, nr);
1065 env->pmsav7.dracr = g_new0(uint32_t, nr);
1066 }
1067 }
1068 }
1069
1070 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1071 uint32_t nr = cpu->sau_sregion;
1072
1073 if (nr > 0xff) {
1074 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr);
1075 return;
1076 }
1077
1078 if (nr) {
1079 env->sau.rbar = g_new0(uint32_t, nr);
1080 env->sau.rlar = g_new0(uint32_t, nr);
1081 }
1082 }
1083
1084 if (arm_feature(env, ARM_FEATURE_EL3)) {
1085 set_feature(env, ARM_FEATURE_VBAR);
1086 }
1087
1088 register_cp_regs_for_features(cpu);
1089 arm_cpu_register_gdb_regs_for_features(cpu);
1090
1091 init_cpreg_list(cpu);
1092
1093#ifndef CONFIG_USER_ONLY
1094 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1095 cs->num_ases = 2;
1096
1097 if (!cpu->secure_memory) {
1098 cpu->secure_memory = cs->memory;
1099 }
1100 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory",
1101 cpu->secure_memory);
1102 } else {
1103 cs->num_ases = 1;
1104 }
1105 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
1106
1107
1108 if (cpu->core_count == -1) {
1109 cpu->core_count = smp_cpus;
1110 }
1111#endif
1112
1113 qemu_init_vcpu(cs);
1114 cpu_reset(cs);
1115
1116 acc->parent_realize(dev, errp);
1117}
1118
1119static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
1120{
1121 ObjectClass *oc;
1122 char *typename;
1123 char **cpuname;
1124 const char *cpunamestr;
1125
1126 cpuname = g_strsplit(cpu_model, ",", 1);
1127 cpunamestr = cpuname[0];
1128#ifdef CONFIG_USER_ONLY
1129
1130
1131
1132 if (!strcmp(cpunamestr, "any")) {
1133 cpunamestr = "max";
1134 }
1135#endif
1136 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr);
1137 oc = object_class_by_name(typename);
1138 g_strfreev(cpuname);
1139 g_free(typename);
1140 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
1141 object_class_is_abstract(oc)) {
1142 return NULL;
1143 }
1144 return oc;
1145}
1146
1147
1148#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1149
1150static void arm926_initfn(Object *obj)
1151{
1152 ARMCPU *cpu = ARM_CPU(obj);
1153
1154 cpu->dtb_compatible = "arm,arm926";
1155 set_feature(&cpu->env, ARM_FEATURE_V5);
1156 set_feature(&cpu->env, ARM_FEATURE_VFP);
1157 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1158 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
1159 cpu->midr = 0x41069265;
1160 cpu->reset_fpsid = 0x41011090;
1161 cpu->ctr = 0x1dd20d2;
1162 cpu->reset_sctlr = 0x00090078;
1163
1164
1165
1166
1167
1168 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
1169}
1170
1171static void arm946_initfn(Object *obj)
1172{
1173 ARMCPU *cpu = ARM_CPU(obj);
1174
1175 cpu->dtb_compatible = "arm,arm946";
1176 set_feature(&cpu->env, ARM_FEATURE_V5);
1177 set_feature(&cpu->env, ARM_FEATURE_PMSA);
1178 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1179 cpu->midr = 0x41059461;
1180 cpu->ctr = 0x0f004006;
1181 cpu->reset_sctlr = 0x00000078;
1182}
1183
1184static void arm1026_initfn(Object *obj)
1185{
1186 ARMCPU *cpu = ARM_CPU(obj);
1187
1188 cpu->dtb_compatible = "arm,arm1026";
1189 set_feature(&cpu->env, ARM_FEATURE_V5);
1190 set_feature(&cpu->env, ARM_FEATURE_VFP);
1191 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
1192 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1193 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
1194 cpu->midr = 0x4106a262;
1195 cpu->reset_fpsid = 0x410110a0;
1196 cpu->ctr = 0x1dd20d2;
1197 cpu->reset_sctlr = 0x00090078;
1198 cpu->reset_auxcr = 1;
1199
1200
1201
1202
1203
1204 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
1205
1206 {
1207
1208 ARMCPRegInfo ifar = {
1209 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
1210 .access = PL1_RW,
1211 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
1212 .resetvalue = 0
1213 };
1214 define_one_arm_cp_reg(cpu, &ifar);
1215 }
1216}
1217
1218static void arm1136_r2_initfn(Object *obj)
1219{
1220 ARMCPU *cpu = ARM_CPU(obj);
1221
1222
1223
1224
1225
1226
1227
1228
1229 cpu->dtb_compatible = "arm,arm1136";
1230 set_feature(&cpu->env, ARM_FEATURE_V6);
1231 set_feature(&cpu->env, ARM_FEATURE_VFP);
1232 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1233 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1234 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1235 cpu->midr = 0x4107b362;
1236 cpu->reset_fpsid = 0x410120b4;
1237 cpu->isar.mvfr0 = 0x11111111;
1238 cpu->isar.mvfr1 = 0x00000000;
1239 cpu->ctr = 0x1dd20d2;
1240 cpu->reset_sctlr = 0x00050078;
1241 cpu->id_pfr0 = 0x111;
1242 cpu->id_pfr1 = 0x1;
1243 cpu->id_dfr0 = 0x2;
1244 cpu->id_afr0 = 0x3;
1245 cpu->id_mmfr0 = 0x01130003;
1246 cpu->id_mmfr1 = 0x10030302;
1247 cpu->id_mmfr2 = 0x01222110;
1248 cpu->isar.id_isar0 = 0x00140011;
1249 cpu->isar.id_isar1 = 0x12002111;
1250 cpu->isar.id_isar2 = 0x11231111;
1251 cpu->isar.id_isar3 = 0x01102131;
1252 cpu->isar.id_isar4 = 0x141;
1253 cpu->reset_auxcr = 7;
1254}
1255
1256static void arm1136_initfn(Object *obj)
1257{
1258 ARMCPU *cpu = ARM_CPU(obj);
1259
1260 cpu->dtb_compatible = "arm,arm1136";
1261 set_feature(&cpu->env, ARM_FEATURE_V6K);
1262 set_feature(&cpu->env, ARM_FEATURE_V6);
1263 set_feature(&cpu->env, ARM_FEATURE_VFP);
1264 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1265 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1266 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1267 cpu->midr = 0x4117b363;
1268 cpu->reset_fpsid = 0x410120b4;
1269 cpu->isar.mvfr0 = 0x11111111;
1270 cpu->isar.mvfr1 = 0x00000000;
1271 cpu->ctr = 0x1dd20d2;
1272 cpu->reset_sctlr = 0x00050078;
1273 cpu->id_pfr0 = 0x111;
1274 cpu->id_pfr1 = 0x1;
1275 cpu->id_dfr0 = 0x2;
1276 cpu->id_afr0 = 0x3;
1277 cpu->id_mmfr0 = 0x01130003;
1278 cpu->id_mmfr1 = 0x10030302;
1279 cpu->id_mmfr2 = 0x01222110;
1280 cpu->isar.id_isar0 = 0x00140011;
1281 cpu->isar.id_isar1 = 0x12002111;
1282 cpu->isar.id_isar2 = 0x11231111;
1283 cpu->isar.id_isar3 = 0x01102131;
1284 cpu->isar.id_isar4 = 0x141;
1285 cpu->reset_auxcr = 7;
1286}
1287
1288static void arm1176_initfn(Object *obj)
1289{
1290 ARMCPU *cpu = ARM_CPU(obj);
1291
1292 cpu->dtb_compatible = "arm,arm1176";
1293 set_feature(&cpu->env, ARM_FEATURE_V6K);
1294 set_feature(&cpu->env, ARM_FEATURE_VFP);
1295 set_feature(&cpu->env, ARM_FEATURE_VAPA);
1296 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1297 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1298 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1299 set_feature(&cpu->env, ARM_FEATURE_EL3);
1300 cpu->midr = 0x410fb767;
1301 cpu->reset_fpsid = 0x410120b5;
1302 cpu->isar.mvfr0 = 0x11111111;
1303 cpu->isar.mvfr1 = 0x00000000;
1304 cpu->ctr = 0x1dd20d2;
1305 cpu->reset_sctlr = 0x00050078;
1306 cpu->id_pfr0 = 0x111;
1307 cpu->id_pfr1 = 0x11;
1308 cpu->id_dfr0 = 0x33;
1309 cpu->id_afr0 = 0;
1310 cpu->id_mmfr0 = 0x01130003;
1311 cpu->id_mmfr1 = 0x10030302;
1312 cpu->id_mmfr2 = 0x01222100;
1313 cpu->isar.id_isar0 = 0x0140011;
1314 cpu->isar.id_isar1 = 0x12002111;
1315 cpu->isar.id_isar2 = 0x11231121;
1316 cpu->isar.id_isar3 = 0x01102131;
1317 cpu->isar.id_isar4 = 0x01141;
1318 cpu->reset_auxcr = 7;
1319}
1320
1321static void arm11mpcore_initfn(Object *obj)
1322{
1323 ARMCPU *cpu = ARM_CPU(obj);
1324
1325 cpu->dtb_compatible = "arm,arm11mpcore";
1326 set_feature(&cpu->env, ARM_FEATURE_V6K);
1327 set_feature(&cpu->env, ARM_FEATURE_VFP);
1328 set_feature(&cpu->env, ARM_FEATURE_VAPA);
1329 set_feature(&cpu->env, ARM_FEATURE_MPIDR);
1330 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1331 cpu->midr = 0x410fb022;
1332 cpu->reset_fpsid = 0x410120b4;
1333 cpu->isar.mvfr0 = 0x11111111;
1334 cpu->isar.mvfr1 = 0x00000000;
1335 cpu->ctr = 0x1d192992;
1336 cpu->id_pfr0 = 0x111;
1337 cpu->id_pfr1 = 0x1;
1338 cpu->id_dfr0 = 0;
1339 cpu->id_afr0 = 0x2;
1340 cpu->id_mmfr0 = 0x01100103;
1341 cpu->id_mmfr1 = 0x10020302;
1342 cpu->id_mmfr2 = 0x01222000;
1343 cpu->isar.id_isar0 = 0x00100011;
1344 cpu->isar.id_isar1 = 0x12002111;
1345 cpu->isar.id_isar2 = 0x11221011;
1346 cpu->isar.id_isar3 = 0x01102131;
1347 cpu->isar.id_isar4 = 0x141;
1348 cpu->reset_auxcr = 1;
1349}
1350
1351static void cortex_m0_initfn(Object *obj)
1352{
1353 ARMCPU *cpu = ARM_CPU(obj);
1354 set_feature(&cpu->env, ARM_FEATURE_V6);
1355 set_feature(&cpu->env, ARM_FEATURE_M);
1356
1357 cpu->midr = 0x410cc200;
1358}
1359
1360static void cortex_m3_initfn(Object *obj)
1361{
1362 ARMCPU *cpu = ARM_CPU(obj);
1363 set_feature(&cpu->env, ARM_FEATURE_V7);
1364 set_feature(&cpu->env, ARM_FEATURE_M);
1365 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1366 cpu->midr = 0x410fc231;
1367 cpu->pmsav7_dregion = 8;
1368 cpu->id_pfr0 = 0x00000030;
1369 cpu->id_pfr1 = 0x00000200;
1370 cpu->id_dfr0 = 0x00100000;
1371 cpu->id_afr0 = 0x00000000;
1372 cpu->id_mmfr0 = 0x00000030;
1373 cpu->id_mmfr1 = 0x00000000;
1374 cpu->id_mmfr2 = 0x00000000;
1375 cpu->id_mmfr3 = 0x00000000;
1376 cpu->isar.id_isar0 = 0x01141110;
1377 cpu->isar.id_isar1 = 0x02111000;
1378 cpu->isar.id_isar2 = 0x21112231;
1379 cpu->isar.id_isar3 = 0x01111110;
1380 cpu->isar.id_isar4 = 0x01310102;
1381 cpu->isar.id_isar5 = 0x00000000;
1382 cpu->isar.id_isar6 = 0x00000000;
1383}
1384
1385static void cortex_m4_initfn(Object *obj)
1386{
1387 ARMCPU *cpu = ARM_CPU(obj);
1388
1389 set_feature(&cpu->env, ARM_FEATURE_V7);
1390 set_feature(&cpu->env, ARM_FEATURE_M);
1391 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1392 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1393 cpu->midr = 0x410fc240;
1394 cpu->pmsav7_dregion = 8;
1395 cpu->id_pfr0 = 0x00000030;
1396 cpu->id_pfr1 = 0x00000200;
1397 cpu->id_dfr0 = 0x00100000;
1398 cpu->id_afr0 = 0x00000000;
1399 cpu->id_mmfr0 = 0x00000030;
1400 cpu->id_mmfr1 = 0x00000000;
1401 cpu->id_mmfr2 = 0x00000000;
1402 cpu->id_mmfr3 = 0x00000000;
1403 cpu->isar.id_isar0 = 0x01141110;
1404 cpu->isar.id_isar1 = 0x02111000;
1405 cpu->isar.id_isar2 = 0x21112231;
1406 cpu->isar.id_isar3 = 0x01111110;
1407 cpu->isar.id_isar4 = 0x01310102;
1408 cpu->isar.id_isar5 = 0x00000000;
1409 cpu->isar.id_isar6 = 0x00000000;
1410}
1411
1412static void cortex_m33_initfn(Object *obj)
1413{
1414 ARMCPU *cpu = ARM_CPU(obj);
1415
1416 set_feature(&cpu->env, ARM_FEATURE_V8);
1417 set_feature(&cpu->env, ARM_FEATURE_M);
1418 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1419 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
1420 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1421 cpu->midr = 0x410fd213;
1422 cpu->pmsav7_dregion = 16;
1423 cpu->sau_sregion = 8;
1424 cpu->id_pfr0 = 0x00000030;
1425 cpu->id_pfr1 = 0x00000210;
1426 cpu->id_dfr0 = 0x00200000;
1427 cpu->id_afr0 = 0x00000000;
1428 cpu->id_mmfr0 = 0x00101F40;
1429 cpu->id_mmfr1 = 0x00000000;
1430 cpu->id_mmfr2 = 0x01000000;
1431 cpu->id_mmfr3 = 0x00000000;
1432 cpu->isar.id_isar0 = 0x01101110;
1433 cpu->isar.id_isar1 = 0x02212000;
1434 cpu->isar.id_isar2 = 0x20232232;
1435 cpu->isar.id_isar3 = 0x01111131;
1436 cpu->isar.id_isar4 = 0x01310132;
1437 cpu->isar.id_isar5 = 0x00000000;
1438 cpu->isar.id_isar6 = 0x00000000;
1439 cpu->clidr = 0x00000000;
1440 cpu->ctr = 0x8000c000;
1441}
1442
1443static void arm_v7m_class_init(ObjectClass *oc, void *data)
1444{
1445 CPUClass *cc = CPU_CLASS(oc);
1446
1447#ifndef CONFIG_USER_ONLY
1448 cc->do_interrupt = arm_v7m_cpu_do_interrupt;
1449#endif
1450
1451 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
1452}
1453
1454static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
1455
1456 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1457 .access = PL1_RW, .type = ARM_CP_CONST },
1458 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1459 .access = PL1_RW, .type = ARM_CP_CONST },
1460 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
1461 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
1462 REGINFO_SENTINEL
1463};
1464
1465static void cortex_r5_initfn(Object *obj)
1466{
1467 ARMCPU *cpu = ARM_CPU(obj);
1468
1469 set_feature(&cpu->env, ARM_FEATURE_V7);
1470 set_feature(&cpu->env, ARM_FEATURE_V7MP);
1471 set_feature(&cpu->env, ARM_FEATURE_PMSA);
1472 cpu->midr = 0x411fc153;
1473 cpu->id_pfr0 = 0x0131;
1474 cpu->id_pfr1 = 0x001;
1475 cpu->id_dfr0 = 0x010400;
1476 cpu->id_afr0 = 0x0;
1477 cpu->id_mmfr0 = 0x0210030;
1478 cpu->id_mmfr1 = 0x00000000;
1479 cpu->id_mmfr2 = 0x01200000;
1480 cpu->id_mmfr3 = 0x0211;
1481 cpu->isar.id_isar0 = 0x02101111;
1482 cpu->isar.id_isar1 = 0x13112111;
1483 cpu->isar.id_isar2 = 0x21232141;
1484 cpu->isar.id_isar3 = 0x01112131;
1485 cpu->isar.id_isar4 = 0x0010142;
1486 cpu->isar.id_isar5 = 0x0;
1487 cpu->isar.id_isar6 = 0x0;
1488 cpu->mp_is_up = true;
1489 cpu->pmsav7_dregion = 16;
1490 define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
1491}
1492
1493static void cortex_r5f_initfn(Object *obj)
1494{
1495 ARMCPU *cpu = ARM_CPU(obj);
1496
1497 cortex_r5_initfn(obj);
1498 set_feature(&cpu->env, ARM_FEATURE_VFP3);
1499}
1500
1501static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
1502 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
1503 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1504 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1505 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1506 REGINFO_SENTINEL
1507};
1508
1509static void cortex_a8_initfn(Object *obj)
1510{
1511 ARMCPU *cpu = ARM_CPU(obj);
1512
1513 cpu->dtb_compatible = "arm,cortex-a8";
1514 set_feature(&cpu->env, ARM_FEATURE_V7);
1515 set_feature(&cpu->env, ARM_FEATURE_VFP3);
1516 set_feature(&cpu->env, ARM_FEATURE_NEON);
1517 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1518 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1519 set_feature(&cpu->env, ARM_FEATURE_EL3);
1520 cpu->midr = 0x410fc080;
1521 cpu->reset_fpsid = 0x410330c0;
1522 cpu->isar.mvfr0 = 0x11110222;
1523 cpu->isar.mvfr1 = 0x00011111;
1524 cpu->ctr = 0x82048004;
1525 cpu->reset_sctlr = 0x00c50078;
1526 cpu->id_pfr0 = 0x1031;
1527 cpu->id_pfr1 = 0x11;
1528 cpu->id_dfr0 = 0x400;
1529 cpu->id_afr0 = 0;
1530 cpu->id_mmfr0 = 0x31100003;
1531 cpu->id_mmfr1 = 0x20000000;
1532 cpu->id_mmfr2 = 0x01202000;
1533 cpu->id_mmfr3 = 0x11;
1534 cpu->isar.id_isar0 = 0x00101111;
1535 cpu->isar.id_isar1 = 0x12112111;
1536 cpu->isar.id_isar2 = 0x21232031;
1537 cpu->isar.id_isar3 = 0x11112131;
1538 cpu->isar.id_isar4 = 0x00111142;
1539 cpu->dbgdidr = 0x15141000;
1540 cpu->clidr = (1 << 27) | (2 << 24) | 3;
1541 cpu->ccsidr[0] = 0xe007e01a;
1542 cpu->ccsidr[1] = 0x2007e01a;
1543 cpu->ccsidr[2] = 0xf0000000;
1544 cpu->reset_auxcr = 2;
1545 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
1546}
1547
1548static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
1549
1550
1551
1552 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1553 .access = PL1_RW, .resetvalue = 0,
1554 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
1555 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
1556 .access = PL1_RW, .resetvalue = 0,
1557 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
1558 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
1559 .access = PL1_RW, .resetvalue = 0,
1560 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
1561 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1562 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1563
1564 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
1565 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1566 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
1567 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1568 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
1569 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1570 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
1571 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1572 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
1573 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1574 REGINFO_SENTINEL
1575};
1576
1577static void cortex_a9_initfn(Object *obj)
1578{
1579 ARMCPU *cpu = ARM_CPU(obj);
1580
1581 cpu->dtb_compatible = "arm,cortex-a9";
1582 set_feature(&cpu->env, ARM_FEATURE_V7);
1583 set_feature(&cpu->env, ARM_FEATURE_VFP3);
1584 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
1585 set_feature(&cpu->env, ARM_FEATURE_NEON);
1586 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1587 set_feature(&cpu->env, ARM_FEATURE_EL3);
1588
1589
1590
1591
1592 set_feature(&cpu->env, ARM_FEATURE_V7MP);
1593 set_feature(&cpu->env, ARM_FEATURE_CBAR);
1594 cpu->midr = 0x410fc090;
1595 cpu->reset_fpsid = 0x41033090;
1596 cpu->isar.mvfr0 = 0x11110222;
1597 cpu->isar.mvfr1 = 0x01111111;
1598 cpu->ctr = 0x80038003;
1599 cpu->reset_sctlr = 0x00c50078;
1600 cpu->id_pfr0 = 0x1031;
1601 cpu->id_pfr1 = 0x11;
1602 cpu->id_dfr0 = 0x000;
1603 cpu->id_afr0 = 0;
1604 cpu->id_mmfr0 = 0x00100103;
1605 cpu->id_mmfr1 = 0x20000000;
1606 cpu->id_mmfr2 = 0x01230000;
1607 cpu->id_mmfr3 = 0x00002111;
1608 cpu->isar.id_isar0 = 0x00101111;
1609 cpu->isar.id_isar1 = 0x13112111;
1610 cpu->isar.id_isar2 = 0x21232041;
1611 cpu->isar.id_isar3 = 0x11112131;
1612 cpu->isar.id_isar4 = 0x00111142;
1613 cpu->dbgdidr = 0x35141000;
1614 cpu->clidr = (1 << 27) | (1 << 24) | 3;
1615 cpu->ccsidr[0] = 0xe00fe019;
1616 cpu->ccsidr[1] = 0x200fe019;
1617 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
1618}
1619
1620#ifndef CONFIG_USER_ONLY
1621static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1622{
1623
1624
1625
1626 return ((smp_cpus - 1) << 24) | (1 << 23);
1627}
1628#endif
1629
1630static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
1631#ifndef CONFIG_USER_ONLY
1632 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1633 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
1634 .writefn = arm_cp_write_ignore, },
1635#endif
1636 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
1637 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1638 REGINFO_SENTINEL
1639};
1640
1641static void cortex_a7_initfn(Object *obj)
1642{
1643 ARMCPU *cpu = ARM_CPU(obj);
1644
1645 cpu->dtb_compatible = "arm,cortex-a7";
1646 set_feature(&cpu->env, ARM_FEATURE_V7VE);
1647 set_feature(&cpu->env, ARM_FEATURE_VFP4);
1648 set_feature(&cpu->env, ARM_FEATURE_NEON);
1649 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1650 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1651 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1652 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1653 set_feature(&cpu->env, ARM_FEATURE_EL2);
1654 set_feature(&cpu->env, ARM_FEATURE_EL3);
1655 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
1656 cpu->midr = 0x410fc075;
1657 cpu->reset_fpsid = 0x41023075;
1658 cpu->isar.mvfr0 = 0x10110222;
1659 cpu->isar.mvfr1 = 0x11111111;
1660 cpu->ctr = 0x84448003;
1661 cpu->reset_sctlr = 0x00c50078;
1662 cpu->id_pfr0 = 0x00001131;
1663 cpu->id_pfr1 = 0x00011011;
1664 cpu->id_dfr0 = 0x02010555;
1665 cpu->pmceid0 = 0x00000000;
1666 cpu->pmceid1 = 0x00000000;
1667 cpu->id_afr0 = 0x00000000;
1668 cpu->id_mmfr0 = 0x10101105;
1669 cpu->id_mmfr1 = 0x40000000;
1670 cpu->id_mmfr2 = 0x01240000;
1671 cpu->id_mmfr3 = 0x02102211;
1672
1673
1674
1675 cpu->isar.id_isar0 = 0x02101110;
1676 cpu->isar.id_isar1 = 0x13112111;
1677 cpu->isar.id_isar2 = 0x21232041;
1678 cpu->isar.id_isar3 = 0x11112131;
1679 cpu->isar.id_isar4 = 0x10011142;
1680 cpu->dbgdidr = 0x3515f005;
1681 cpu->clidr = 0x0a200023;
1682 cpu->ccsidr[0] = 0x701fe00a;
1683 cpu->ccsidr[1] = 0x201fe00a;
1684 cpu->ccsidr[2] = 0x711fe07a;
1685 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
1686}
1687
1688static void cortex_a15_initfn(Object *obj)
1689{
1690 ARMCPU *cpu = ARM_CPU(obj);
1691
1692 cpu->dtb_compatible = "arm,cortex-a15";
1693 set_feature(&cpu->env, ARM_FEATURE_V7VE);
1694 set_feature(&cpu->env, ARM_FEATURE_VFP4);
1695 set_feature(&cpu->env, ARM_FEATURE_NEON);
1696 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1697 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1698 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1699 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1700 set_feature(&cpu->env, ARM_FEATURE_EL2);
1701 set_feature(&cpu->env, ARM_FEATURE_EL3);
1702 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
1703 cpu->midr = 0x412fc0f1;
1704 cpu->reset_fpsid = 0x410430f0;
1705 cpu->isar.mvfr0 = 0x10110222;
1706 cpu->isar.mvfr1 = 0x11111111;
1707 cpu->ctr = 0x8444c004;
1708 cpu->reset_sctlr = 0x00c50078;
1709 cpu->id_pfr0 = 0x00001131;
1710 cpu->id_pfr1 = 0x00011011;
1711 cpu->id_dfr0 = 0x02010555;
1712 cpu->pmceid0 = 0x0000000;
1713 cpu->pmceid1 = 0x00000000;
1714 cpu->id_afr0 = 0x00000000;
1715 cpu->id_mmfr0 = 0x10201105;
1716 cpu->id_mmfr1 = 0x20000000;
1717 cpu->id_mmfr2 = 0x01240000;
1718 cpu->id_mmfr3 = 0x02102211;
1719 cpu->isar.id_isar0 = 0x02101110;
1720 cpu->isar.id_isar1 = 0x13112111;
1721 cpu->isar.id_isar2 = 0x21232041;
1722 cpu->isar.id_isar3 = 0x11112131;
1723 cpu->isar.id_isar4 = 0x10011142;
1724 cpu->dbgdidr = 0x3515f021;
1725 cpu->clidr = 0x0a200023;
1726 cpu->ccsidr[0] = 0x701fe00a;
1727 cpu->ccsidr[1] = 0x201fe00a;
1728 cpu->ccsidr[2] = 0x711fe07a;
1729 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
1730}
1731
1732static void ti925t_initfn(Object *obj)
1733{
1734 ARMCPU *cpu = ARM_CPU(obj);
1735 set_feature(&cpu->env, ARM_FEATURE_V4T);
1736 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
1737 cpu->midr = ARM_CPUID_TI925T;
1738 cpu->ctr = 0x5109149;
1739 cpu->reset_sctlr = 0x00000070;
1740}
1741
1742static void sa1100_initfn(Object *obj)
1743{
1744 ARMCPU *cpu = ARM_CPU(obj);
1745
1746 cpu->dtb_compatible = "intel,sa1100";
1747 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1748 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1749 cpu->midr = 0x4401A11B;
1750 cpu->reset_sctlr = 0x00000070;
1751}
1752
1753static void sa1110_initfn(Object *obj)
1754{
1755 ARMCPU *cpu = ARM_CPU(obj);
1756 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1757 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1758 cpu->midr = 0x6901B119;
1759 cpu->reset_sctlr = 0x00000070;
1760}
1761
1762static void pxa250_initfn(Object *obj)
1763{
1764 ARMCPU *cpu = ARM_CPU(obj);
1765
1766 cpu->dtb_compatible = "marvell,xscale";
1767 set_feature(&cpu->env, ARM_FEATURE_V5);
1768 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1769 cpu->midr = 0x69052100;
1770 cpu->ctr = 0xd172172;
1771 cpu->reset_sctlr = 0x00000078;
1772}
1773
1774static void pxa255_initfn(Object *obj)
1775{
1776 ARMCPU *cpu = ARM_CPU(obj);
1777
1778 cpu->dtb_compatible = "marvell,xscale";
1779 set_feature(&cpu->env, ARM_FEATURE_V5);
1780 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1781 cpu->midr = 0x69052d00;
1782 cpu->ctr = 0xd172172;
1783 cpu->reset_sctlr = 0x00000078;
1784}
1785
1786static void pxa260_initfn(Object *obj)
1787{
1788 ARMCPU *cpu = ARM_CPU(obj);
1789
1790 cpu->dtb_compatible = "marvell,xscale";
1791 set_feature(&cpu->env, ARM_FEATURE_V5);
1792 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1793 cpu->midr = 0x69052903;
1794 cpu->ctr = 0xd172172;
1795 cpu->reset_sctlr = 0x00000078;
1796}
1797
1798static void pxa261_initfn(Object *obj)
1799{
1800 ARMCPU *cpu = ARM_CPU(obj);
1801
1802 cpu->dtb_compatible = "marvell,xscale";
1803 set_feature(&cpu->env, ARM_FEATURE_V5);
1804 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1805 cpu->midr = 0x69052d05;
1806 cpu->ctr = 0xd172172;
1807 cpu->reset_sctlr = 0x00000078;
1808}
1809
1810static void pxa262_initfn(Object *obj)
1811{
1812 ARMCPU *cpu = ARM_CPU(obj);
1813
1814 cpu->dtb_compatible = "marvell,xscale";
1815 set_feature(&cpu->env, ARM_FEATURE_V5);
1816 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1817 cpu->midr = 0x69052d06;
1818 cpu->ctr = 0xd172172;
1819 cpu->reset_sctlr = 0x00000078;
1820}
1821
1822static void pxa270a0_initfn(Object *obj)
1823{
1824 ARMCPU *cpu = ARM_CPU(obj);
1825
1826 cpu->dtb_compatible = "marvell,xscale";
1827 set_feature(&cpu->env, ARM_FEATURE_V5);
1828 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1829 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1830 cpu->midr = 0x69054110;
1831 cpu->ctr = 0xd172172;
1832 cpu->reset_sctlr = 0x00000078;
1833}
1834
1835static void pxa270a1_initfn(Object *obj)
1836{
1837 ARMCPU *cpu = ARM_CPU(obj);
1838
1839 cpu->dtb_compatible = "marvell,xscale";
1840 set_feature(&cpu->env, ARM_FEATURE_V5);
1841 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1842 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1843 cpu->midr = 0x69054111;
1844 cpu->ctr = 0xd172172;
1845 cpu->reset_sctlr = 0x00000078;
1846}
1847
1848static void pxa270b0_initfn(Object *obj)
1849{
1850 ARMCPU *cpu = ARM_CPU(obj);
1851
1852 cpu->dtb_compatible = "marvell,xscale";
1853 set_feature(&cpu->env, ARM_FEATURE_V5);
1854 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1855 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1856 cpu->midr = 0x69054112;
1857 cpu->ctr = 0xd172172;
1858 cpu->reset_sctlr = 0x00000078;
1859}
1860
1861static void pxa270b1_initfn(Object *obj)
1862{
1863 ARMCPU *cpu = ARM_CPU(obj);
1864
1865 cpu->dtb_compatible = "marvell,xscale";
1866 set_feature(&cpu->env, ARM_FEATURE_V5);
1867 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1868 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1869 cpu->midr = 0x69054113;
1870 cpu->ctr = 0xd172172;
1871 cpu->reset_sctlr = 0x00000078;
1872}
1873
1874static void pxa270c0_initfn(Object *obj)
1875{
1876 ARMCPU *cpu = ARM_CPU(obj);
1877
1878 cpu->dtb_compatible = "marvell,xscale";
1879 set_feature(&cpu->env, ARM_FEATURE_V5);
1880 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1881 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1882 cpu->midr = 0x69054114;
1883 cpu->ctr = 0xd172172;
1884 cpu->reset_sctlr = 0x00000078;
1885}
1886
1887static void pxa270c5_initfn(Object *obj)
1888{
1889 ARMCPU *cpu = ARM_CPU(obj);
1890
1891 cpu->dtb_compatible = "marvell,xscale";
1892 set_feature(&cpu->env, ARM_FEATURE_V5);
1893 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1894 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1895 cpu->midr = 0x69054117;
1896 cpu->ctr = 0xd172172;
1897 cpu->reset_sctlr = 0x00000078;
1898}
1899
1900#ifndef TARGET_AARCH64
1901
1902
1903
1904
1905
1906static void arm_max_initfn(Object *obj)
1907{
1908 ARMCPU *cpu = ARM_CPU(obj);
1909
1910 if (kvm_enabled()) {
1911 kvm_arm_set_cpu_features_from_host(cpu);
1912 } else {
1913 cortex_a15_initfn(obj);
1914#ifdef CONFIG_USER_ONLY
1915
1916
1917
1918
1919 set_feature(&cpu->env, ARM_FEATURE_V8);
1920 {
1921 uint32_t t;
1922
1923 t = cpu->isar.id_isar5;
1924 t = FIELD_DP32(t, ID_ISAR5, AES, 2);
1925 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
1926 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
1927 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
1928 t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
1929 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
1930 cpu->isar.id_isar5 = t;
1931
1932 t = cpu->isar.id_isar6;
1933 t = FIELD_DP32(t, ID_ISAR6, DP, 1);
1934 cpu->isar.id_isar6 = t;
1935 }
1936#endif
1937 }
1938}
1939#endif
1940
1941#endif
1942
1943typedef struct ARMCPUInfo {
1944 const char *name;
1945 void (*initfn)(Object *obj);
1946 void (*class_init)(ObjectClass *oc, void *data);
1947} ARMCPUInfo;
1948
1949static const ARMCPUInfo arm_cpus[] = {
1950#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1951 { .name = "arm926", .initfn = arm926_initfn },
1952 { .name = "arm946", .initfn = arm946_initfn },
1953 { .name = "arm1026", .initfn = arm1026_initfn },
1954
1955
1956
1957
1958 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
1959 { .name = "arm1136", .initfn = arm1136_initfn },
1960 { .name = "arm1176", .initfn = arm1176_initfn },
1961 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1962 { .name = "cortex-m0", .initfn = cortex_m0_initfn,
1963 .class_init = arm_v7m_class_init },
1964 { .name = "cortex-m3", .initfn = cortex_m3_initfn,
1965 .class_init = arm_v7m_class_init },
1966 { .name = "cortex-m4", .initfn = cortex_m4_initfn,
1967 .class_init = arm_v7m_class_init },
1968 { .name = "cortex-m33", .initfn = cortex_m33_initfn,
1969 .class_init = arm_v7m_class_init },
1970 { .name = "cortex-r5", .initfn = cortex_r5_initfn },
1971 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
1972 { .name = "cortex-a7", .initfn = cortex_a7_initfn },
1973 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
1974 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
1975 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
1976 { .name = "ti925t", .initfn = ti925t_initfn },
1977 { .name = "sa1100", .initfn = sa1100_initfn },
1978 { .name = "sa1110", .initfn = sa1110_initfn },
1979 { .name = "pxa250", .initfn = pxa250_initfn },
1980 { .name = "pxa255", .initfn = pxa255_initfn },
1981 { .name = "pxa260", .initfn = pxa260_initfn },
1982 { .name = "pxa261", .initfn = pxa261_initfn },
1983 { .name = "pxa262", .initfn = pxa262_initfn },
1984
1985 { .name = "pxa270", .initfn = pxa270a0_initfn },
1986 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
1987 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
1988 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
1989 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
1990 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
1991 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
1992#ifndef TARGET_AARCH64
1993 { .name = "max", .initfn = arm_max_initfn },
1994#endif
1995#ifdef CONFIG_USER_ONLY
1996 { .name = "any", .initfn = arm_max_initfn },
1997#endif
1998#endif
1999 { .name = NULL }
2000};
2001
2002static Property arm_cpu_properties[] = {
2003 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
2004 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
2005 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
2006 DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
2007 mp_affinity, ARM64_AFFINITY_INVALID),
2008 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
2009 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
2010 DEFINE_PROP_END_OF_LIST()
2011};
2012
2013#ifdef CONFIG_USER_ONLY
2014static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
2015 int rw, int mmu_idx)
2016{
2017 ARMCPU *cpu = ARM_CPU(cs);
2018 CPUARMState *env = &cpu->env;
2019
2020 env->exception.vaddress = address;
2021 if (rw == 2) {
2022 cs->exception_index = EXCP_PREFETCH_ABORT;
2023 } else {
2024 cs->exception_index = EXCP_DATA_ABORT;
2025 }
2026 return 1;
2027}
2028#endif
2029
2030static gchar *arm_gdb_arch_name(CPUState *cs)
2031{
2032 ARMCPU *cpu = ARM_CPU(cs);
2033 CPUARMState *env = &cpu->env;
2034
2035 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
2036 return g_strdup("iwmmxt");
2037 }
2038 return g_strdup("arm");
2039}
2040
2041static void arm_cpu_class_init(ObjectClass *oc, void *data)
2042{
2043 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2044 CPUClass *cc = CPU_CLASS(acc);
2045 DeviceClass *dc = DEVICE_CLASS(oc);
2046
2047 device_class_set_parent_realize(dc, arm_cpu_realizefn,
2048 &acc->parent_realize);
2049 dc->props = arm_cpu_properties;
2050
2051 acc->parent_reset = cc->reset;
2052 cc->reset = arm_cpu_reset;
2053
2054 cc->class_by_name = arm_cpu_class_by_name;
2055 cc->has_work = arm_cpu_has_work;
2056 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
2057 cc->dump_state = arm_cpu_dump_state;
2058 cc->set_pc = arm_cpu_set_pc;
2059 cc->gdb_read_register = arm_cpu_gdb_read_register;
2060 cc->gdb_write_register = arm_cpu_gdb_write_register;
2061#ifdef CONFIG_USER_ONLY
2062 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
2063#else
2064 cc->do_interrupt = arm_cpu_do_interrupt;
2065 cc->do_unaligned_access = arm_cpu_do_unaligned_access;
2066 cc->do_transaction_failed = arm_cpu_do_transaction_failed;
2067 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
2068 cc->asidx_from_attrs = arm_asidx_from_attrs;
2069 cc->vmsd = &vmstate_arm_cpu;
2070 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
2071 cc->write_elf64_note = arm_cpu_write_elf64_note;
2072 cc->write_elf32_note = arm_cpu_write_elf32_note;
2073#endif
2074 cc->gdb_num_core_regs = 26;
2075 cc->gdb_core_xml_file = "arm-core.xml";
2076 cc->gdb_arch_name = arm_gdb_arch_name;
2077 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml;
2078 cc->gdb_stop_before_watchpoint = true;
2079 cc->debug_excp_handler = arm_debug_excp_handler;
2080 cc->debug_check_watchpoint = arm_debug_check_watchpoint;
2081#if !defined(CONFIG_USER_ONLY)
2082 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
2083#endif
2084
2085 cc->disas_set_info = arm_disas_set_info;
2086#ifdef CONFIG_TCG
2087 cc->tcg_initialize = arm_translate_init;
2088#endif
2089}
2090
2091#ifdef CONFIG_KVM
2092static void arm_host_initfn(Object *obj)
2093{
2094 ARMCPU *cpu = ARM_CPU(obj);
2095
2096 kvm_arm_set_cpu_features_from_host(cpu);
2097}
2098
2099static const TypeInfo host_arm_cpu_type_info = {
2100 .name = TYPE_ARM_HOST_CPU,
2101#ifdef TARGET_AARCH64
2102 .parent = TYPE_AARCH64_CPU,
2103#else
2104 .parent = TYPE_ARM_CPU,
2105#endif
2106 .instance_init = arm_host_initfn,
2107};
2108
2109#endif
2110
2111static void cpu_register(const ARMCPUInfo *info)
2112{
2113 TypeInfo type_info = {
2114 .parent = TYPE_ARM_CPU,
2115 .instance_size = sizeof(ARMCPU),
2116 .instance_init = info->initfn,
2117 .class_size = sizeof(ARMCPUClass),
2118 .class_init = info->class_init,
2119 };
2120
2121 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
2122 type_register(&type_info);
2123 g_free((void *)type_info.name);
2124}
2125
2126static const TypeInfo arm_cpu_type_info = {
2127 .name = TYPE_ARM_CPU,
2128 .parent = TYPE_CPU,
2129 .instance_size = sizeof(ARMCPU),
2130 .instance_init = arm_cpu_initfn,
2131 .instance_post_init = arm_cpu_post_init,
2132 .instance_finalize = arm_cpu_finalizefn,
2133 .abstract = true,
2134 .class_size = sizeof(ARMCPUClass),
2135 .class_init = arm_cpu_class_init,
2136};
2137
2138static const TypeInfo idau_interface_type_info = {
2139 .name = TYPE_IDAU_INTERFACE,
2140 .parent = TYPE_INTERFACE,
2141 .class_size = sizeof(IDAUInterfaceClass),
2142};
2143
2144static void arm_cpu_register_types(void)
2145{
2146 const ARMCPUInfo *info = arm_cpus;
2147
2148 type_register_static(&arm_cpu_type_info);
2149 type_register_static(&idau_interface_type_info);
2150
2151 while (info->name) {
2152 cpu_register(info);
2153 info++;
2154 }
2155
2156#ifdef CONFIG_KVM
2157 type_register_static(&host_arm_cpu_type_info);
2158#endif
2159}
2160
2161type_init(arm_cpu_register_types)
2162