LXR qemu/target/arm/translate.h

   1#ifndef TARGET_ARM_TRANSLATE_H
   2#define TARGET_ARM_TRANSLATE_H
   3
   4#include "exec/translator.h"
   5
   6
   7/* internal defines */
   8typedef struct DisasContext {
   9    DisasContextBase base;
  10    const ARMISARegisters *isar;
  11
  12    target_ulong pc;
  13    target_ulong page_start;
  14    uint32_t insn;
  15    /* Nonzero if this instruction has been conditionally skipped.  */
  16    int condjmp;
  17    /* The label that will be jumped to when the instruction is skipped.  */
  18    TCGLabel *condlabel;
  19    /* Thumb-2 conditional execution bits.  */
  20    int condexec_mask;
  21    int condexec_cond;
  22    int thumb;
  23    int sctlr_b;
  24    TCGMemOp be_data;
  25#if !defined(CONFIG_USER_ONLY)
  26    int user;
  27#endif
  28    ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
  29    bool tbi0;         /* TBI0 for EL0/1 or TBI for EL2/3 */
  30    bool tbi1;         /* TBI1 for EL0/1, not used for EL2/3 */
  31    bool ns;        /* Use non-secure CPREG bank on access */
  32    int fp_excp_el; /* FP exception EL or 0 if enabled */
  33    int sve_excp_el; /* SVE exception EL or 0 if enabled */
  34    int sve_len;     /* SVE vector length in bytes */
  35    /* Flag indicating that exceptions from secure mode are routed to EL3. */
  36    bool secure_routed_to_el3;
  37    bool vfp_enabled; /* FP enabled via FPSCR.EN */
  38    int vec_len;
  39    int vec_stride;
  40    bool v7m_handler_mode;
  41    bool v8m_secure; /* true if v8M and we're in Secure mode */
  42    bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */
  43    /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
  44     * so that top level loop can generate correct syndrome information.
  45     */
  46    uint32_t svc_imm;
  47    int aarch64;
  48    int current_el;
  49    GHashTable *cp_regs;
  50    uint64_t features; /* CPU features bits */
  51    /* Because unallocated encodings generate different exception syndrome
  52     * information from traps due to FP being disabled, we can't do a single
  53     * "is fp access disabled" check at a high level in the decode tree.
  54     * To help in catching bugs where the access check was forgotten in some
  55     * code path, we set this flag when the access check is done, and assert
  56     * that it is set at the point where we actually touch the FP regs.
  57     */
  58    bool fp_access_checked;
  59    /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
  60     * single-step support).
  61     */
  62    bool ss_active;
  63    bool pstate_ss;
  64    /* True if the insn just emitted was a load-exclusive instruction
  65     * (necessary for syndrome information for single step exceptions),
  66     * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
  67     */
  68    bool is_ldex;
  69    /* True if a single-step exception will be taken to the current EL */
  70    bool ss_same_el;
  71    /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
  72    int c15_cpar;
  73    /* TCG op of the current insn_start.  */
  74    TCGOp *insn_start;
  75#define TMP_A64_MAX 16
  76    int tmp_a64_count;
  77    TCGv_i64 tmp_a64[TMP_A64_MAX];
  78} DisasContext;
  79
  80typedef struct DisasCompare {
  81    TCGCond cond;
  82    TCGv_i32 value;
  83    bool value_global;
  84} DisasCompare;
  85
  86/* Share the TCG temporaries common between 32 and 64 bit modes.  */
  87extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
  88extern TCGv_i64 cpu_exclusive_addr;
  89extern TCGv_i64 cpu_exclusive_val;
  90
  91static inline int arm_dc_feature(DisasContext *dc, int feature)
  92{
  93    return (dc->features & (1ULL << feature)) != 0;
  94}
  95
  96static inline int get_mem_index(DisasContext *s)
  97{
  98    return arm_to_core_mmu_idx(s->mmu_idx);
  99}
 100
 101/* Function used to determine the target exception EL when otherwise not known
 102 * or default.
 103 */
 104static inline int default_exception_el(DisasContext *s)
 105{
 106    /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
 107     * there is no secure EL1, so we route exceptions to EL3.  Otherwise,
 108     * exceptions can only be routed to ELs above 1, so we target the higher of
 109     * 1 or the current EL.
 110     */
 111    return (s->mmu_idx == ARMMMUIdx_S1SE0 && s->secure_routed_to_el3)
 112            ? 3 : MAX(1, s->current_el);
 113}
 114
 115static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
 116{
 117    /* We don't need to save all of the syndrome so we mask and shift
 118     * out unneeded bits to help the sleb128 encoder do a better job.
 119     */
 120    syn &= ARM_INSN_START_WORD2_MASK;
 121    syn >>= ARM_INSN_START_WORD2_SHIFT;
 122
 123    /* We check and clear insn_start_idx to catch multiple updates.  */
 124    assert(s->insn_start != NULL);
 125    tcg_set_insn_start_param(s->insn_start, 2, syn);
 126    s->insn_start = NULL;
 127}
 128
 129/* is_jmp field values */
 130#define DISAS_JUMP      DISAS_TARGET_0 /* only pc was modified dynamically */
 131#define DISAS_UPDATE    DISAS_TARGET_1 /* cpu state was modified dynamically */
 132/* These instructions trap after executing, so the A32/T32 decoder must
 133 * defer them until after the conditional execution state has been updated.
 134 * WFI also needs special handling when single-stepping.
 135 */
 136#define DISAS_WFI       DISAS_TARGET_2
 137#define DISAS_SWI       DISAS_TARGET_3
 138/* WFE */
 139#define DISAS_WFE       DISAS_TARGET_4
 140#define DISAS_HVC       DISAS_TARGET_5
 141#define DISAS_SMC       DISAS_TARGET_6
 142#define DISAS_YIELD     DISAS_TARGET_7
 143/* M profile branch which might be an exception return (and so needs
 144 * custom end-of-TB code)
 145 */
 146#define DISAS_BX_EXCRET DISAS_TARGET_8
 147/* For instructions which want an immediate exit to the main loop,
 148 * as opposed to attempting to use lookup_and_goto_ptr. Unlike
 149 * DISAS_UPDATE this doesn't write the PC on exiting the translation
 150 * loop so you need to ensure something (gen_a64_set_pc_im or runtime
 151 * helper) has done so before we reach return from cpu_tb_exec.
 152 */
 153#define DISAS_EXIT      DISAS_TARGET_9
 154
 155#ifdef TARGET_AARCH64
 156void a64_translate_init(void);
 157void gen_a64_set_pc_im(uint64_t val);
 158void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
 159                            fprintf_function cpu_fprintf, int flags);
 160extern const TranslatorOps aarch64_translator_ops;
 161#else
 162static inline void a64_translate_init(void)
 163{
 164}
 165
 166static inline void gen_a64_set_pc_im(uint64_t val)
 167{
 168}
 169
 170static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
 171                                          fprintf_function cpu_fprintf,
 172                                          int flags)
 173{
 174}
 175#endif
 176
 177void arm_test_cc(DisasCompare *cmp, int cc);
 178void arm_free_cc(DisasCompare *cmp);
 179void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
 180void arm_gen_test_cc(int cc, TCGLabel *label);
 181
 182/* Return state of Alternate Half-precision flag, caller frees result */
 183static inline TCGv_i32 get_ahp_flag(void)
 184{
 185    TCGv_i32 ret = tcg_temp_new_i32();
 186
 187    tcg_gen_ld_i32(ret, cpu_env,
 188                   offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
 189    tcg_gen_extract_i32(ret, ret, 26, 1);
 190
 191    return ret;
 192}
 193
 194
 195/* Vector operations shared between ARM and AArch64.  */
 196extern const GVecGen3 bsl_op;
 197extern const GVecGen3 bit_op;
 198extern const GVecGen3 bif_op;
 199extern const GVecGen3 mla_op[4];
 200extern const GVecGen3 mls_op[4];
 201extern const GVecGen3 cmtst_op[4];
 202extern const GVecGen2i ssra_op[4];
 203extern const GVecGen2i usra_op[4];
 204extern const GVecGen2i sri_op[4];
 205extern const GVecGen2i sli_op[4];
 206void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
 207
 208/*
 209 * Forward to the isar_feature_* tests given a DisasContext pointer.
 210 */
 211#define dc_isar_feature(name, ctx) \
 212    ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
 213
 214#endif /* TARGET_ARM_TRANSLATE_H */
 215