LXR qemu/target/hppa/cpu.h

   1/*
   2 * PA-RISC emulation cpu definitions for qemu.
   3 *
   4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#ifndef HPPA_CPU_H
  21#define HPPA_CPU_H
  22
  23#include "qemu-common.h"
  24#include "cpu-qom.h"
  25
  26#ifdef TARGET_HPPA64
  27#define TARGET_LONG_BITS            64
  28#define TARGET_VIRT_ADDR_SPACE_BITS 64
  29#define TARGET_REGISTER_BITS        64
  30#define TARGET_PHYS_ADDR_SPACE_BITS 64
  31#elif defined(CONFIG_USER_ONLY)
  32#define TARGET_LONG_BITS            32
  33#define TARGET_VIRT_ADDR_SPACE_BITS 32
  34#define TARGET_REGISTER_BITS        32
  35#define TARGET_PHYS_ADDR_SPACE_BITS 32
  36#else
  37/* In order to form the GVA from space:offset,
  38   we need a 64-bit virtual address space.  */
  39#define TARGET_LONG_BITS            64
  40#define TARGET_VIRT_ADDR_SPACE_BITS 64
  41#define TARGET_REGISTER_BITS        32
  42#define TARGET_PHYS_ADDR_SPACE_BITS 32
  43#endif
  44
  45/* PA-RISC 1.x processors have a strong memory model.  */
  46/* ??? While we do not yet implement PA-RISC 2.0, those processors have
  47   a weak memory model, but with TLB bits that force ordering on a per-page
  48   basis.  It's probably easier to fall back to a strong memory model.  */
  49#define TCG_GUEST_DEFAULT_MO        TCG_MO_ALL
  50
  51#define CPUArchState struct CPUHPPAState
  52
  53#include "exec/cpu-defs.h"
  54
  55#define TARGET_PAGE_BITS 12
  56
  57#define ALIGNED_ONLY
  58#define NB_MMU_MODES     5
  59#define MMU_KERNEL_IDX   0
  60#define MMU_USER_IDX     3
  61#define MMU_PHYS_IDX     4
  62#define TARGET_INSN_START_EXTRA_WORDS 1
  63
  64/* Hardware exceptions, interupts, faults, and traps.  */
  65#define EXCP_HPMC                1  /* high priority machine check */
  66#define EXCP_POWER_FAIL          2
  67#define EXCP_RC                  3  /* recovery counter */
  68#define EXCP_EXT_INTERRUPT       4  /* external interrupt */
  69#define EXCP_LPMC                5  /* low priority machine check */
  70#define EXCP_ITLB_MISS           6  /* itlb miss / instruction page fault */
  71#define EXCP_IMP                 7  /* instruction memory protection trap */
  72#define EXCP_ILL                 8  /* illegal instruction trap */
  73#define EXCP_BREAK               9  /* break instruction */
  74#define EXCP_PRIV_OPR            10 /* privileged operation trap */
  75#define EXCP_PRIV_REG            11 /* privileged register trap */
  76#define EXCP_OVERFLOW            12 /* signed overflow trap */
  77#define EXCP_COND                13 /* trap-on-condition */
  78#define EXCP_ASSIST              14 /* assist exception trap */
  79#define EXCP_DTLB_MISS           15 /* dtlb miss / data page fault */
  80#define EXCP_NA_ITLB_MISS        16 /* non-access itlb miss */
  81#define EXCP_NA_DTLB_MISS        17 /* non-access dtlb miss */
  82#define EXCP_DMP                 18 /* data memory protection trap */
  83#define EXCP_DMB                 19 /* data memory break trap */
  84#define EXCP_TLB_DIRTY           20 /* tlb dirty bit trap */
  85#define EXCP_PAGE_REF            21 /* page reference trap */
  86#define EXCP_ASSIST_EMU          22 /* assist emulation trap */
  87#define EXCP_HPT                 23 /* high-privilege transfer trap */
  88#define EXCP_LPT                 24 /* low-privilege transfer trap */
  89#define EXCP_TB                  25 /* taken branch trap */
  90#define EXCP_DMAR                26 /* data memory access rights trap */
  91#define EXCP_DMPI                27 /* data memory protection id trap */
  92#define EXCP_UNALIGN             28 /* unaligned data reference trap */
  93#define EXCP_PER_INTERRUPT       29 /* performance monitor interrupt */
  94
  95/* Exceptions for linux-user emulation.  */
  96#define EXCP_SYSCALL             30
  97#define EXCP_SYSCALL_LWS         31
  98
  99/* Taken from Linux kernel: arch/parisc/include/asm/psw.h */
 100#define PSW_I            0x00000001
 101#define PSW_D            0x00000002
 102#define PSW_P            0x00000004
 103#define PSW_Q            0x00000008
 104#define PSW_R            0x00000010
 105#define PSW_F            0x00000020
 106#define PSW_G            0x00000040 /* PA1.x only */
 107#define PSW_O            0x00000080 /* PA2.0 only */
 108#define PSW_CB           0x0000ff00
 109#define PSW_M            0x00010000
 110#define PSW_V            0x00020000
 111#define PSW_C            0x00040000
 112#define PSW_B            0x00080000
 113#define PSW_X            0x00100000
 114#define PSW_N            0x00200000
 115#define PSW_L            0x00400000
 116#define PSW_H            0x00800000
 117#define PSW_T            0x01000000
 118#define PSW_S            0x02000000
 119#define PSW_E            0x04000000
 120#ifdef TARGET_HPPA64
 121#define PSW_W            0x08000000 /* PA2.0 only */
 122#else
 123#define PSW_W            0
 124#endif
 125#define PSW_Z            0x40000000 /* PA1.x only */
 126#define PSW_Y            0x80000000 /* PA1.x only */
 127
 128#define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \
 129               | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I)
 130
 131/* ssm/rsm instructions number PSW_W and PSW_E differently */
 132#define PSW_SM_I         PSW_I      /* Enable External Interrupts */
 133#define PSW_SM_D         PSW_D
 134#define PSW_SM_P         PSW_P
 135#define PSW_SM_Q         PSW_Q      /* Enable Interrupt State Collection */
 136#define PSW_SM_R         PSW_R      /* Enable Recover Counter Trap */
 137#ifdef TARGET_HPPA64
 138#define PSW_SM_E         0x100
 139#define PSW_SM_W         0x200      /* PA2.0 only : Enable Wide Mode */
 140#else
 141#define PSW_SM_E         0
 142#define PSW_SM_W         0
 143#endif
 144
 145#define CR_RC            0
 146#define CR_SCRCCR        10
 147#define CR_SAR           11
 148#define CR_IVA           14
 149#define CR_EIEM          15
 150#define CR_IT            16
 151#define CR_IIASQ         17
 152#define CR_IIAOQ         18
 153#define CR_IIR           19
 154#define CR_ISR           20
 155#define CR_IOR           21
 156#define CR_IPSW          22
 157#define CR_EIRR          23
 158
 159typedef struct CPUHPPAState CPUHPPAState;
 160
 161#if TARGET_REGISTER_BITS == 32
 162typedef uint32_t target_ureg;
 163typedef int32_t  target_sreg;
 164#define TREG_FMT_lx   "%08"PRIx32
 165#define TREG_FMT_ld   "%"PRId32
 166#else
 167typedef uint64_t target_ureg;
 168typedef int64_t  target_sreg;
 169#define TREG_FMT_lx   "%016"PRIx64
 170#define TREG_FMT_ld   "%"PRId64
 171#endif
 172
 173typedef struct {
 174    uint64_t va_b;
 175    uint64_t va_e;
 176    target_ureg pa;
 177    unsigned u : 1;
 178    unsigned t : 1;
 179    unsigned d : 1;
 180    unsigned b : 1;
 181    unsigned page_size : 4;
 182    unsigned ar_type : 3;
 183    unsigned ar_pl1 : 2;
 184    unsigned ar_pl2 : 2;
 185    unsigned entry_valid : 1;
 186    unsigned access_id : 16;
 187} hppa_tlb_entry;
 188
 189struct CPUHPPAState {
 190    target_ureg gr[32];
 191    uint64_t fr[32];
 192    uint64_t sr[8];          /* stored shifted into place for gva */
 193
 194    target_ureg psw;         /* All psw bits except the following:  */
 195    target_ureg psw_n;       /* boolean */
 196    target_sreg psw_v;       /* in most significant bit */
 197
 198    /* Splitting the carry-borrow field into the MSB and "the rest", allows
 199     * for "the rest" to be deleted when it is unused, but the MSB is in use.
 200     * In addition, it's easier to compute carry-in for bit B+1 than it is to
 201     * compute carry-out for bit B (3 vs 4 insns for addition, assuming the
 202     * host has the appropriate add-with-carry insn to compute the msb).
 203     * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110.
 204     */
 205    target_ureg psw_cb;      /* in least significant bit of next nibble */
 206    target_ureg psw_cb_msb;  /* boolean */
 207
 208    target_ureg iaoq_f;      /* front */
 209    target_ureg iaoq_b;      /* back, aka next instruction */
 210    uint64_t iasq_f;
 211    uint64_t iasq_b;
 212
 213    uint32_t fr0_shadow;     /* flags, c, ca/cq, rm, d, enables */
 214    float_status fp_status;
 215
 216    target_ureg cr[32];      /* control registers */
 217    target_ureg cr_back[2];  /* back of cr17/cr18 */
 218    target_ureg shadow[7];   /* shadow registers */
 219
 220    /* Those resources are used only in QEMU core */
 221    CPU_COMMON
 222
 223    /* ??? The number of entries isn't specified by the architecture.  */
 224    /* ??? Implement a unified itlb/dtlb for the moment.  */
 225    /* ??? We should use a more intelligent data structure.  */
 226    hppa_tlb_entry tlb[256];
 227    uint32_t tlb_last;
 228};
 229
 230/**
 231 * HPPACPU:
 232 * @env: #CPUHPPAState
 233 *
 234 * An HPPA CPU.
 235 */
 236struct HPPACPU {
 237    /*< private >*/
 238    CPUState parent_obj;
 239    /*< public >*/
 240
 241    CPUHPPAState env;
 242    QEMUTimer *alarm_timer;
 243};
 244
 245static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env)
 246{
 247    return container_of(env, HPPACPU, env);
 248}
 249
 250#define ENV_GET_CPU(e)  CPU(hppa_env_get_cpu(e))
 251#define ENV_OFFSET      offsetof(HPPACPU, env)
 252
 253#include "exec/cpu-all.h"
 254
 255static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
 256{
 257#ifdef CONFIG_USER_ONLY
 258    return MMU_USER_IDX;
 259#else
 260    if (env->psw & (ifetch ? PSW_C : PSW_D)) {
 261        return env->iaoq_f & 3;
 262    }
 263    return MMU_PHYS_IDX;  /* mmu disabled */
 264#endif
 265}
 266
 267void hppa_translate_init(void);
 268
 269#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
 270
 271void hppa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 272
 273static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc,
 274                                             target_ureg off)
 275{
 276#ifdef CONFIG_USER_ONLY
 277    return off;
 278#else
 279    off &= (psw & PSW_W ? 0x3fffffffffffffffull : 0xffffffffull);
 280    return spc | off;
 281#endif
 282}
 283
 284static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc,
 285                                         target_ureg off)
 286{
 287    return hppa_form_gva_psw(env->psw, spc, off);
 288}
 289
 290/* Since PSW_{I,CB} will never need to be in tb->flags, reuse them.
 291 * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the
 292 * same value.
 293 */
 294#define TB_FLAG_SR_SAME     PSW_I
 295#define TB_FLAG_PRIV_SHIFT  8
 296
 297static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc,
 298                                        target_ulong *cs_base,
 299                                        uint32_t *pflags)
 300{
 301    uint32_t flags = env->psw_n * PSW_N;
 302
 303    /* TB lookup assumes that PC contains the complete virtual address.
 304       If we leave space+offset separate, we'll get ITLB misses to an
 305       incomplete virtual address.  This also means that we must separate
 306       out current cpu priviledge from the low bits of IAOQ_F.  */
 307#ifdef CONFIG_USER_ONLY
 308    *pc = env->iaoq_f & -4;
 309    *cs_base = env->iaoq_b & -4;
 310#else
 311    /* ??? E, T, H, L, B, P bits need to be here, when implemented.  */
 312    flags |= env->psw & (PSW_W | PSW_C | PSW_D);
 313    flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT;
 314
 315    *pc = (env->psw & PSW_C
 316           ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4)
 317           : env->iaoq_f & -4);
 318    *cs_base = env->iasq_f;
 319
 320    /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero
 321       low 32-bits of CS_BASE.  This will succeed for all direct branches,
 322       which is the primary case we care about -- using goto_tb within a page.
 323       Failure is indicated by a zero difference.  */
 324    if (env->iasq_f == env->iasq_b) {
 325        target_sreg diff = env->iaoq_b - env->iaoq_f;
 326        if (TARGET_REGISTER_BITS == 32 || diff == (int32_t)diff) {
 327            *cs_base |= (uint32_t)diff;
 328        }
 329    }
 330    if ((env->sr[4] == env->sr[5])
 331        & (env->sr[4] == env->sr[6])
 332        & (env->sr[4] == env->sr[7])) {
 333        flags |= TB_FLAG_SR_SAME;
 334    }
 335#endif
 336
 337    *pflags = flags;
 338}
 339
 340target_ureg cpu_hppa_get_psw(CPUHPPAState *env);
 341void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg);
 342void cpu_hppa_loaded_fr0(CPUHPPAState *env);
 343
 344#define cpu_signal_handler cpu_hppa_signal_handler
 345
 346int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc);
 347hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
 348int hppa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 349int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 350void hppa_cpu_do_interrupt(CPUState *cpu);
 351bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
 352void hppa_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function, int);
 353#ifdef CONFIG_USER_ONLY
 354int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
 355                              int rw, int midx);
 356#else
 357int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
 358                              int type, hwaddr *pphys, int *pprot);
 359extern const MemoryRegionOps hppa_io_eir_ops;
 360extern const struct VMStateDescription vmstate_hppa_cpu;
 361void hppa_cpu_alarm_timer(void *);
 362int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr);
 363#endif
 364void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra);
 365
 366#endif /* HPPA_CPU_H */
 367