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21#include "qemu/osdep.h"
22#include "cpu.h"
23#include "exec/helper-proto.h"
24#include "qemu/host-utils.h"
25#include "exec/exec-all.h"
26#include "exec/cpu_ldst.h"
27#include "fpu/softfloat.h"
28
29#define D(x)
30
31#if !defined(CONFIG_USER_ONLY)
32
33
34
35
36
37void tlb_fill(CPUState *cs, target_ulong addr, int size,
38 MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
39{
40 int ret;
41
42 ret = mb_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx);
43 if (unlikely(ret)) {
44
45 cpu_loop_exit_restore(cs, retaddr);
46 }
47}
48#endif
49
50void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
51{
52 int test = ctrl & STREAM_TEST;
53 int atomic = ctrl & STREAM_ATOMIC;
54 int control = ctrl & STREAM_CONTROL;
55 int nonblock = ctrl & STREAM_NONBLOCK;
56 int exception = ctrl & STREAM_EXCEPTION;
57
58 qemu_log_mask(LOG_UNIMP, "Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
59 id, data,
60 test ? "t" : "",
61 nonblock ? "n" : "",
62 exception ? "e" : "",
63 control ? "c" : "",
64 atomic ? "a" : "");
65}
66
67uint32_t helper_get(uint32_t id, uint32_t ctrl)
68{
69 int test = ctrl & STREAM_TEST;
70 int atomic = ctrl & STREAM_ATOMIC;
71 int control = ctrl & STREAM_CONTROL;
72 int nonblock = ctrl & STREAM_NONBLOCK;
73 int exception = ctrl & STREAM_EXCEPTION;
74
75 qemu_log_mask(LOG_UNIMP, "Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
76 id,
77 test ? "t" : "",
78 nonblock ? "n" : "",
79 exception ? "e" : "",
80 control ? "c" : "",
81 atomic ? "a" : "");
82 return 0xdead0000 | id;
83}
84
85void helper_raise_exception(CPUMBState *env, uint32_t index)
86{
87 CPUState *cs = CPU(mb_env_get_cpu(env));
88
89 cs->exception_index = index;
90 cpu_loop_exit(cs);
91}
92
93void helper_debug(CPUMBState *env)
94{
95 int i;
96
97 qemu_log("PC=%" PRIx64 "\n", env->sregs[SR_PC]);
98 qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " "
99 "debug[%x] imm=%x iflags=%x\n",
100 env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
101 env->debug, env->imm, env->iflags);
102 qemu_log("btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) eip=%d ie=%d\n",
103 env->btaken, env->btarget,
104 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
105 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
106 (bool)(env->sregs[SR_MSR] & MSR_EIP),
107 (bool)(env->sregs[SR_MSR] & MSR_IE));
108 for (i = 0; i < 32; i++) {
109 qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
110 if ((i + 1) % 4 == 0)
111 qemu_log("\n");
112 }
113 qemu_log("\n\n");
114}
115
116static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
117{
118 uint32_t cout = 0;
119
120 if ((b == ~0) && cin)
121 cout = 1;
122 else if ((~0 - a) < (b + cin))
123 cout = 1;
124 return cout;
125}
126
127uint32_t helper_cmp(uint32_t a, uint32_t b)
128{
129 uint32_t t;
130
131 t = b + ~a + 1;
132 if ((b & 0x80000000) ^ (a & 0x80000000))
133 t = (t & 0x7fffffff) | (b & 0x80000000);
134 return t;
135}
136
137uint32_t helper_cmpu(uint32_t a, uint32_t b)
138{
139 uint32_t t;
140
141 t = b + ~a + 1;
142 if ((b & 0x80000000) ^ (a & 0x80000000))
143 t = (t & 0x7fffffff) | (a & 0x80000000);
144 return t;
145}
146
147uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
148{
149 return compute_carry(a, b, cf);
150}
151
152static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
153{
154 if (b == 0) {
155 env->sregs[SR_MSR] |= MSR_DZ;
156
157 if ((env->sregs[SR_MSR] & MSR_EE)
158 && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
159 env->sregs[SR_ESR] = ESR_EC_DIVZERO;
160 helper_raise_exception(env, EXCP_HW_EXCP);
161 }
162 return 0;
163 }
164 env->sregs[SR_MSR] &= ~MSR_DZ;
165 return 1;
166}
167
168uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
169{
170 if (!div_prepare(env, a, b)) {
171 return 0;
172 }
173 return (int32_t)a / (int32_t)b;
174}
175
176uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
177{
178 if (!div_prepare(env, a, b)) {
179 return 0;
180 }
181 return a / b;
182}
183
184
185static void raise_fpu_exception(CPUMBState *env)
186{
187 env->sregs[SR_ESR] = ESR_EC_FPU;
188 helper_raise_exception(env, EXCP_HW_EXCP);
189}
190
191static void update_fpu_flags(CPUMBState *env, int flags)
192{
193 int raise = 0;
194
195 if (flags & float_flag_invalid) {
196 env->sregs[SR_FSR] |= FSR_IO;
197 raise = 1;
198 }
199 if (flags & float_flag_divbyzero) {
200 env->sregs[SR_FSR] |= FSR_DZ;
201 raise = 1;
202 }
203 if (flags & float_flag_overflow) {
204 env->sregs[SR_FSR] |= FSR_OF;
205 raise = 1;
206 }
207 if (flags & float_flag_underflow) {
208 env->sregs[SR_FSR] |= FSR_UF;
209 raise = 1;
210 }
211 if (raise
212 && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
213 && (env->sregs[SR_MSR] & MSR_EE)) {
214 raise_fpu_exception(env);
215 }
216}
217
218uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
219{
220 CPU_FloatU fd, fa, fb;
221 int flags;
222
223 set_float_exception_flags(0, &env->fp_status);
224 fa.l = a;
225 fb.l = b;
226 fd.f = float32_add(fa.f, fb.f, &env->fp_status);
227
228 flags = get_float_exception_flags(&env->fp_status);
229 update_fpu_flags(env, flags);
230 return fd.l;
231}
232
233uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
234{
235 CPU_FloatU fd, fa, fb;
236 int flags;
237
238 set_float_exception_flags(0, &env->fp_status);
239 fa.l = a;
240 fb.l = b;
241 fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
242 flags = get_float_exception_flags(&env->fp_status);
243 update_fpu_flags(env, flags);
244 return fd.l;
245}
246
247uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
248{
249 CPU_FloatU fd, fa, fb;
250 int flags;
251
252 set_float_exception_flags(0, &env->fp_status);
253 fa.l = a;
254 fb.l = b;
255 fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
256 flags = get_float_exception_flags(&env->fp_status);
257 update_fpu_flags(env, flags);
258
259 return fd.l;
260}
261
262uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
263{
264 CPU_FloatU fd, fa, fb;
265 int flags;
266
267 set_float_exception_flags(0, &env->fp_status);
268 fa.l = a;
269 fb.l = b;
270 fd.f = float32_div(fb.f, fa.f, &env->fp_status);
271 flags = get_float_exception_flags(&env->fp_status);
272 update_fpu_flags(env, flags);
273
274 return fd.l;
275}
276
277uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
278{
279 CPU_FloatU fa, fb;
280 uint32_t r = 0;
281
282 fa.l = a;
283 fb.l = b;
284
285 if (float32_is_signaling_nan(fa.f, &env->fp_status) ||
286 float32_is_signaling_nan(fb.f, &env->fp_status)) {
287 update_fpu_flags(env, float_flag_invalid);
288 r = 1;
289 }
290
291 if (float32_is_quiet_nan(fa.f, &env->fp_status) ||
292 float32_is_quiet_nan(fb.f, &env->fp_status)) {
293 r = 1;
294 }
295
296 return r;
297}
298
299uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
300{
301 CPU_FloatU fa, fb;
302 int r;
303 int flags;
304
305 set_float_exception_flags(0, &env->fp_status);
306 fa.l = a;
307 fb.l = b;
308 r = float32_lt(fb.f, fa.f, &env->fp_status);
309 flags = get_float_exception_flags(&env->fp_status);
310 update_fpu_flags(env, flags & float_flag_invalid);
311
312 return r;
313}
314
315uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
316{
317 CPU_FloatU fa, fb;
318 int flags;
319 int r;
320
321 set_float_exception_flags(0, &env->fp_status);
322 fa.l = a;
323 fb.l = b;
324 r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
325 flags = get_float_exception_flags(&env->fp_status);
326 update_fpu_flags(env, flags & float_flag_invalid);
327
328 return r;
329}
330
331uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
332{
333 CPU_FloatU fa, fb;
334 int flags;
335 int r;
336
337 fa.l = a;
338 fb.l = b;
339 set_float_exception_flags(0, &env->fp_status);
340 r = float32_le(fa.f, fb.f, &env->fp_status);
341 flags = get_float_exception_flags(&env->fp_status);
342 update_fpu_flags(env, flags & float_flag_invalid);
343
344
345 return r;
346}
347
348uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
349{
350 CPU_FloatU fa, fb;
351 int flags, r;
352
353 fa.l = a;
354 fb.l = b;
355 set_float_exception_flags(0, &env->fp_status);
356 r = float32_lt(fa.f, fb.f, &env->fp_status);
357 flags = get_float_exception_flags(&env->fp_status);
358 update_fpu_flags(env, flags & float_flag_invalid);
359 return r;
360}
361
362uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
363{
364 CPU_FloatU fa, fb;
365 int flags, r;
366
367 fa.l = a;
368 fb.l = b;
369 set_float_exception_flags(0, &env->fp_status);
370 r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
371 flags = get_float_exception_flags(&env->fp_status);
372 update_fpu_flags(env, flags & float_flag_invalid);
373
374 return r;
375}
376
377uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
378{
379 CPU_FloatU fa, fb;
380 int flags, r;
381
382 fa.l = a;
383 fb.l = b;
384 set_float_exception_flags(0, &env->fp_status);
385 r = !float32_lt(fa.f, fb.f, &env->fp_status);
386 flags = get_float_exception_flags(&env->fp_status);
387 update_fpu_flags(env, flags & float_flag_invalid);
388
389 return r;
390}
391
392uint32_t helper_flt(CPUMBState *env, uint32_t a)
393{
394 CPU_FloatU fd, fa;
395
396 fa.l = a;
397 fd.f = int32_to_float32(fa.l, &env->fp_status);
398 return fd.l;
399}
400
401uint32_t helper_fint(CPUMBState *env, uint32_t a)
402{
403 CPU_FloatU fa;
404 uint32_t r;
405 int flags;
406
407 set_float_exception_flags(0, &env->fp_status);
408 fa.l = a;
409 r = float32_to_int32(fa.f, &env->fp_status);
410 flags = get_float_exception_flags(&env->fp_status);
411 update_fpu_flags(env, flags);
412
413 return r;
414}
415
416uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
417{
418 CPU_FloatU fd, fa;
419 int flags;
420
421 set_float_exception_flags(0, &env->fp_status);
422 fa.l = a;
423 fd.l = float32_sqrt(fa.f, &env->fp_status);
424 flags = get_float_exception_flags(&env->fp_status);
425 update_fpu_flags(env, flags);
426
427 return fd.l;
428}
429
430uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
431{
432 unsigned int i;
433 uint32_t mask = 0xff000000;
434
435 for (i = 0; i < 4; i++) {
436 if ((a & mask) == (b & mask))
437 return i + 1;
438 mask >>= 8;
439 }
440 return 0;
441}
442
443void helper_memalign(CPUMBState *env, target_ulong addr,
444 uint32_t dr, uint32_t wr,
445 uint32_t mask)
446{
447 if (addr & mask) {
448 qemu_log_mask(CPU_LOG_INT,
449 "unaligned access addr=" TARGET_FMT_lx
450 " mask=%x, wr=%d dr=r%d\n",
451 addr, mask, wr, dr);
452 env->sregs[SR_EAR] = addr;
453 env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
454 | (dr & 31) << 5;
455 if (mask == 3) {
456 env->sregs[SR_ESR] |= 1 << 11;
457 }
458 if (!(env->sregs[SR_MSR] & MSR_EE)) {
459 return;
460 }
461 helper_raise_exception(env, EXCP_HW_EXCP);
462 }
463}
464
465void helper_stackprot(CPUMBState *env, target_ulong addr)
466{
467 if (addr < env->slr || addr > env->shr) {
468 qemu_log_mask(CPU_LOG_INT, "Stack protector violation at "
469 TARGET_FMT_lx " %x %x\n",
470 addr, env->slr, env->shr);
471 env->sregs[SR_EAR] = addr;
472 env->sregs[SR_ESR] = ESR_EC_STACKPROT;
473 helper_raise_exception(env, EXCP_HW_EXCP);
474 }
475}
476
477#if !defined(CONFIG_USER_ONLY)
478
479uint32_t helper_mmu_read(CPUMBState *env, uint32_t ext, uint32_t rn)
480{
481 return mmu_read(env, ext, rn);
482}
483
484void helper_mmu_write(CPUMBState *env, uint32_t ext, uint32_t rn, uint32_t v)
485{
486 mmu_write(env, ext, rn, v);
487}
488
489void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr,
490 bool is_write, bool is_exec, int is_asi,
491 unsigned size)
492{
493 MicroBlazeCPU *cpu;
494 CPUMBState *env;
495
496 qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
497 addr, is_write ? 1 : 0, is_exec ? 1 : 0);
498 if (cs == NULL) {
499 return;
500 }
501 cpu = MICROBLAZE_CPU(cs);
502 env = &cpu->env;
503 if (!(env->sregs[SR_MSR] & MSR_EE)) {
504 return;
505 }
506
507 env->sregs[SR_EAR] = addr;
508 if (is_exec) {
509 if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
510 env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
511 helper_raise_exception(env, EXCP_HW_EXCP);
512 }
513 } else {
514 if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
515 env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
516 helper_raise_exception(env, EXCP_HW_EXCP);
517 }
518 }
519}
520#endif
521
