LXR qemu/target/mips/machine.c

   1#include "qemu/osdep.h"
   2#include "qemu-common.h"
   3#include "cpu.h"
   4#include "internal.h"
   5#include "hw/hw.h"
   6#include "migration/cpu.h"
   7
   8static int cpu_post_load(void *opaque, int version_id)
   9{
  10    MIPSCPU *cpu = opaque;
  11    CPUMIPSState *env = &cpu->env;
  12
  13    restore_fp_status(env);
  14    restore_msa_fp_status(env);
  15    compute_hflags(env);
  16    restore_pamask(env);
  17
  18    return 0;
  19}
  20
  21/* FPU state */
  22
  23static int get_fpr(QEMUFile *f, void *pv, size_t size,
  24                   const VMStateField *field)
  25{
  26    int i;
  27    fpr_t *v = pv;
  28    /* Restore entire MSA vector register */
  29    for (i = 0; i < MSA_WRLEN/64; i++) {
  30        qemu_get_sbe64s(f, &v->wr.d[i]);
  31    }
  32    return 0;
  33}
  34
  35static int put_fpr(QEMUFile *f, void *pv, size_t size,
  36                   const VMStateField *field, QJSON *vmdesc)
  37{
  38    int i;
  39    fpr_t *v = pv;
  40    /* Save entire MSA vector register */
  41    for (i = 0; i < MSA_WRLEN/64; i++) {
  42        qemu_put_sbe64s(f, &v->wr.d[i]);
  43    }
  44
  45    return 0;
  46}
  47
  48const VMStateInfo vmstate_info_fpr = {
  49    .name = "fpr",
  50    .get  = get_fpr,
  51    .put  = put_fpr,
  52};
  53
  54#define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v)                     \
  55    VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_fpr, fpr_t)
  56
  57#define VMSTATE_FPR_ARRAY(_f, _s, _n)                           \
  58    VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0)
  59
  60static VMStateField vmstate_fpu_fields[] = {
  61    VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32),
  62    VMSTATE_UINT32(fcr0, CPUMIPSFPUContext),
  63    VMSTATE_UINT32(fcr31, CPUMIPSFPUContext),
  64    VMSTATE_END_OF_LIST()
  65};
  66
  67const VMStateDescription vmstate_fpu = {
  68    .name = "cpu/fpu",
  69    .version_id = 1,
  70    .minimum_version_id = 1,
  71    .fields = vmstate_fpu_fields
  72};
  73
  74const VMStateDescription vmstate_inactive_fpu = {
  75    .name = "cpu/inactive_fpu",
  76    .version_id = 1,
  77    .minimum_version_id = 1,
  78    .fields = vmstate_fpu_fields
  79};
  80
  81/* TC state */
  82
  83static VMStateField vmstate_tc_fields[] = {
  84    VMSTATE_UINTTL_ARRAY(gpr, TCState, 32),
  85    VMSTATE_UINTTL(PC, TCState),
  86    VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC),
  87    VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC),
  88    VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC),
  89    VMSTATE_UINTTL(DSPControl, TCState),
  90    VMSTATE_INT32(CP0_TCStatus, TCState),
  91    VMSTATE_INT32(CP0_TCBind, TCState),
  92    VMSTATE_UINTTL(CP0_TCHalt, TCState),
  93    VMSTATE_UINTTL(CP0_TCContext, TCState),
  94    VMSTATE_UINTTL(CP0_TCSchedule, TCState),
  95    VMSTATE_UINTTL(CP0_TCScheFBack, TCState),
  96    VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
  97    VMSTATE_UINTTL(CP0_UserLocal, TCState),
  98    VMSTATE_INT32(msacsr, TCState),
  99    VMSTATE_END_OF_LIST()
 100};
 101
 102const VMStateDescription vmstate_tc = {
 103    .name = "cpu/tc",
 104    .version_id = 1,
 105    .minimum_version_id = 1,
 106    .fields = vmstate_tc_fields
 107};
 108
 109const VMStateDescription vmstate_inactive_tc = {
 110    .name = "cpu/inactive_tc",
 111    .version_id = 1,
 112    .minimum_version_id = 1,
 113    .fields = vmstate_tc_fields
 114};
 115
 116/* MVP state */
 117
 118const VMStateDescription vmstate_mvp = {
 119    .name = "cpu/mvp",
 120    .version_id = 1,
 121    .minimum_version_id = 1,
 122    .fields = (VMStateField[]) {
 123        VMSTATE_INT32(CP0_MVPControl, CPUMIPSMVPContext),
 124        VMSTATE_INT32(CP0_MVPConf0, CPUMIPSMVPContext),
 125        VMSTATE_INT32(CP0_MVPConf1, CPUMIPSMVPContext),
 126        VMSTATE_END_OF_LIST()
 127    }
 128};
 129
 130/* TLB state */
 131
 132static int get_tlb(QEMUFile *f, void *pv, size_t size,
 133                   const VMStateField *field)
 134{
 135    r4k_tlb_t *v = pv;
 136    uint16_t flags;
 137
 138    qemu_get_betls(f, &v->VPN);
 139    qemu_get_be32s(f, &v->PageMask);
 140    qemu_get_be16s(f, &v->ASID);
 141    qemu_get_be16s(f, &flags);
 142    v->G = (flags >> 10) & 1;
 143    v->C0 = (flags >> 7) & 3;
 144    v->C1 = (flags >> 4) & 3;
 145    v->V0 = (flags >> 3) & 1;
 146    v->V1 = (flags >> 2) & 1;
 147    v->D0 = (flags >> 1) & 1;
 148    v->D1 = (flags >> 0) & 1;
 149    v->EHINV = (flags >> 15) & 1;
 150    v->RI1 = (flags >> 14) & 1;
 151    v->RI0 = (flags >> 13) & 1;
 152    v->XI1 = (flags >> 12) & 1;
 153    v->XI0 = (flags >> 11) & 1;
 154    qemu_get_be64s(f, &v->PFN[0]);
 155    qemu_get_be64s(f, &v->PFN[1]);
 156
 157    return 0;
 158}
 159
 160static int put_tlb(QEMUFile *f, void *pv, size_t size,
 161                   const VMStateField *field, QJSON *vmdesc)
 162{
 163    r4k_tlb_t *v = pv;
 164
 165    uint16_t asid = v->ASID;
 166    uint16_t flags = ((v->EHINV << 15) |
 167                      (v->RI1 << 14) |
 168                      (v->RI0 << 13) |
 169                      (v->XI1 << 12) |
 170                      (v->XI0 << 11) |
 171                      (v->G << 10) |
 172                      (v->C0 << 7) |
 173                      (v->C1 << 4) |
 174                      (v->V0 << 3) |
 175                      (v->V1 << 2) |
 176                      (v->D0 << 1) |
 177                      (v->D1 << 0));
 178
 179    qemu_put_betls(f, &v->VPN);
 180    qemu_put_be32s(f, &v->PageMask);
 181    qemu_put_be16s(f, &asid);
 182    qemu_put_be16s(f, &flags);
 183    qemu_put_be64s(f, &v->PFN[0]);
 184    qemu_put_be64s(f, &v->PFN[1]);
 185
 186    return 0;
 187}
 188
 189const VMStateInfo vmstate_info_tlb = {
 190    .name = "tlb_entry",
 191    .get  = get_tlb,
 192    .put  = put_tlb,
 193};
 194
 195#define VMSTATE_TLB_ARRAY_V(_f, _s, _n, _v)                     \
 196    VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_tlb, r4k_tlb_t)
 197
 198#define VMSTATE_TLB_ARRAY(_f, _s, _n)                           \
 199    VMSTATE_TLB_ARRAY_V(_f, _s, _n, 0)
 200
 201const VMStateDescription vmstate_tlb = {
 202    .name = "cpu/tlb",
 203    .version_id = 2,
 204    .minimum_version_id = 2,
 205    .fields = (VMStateField[]) {
 206        VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext),
 207        VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext),
 208        VMSTATE_TLB_ARRAY(mmu.r4k.tlb, CPUMIPSTLBContext, MIPS_TLB_MAX),
 209        VMSTATE_END_OF_LIST()
 210    }
 211};
 212
 213/* MIPS CPU state */
 214
 215const VMStateDescription vmstate_mips_cpu = {
 216    .name = "cpu",
 217    .version_id = 15,
 218    .minimum_version_id = 15,
 219    .post_load = cpu_post_load,
 220    .fields = (VMStateField[]) {
 221        /* Active TC */
 222        VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState),
 223
 224        /* Active FPU */
 225        VMSTATE_STRUCT(env.active_fpu, MIPSCPU, 1, vmstate_fpu,
 226                       CPUMIPSFPUContext),
 227
 228        /* MVP */
 229        VMSTATE_STRUCT_POINTER(env.mvp, MIPSCPU, vmstate_mvp,
 230                               CPUMIPSMVPContext),
 231
 232        /* TLB */
 233        VMSTATE_STRUCT_POINTER(env.tlb, MIPSCPU, vmstate_tlb,
 234                               CPUMIPSTLBContext),
 235
 236        /* CPU metastate */
 237        VMSTATE_UINT32(env.current_tc, MIPSCPU),
 238        VMSTATE_UINT32(env.current_fpu, MIPSCPU),
 239        VMSTATE_INT32(env.error_code, MIPSCPU),
 240        VMSTATE_UINTTL(env.btarget, MIPSCPU),
 241        VMSTATE_UINTTL(env.bcond, MIPSCPU),
 242
 243        /* Remaining CP0 registers */
 244        VMSTATE_INT32(env.CP0_Index, MIPSCPU),
 245        VMSTATE_INT32(env.CP0_Random, MIPSCPU),
 246        VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU),
 247        VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU),
 248        VMSTATE_INT32(env.CP0_VPEConf1, MIPSCPU),
 249        VMSTATE_UINTTL(env.CP0_YQMask, MIPSCPU),
 250        VMSTATE_UINTTL(env.CP0_VPESchedule, MIPSCPU),
 251        VMSTATE_UINTTL(env.CP0_VPEScheFBack, MIPSCPU),
 252        VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU),
 253        VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU),
 254        VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU),
 255        VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
 256        VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
 257        VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),
 258        VMSTATE_UINTTL(env.CP0_SegCtl0, MIPSCPU),
 259        VMSTATE_UINTTL(env.CP0_SegCtl1, MIPSCPU),
 260        VMSTATE_UINTTL(env.CP0_SegCtl2, MIPSCPU),
 261        VMSTATE_UINTTL(env.CP0_PWBase, MIPSCPU),
 262        VMSTATE_UINTTL(env.CP0_PWField, MIPSCPU),
 263        VMSTATE_UINTTL(env.CP0_PWSize, MIPSCPU),
 264        VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
 265        VMSTATE_INT32(env.CP0_PWCtl, MIPSCPU),
 266        VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
 267        VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
 268        VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU),
 269        VMSTATE_INT32(env.CP0_SRSConf3, MIPSCPU),
 270        VMSTATE_INT32(env.CP0_SRSConf4, MIPSCPU),
 271        VMSTATE_INT32(env.CP0_HWREna, MIPSCPU),
 272        VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
 273        VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
 274        VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
 275        VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
 276        VMSTATE_INT32(env.CP0_Count, MIPSCPU),
 277        VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
 278        VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
 279        VMSTATE_INT32(env.CP0_Status, MIPSCPU),
 280        VMSTATE_INT32(env.CP0_IntCtl, MIPSCPU),
 281        VMSTATE_INT32(env.CP0_SRSCtl, MIPSCPU),
 282        VMSTATE_INT32(env.CP0_SRSMap, MIPSCPU),
 283        VMSTATE_INT32(env.CP0_Cause, MIPSCPU),
 284        VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU),
 285        VMSTATE_INT32(env.CP0_PRid, MIPSCPU),
 286        VMSTATE_UINTTL(env.CP0_EBase, MIPSCPU),
 287        VMSTATE_INT32(env.CP0_Config0, MIPSCPU),
 288        VMSTATE_INT32(env.CP0_Config1, MIPSCPU),
 289        VMSTATE_INT32(env.CP0_Config2, MIPSCPU),
 290        VMSTATE_INT32(env.CP0_Config3, MIPSCPU),
 291        VMSTATE_INT32(env.CP0_Config6, MIPSCPU),
 292        VMSTATE_INT32(env.CP0_Config7, MIPSCPU),
 293        VMSTATE_UINT64_ARRAY(env.CP0_MAAR, MIPSCPU, MIPS_MAAR_MAX),
 294        VMSTATE_INT32(env.CP0_MAARI, MIPSCPU),
 295        VMSTATE_UINT64(env.lladdr, MIPSCPU),
 296        VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8),
 297        VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
 298        VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU),
 299        VMSTATE_INT32(env.CP0_Framemask, MIPSCPU),
 300        VMSTATE_INT32(env.CP0_Debug, MIPSCPU),
 301        VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU),
 302        VMSTATE_INT32(env.CP0_Performance0, MIPSCPU),
 303        VMSTATE_UINT64(env.CP0_TagLo, MIPSCPU),
 304        VMSTATE_INT32(env.CP0_DataLo, MIPSCPU),
 305        VMSTATE_INT32(env.CP0_TagHi, MIPSCPU),
 306        VMSTATE_INT32(env.CP0_DataHi, MIPSCPU),
 307        VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU),
 308        VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU),
 309        VMSTATE_UINTTL_ARRAY(env.CP0_KScratch, MIPSCPU, MIPS_KSCRATCH_NUM),
 310
 311        /* Inactive TC */
 312        VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1,
 313                             vmstate_inactive_tc, TCState),
 314        VMSTATE_STRUCT_ARRAY(env.fpus, MIPSCPU, MIPS_FPU_MAX, 1,
 315                             vmstate_inactive_fpu, CPUMIPSFPUContext),
 316
 317        VMSTATE_END_OF_LIST()
 318    },
 319};
 320