1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#ifndef QEMU_PPC_CPU_QOM_H
21#define QEMU_PPC_CPU_QOM_H
22
23#include "qom/cpu.h"
24
25#ifdef TARGET_PPC64
26#define TYPE_POWERPC_CPU "powerpc64-cpu"
27#else
28#define TYPE_POWERPC_CPU "powerpc-cpu"
29#endif
30
31#define POWERPC_CPU_CLASS(klass) \
32 OBJECT_CLASS_CHECK(PowerPCCPUClass, (klass), TYPE_POWERPC_CPU)
33#define POWERPC_CPU(obj) \
34 OBJECT_CHECK(PowerPCCPU, (obj), TYPE_POWERPC_CPU)
35#define POWERPC_CPU_GET_CLASS(obj) \
36 OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU)
37
38typedef struct PowerPCCPU PowerPCCPU;
39typedef struct CPUPPCState CPUPPCState;
40typedef struct ppc_tb_t ppc_tb_t;
41typedef struct ppc_dcr_t ppc_dcr_t;
42
43
44
45typedef enum powerpc_mmu_t powerpc_mmu_t;
46enum powerpc_mmu_t {
47 POWERPC_MMU_UNKNOWN = 0x00000000,
48
49 POWERPC_MMU_32B = 0x00000001,
50
51 POWERPC_MMU_SOFT_6xx = 0x00000002,
52
53 POWERPC_MMU_SOFT_74xx = 0x00000003,
54
55 POWERPC_MMU_SOFT_4xx = 0x00000004,
56
57 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
58
59 POWERPC_MMU_REAL = 0x00000006,
60
61 POWERPC_MMU_MPC8xx = 0x00000007,
62
63 POWERPC_MMU_BOOKE = 0x00000008,
64
65 POWERPC_MMU_BOOKE206 = 0x00000009,
66
67 POWERPC_MMU_601 = 0x0000000A,
68#define POWERPC_MMU_64 0x00010000
69
70 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
71
72 POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
73
74 POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003,
75
76 POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
77
78 POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
79};
80
81
82
83typedef enum powerpc_excp_t powerpc_excp_t;
84enum powerpc_excp_t {
85 POWERPC_EXCP_UNKNOWN = 0,
86
87 POWERPC_EXCP_STD,
88
89 POWERPC_EXCP_40x,
90
91 POWERPC_EXCP_601,
92
93 POWERPC_EXCP_602,
94
95 POWERPC_EXCP_603,
96
97 POWERPC_EXCP_603E,
98
99 POWERPC_EXCP_G2,
100
101 POWERPC_EXCP_604,
102
103 POWERPC_EXCP_7x0,
104
105 POWERPC_EXCP_7x5,
106
107 POWERPC_EXCP_74xx,
108
109 POWERPC_EXCP_BOOKE,
110
111 POWERPC_EXCP_970,
112
113 POWERPC_EXCP_POWER7,
114
115 POWERPC_EXCP_POWER8,
116};
117
118
119
120typedef enum {
121 PPC_PM_DOZE,
122 PPC_PM_NAP,
123 PPC_PM_SLEEP,
124 PPC_PM_RVWINKLE,
125} powerpc_pm_insn_t;
126
127
128
129typedef enum powerpc_input_t powerpc_input_t;
130enum powerpc_input_t {
131 PPC_FLAGS_INPUT_UNKNOWN = 0,
132
133 PPC_FLAGS_INPUT_6xx,
134
135 PPC_FLAGS_INPUT_BookE,
136
137 PPC_FLAGS_INPUT_405,
138
139 PPC_FLAGS_INPUT_970,
140
141 PPC_FLAGS_INPUT_POWER7,
142
143 PPC_FLAGS_INPUT_401,
144
145 PPC_FLAGS_INPUT_RCPU,
146};
147
148typedef struct PPCHash64Options PPCHash64Options;
149
150
151
152
153
154
155
156
157typedef struct PowerPCCPUClass {
158
159 CPUClass parent_class;
160
161
162 DeviceRealize parent_realize;
163 DeviceUnrealize parent_unrealize;
164 void (*parent_reset)(CPUState *cpu);
165 void (*parent_parse_features)(const char *type, char *str, Error **errp);
166
167 uint32_t pvr;
168 bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr);
169 uint64_t pcr_mask;
170 uint64_t pcr_supported;
171 uint32_t svr;
172 uint64_t insns_flags;
173 uint64_t insns_flags2;
174 uint64_t msr_mask;
175 uint64_t lpcr_pm;
176 powerpc_mmu_t mmu_model;
177 powerpc_excp_t excp_model;
178 powerpc_input_t bus_model;
179 uint32_t flags;
180 int bfd_mach;
181 uint32_t l1_dcache_size, l1_icache_size;
182 const PPCHash64Options *hash64_opts;
183 struct ppc_radix_page_info *radix_page_info;
184 void (*init_proc)(CPUPPCState *env);
185 int (*check_pow)(CPUPPCState *env);
186 int (*handle_mmu_fault)(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx);
187 bool (*interrupts_big_endian)(PowerPCCPU *cpu);
188} PowerPCCPUClass;
189
190#ifndef CONFIG_USER_ONLY
191typedef struct PPCTimebase {
192 uint64_t guest_timebase;
193 int64_t time_of_the_day_ns;
194} PPCTimebase;
195
196extern const struct VMStateDescription vmstate_ppc_timebase;
197
198#define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) { \
199 .name = (stringify(_field)), \
200 .version_id = (_version), \
201 .size = sizeof(PPCTimebase), \
202 .vmsd = &vmstate_ppc_timebase, \
203 .flags = VMS_STRUCT, \
204 .offset = vmstate_offset_value(_state, _field, PPCTimebase), \
205}
206
207void cpu_ppc_clock_vm_state_change(void *opaque, int running,
208 RunState state);
209#endif
210
211#endif
212