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19#include "qemu/osdep.h"
20#include "qemu/main-loop.h"
21#include "cpu.h"
22#include "exec/helper-proto.h"
23#include "exec/exec-all.h"
24#include "exec/cpu_ldst.h"
25#include "internal.h"
26#include "helper_regs.h"
27
28
29
30
31
32#ifdef DEBUG_EXCEPTIONS
33# define LOG_EXCP(...) qemu_log(__VA_ARGS__)
34#else
35# define LOG_EXCP(...) do { } while (0)
36#endif
37
38
39
40#if defined(CONFIG_USER_ONLY)
41void ppc_cpu_do_interrupt(CPUState *cs)
42{
43 PowerPCCPU *cpu = POWERPC_CPU(cs);
44 CPUPPCState *env = &cpu->env;
45
46 cs->exception_index = POWERPC_EXCP_NONE;
47 env->error_code = 0;
48}
49
50static void ppc_hw_interrupt(CPUPPCState *env)
51{
52 CPUState *cs = CPU(ppc_env_get_cpu(env));
53
54 cs->exception_index = POWERPC_EXCP_NONE;
55 env->error_code = 0;
56}
57#else
58static inline void dump_syscall(CPUPPCState *env)
59{
60 qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 " r3=%016" PRIx64
61 " r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64
62 " nip=" TARGET_FMT_lx "\n",
63 ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3),
64 ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5),
65 ppc_dump_gpr(env, 6), env->nip);
66}
67
68
69
70
71static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
72{
73 CPUState *cs = CPU(cpu);
74 CPUPPCState *env = &cpu->env;
75 target_ulong msr, new_msr, vector;
76 int srr0, srr1, asrr0, asrr1, lev, ail;
77 bool lpes0;
78
79 qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
80 " => %08x (%02x)\n", env->nip, excp, env->error_code);
81
82
83 if (excp_model == POWERPC_EXCP_BOOKE) {
84 msr = env->msr;
85 } else {
86 msr = env->msr & ~0x783f0000ULL;
87 }
88
89
90
91
92 new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
93
94
95 srr0 = SPR_SRR0;
96 srr1 = SPR_SRR1;
97 asrr0 = -1;
98 asrr1 = -1;
99
100
101 if (env->in_pm_state) {
102 env->in_pm_state = false;
103
104
105 msr |= (0x1ull << (63 - 47));
106
107
108
109
110 if (excp != POWERPC_EXCP_MCHECK) {
111 switch (excp) {
112 case POWERPC_EXCP_RESET:
113 msr |= 0x4ull << (63 - 45);
114 break;
115 case POWERPC_EXCP_EXTERNAL:
116 msr |= 0x8ull << (63 - 45);
117 break;
118 case POWERPC_EXCP_DECR:
119 msr |= 0x6ull << (63 - 45);
120 break;
121 case POWERPC_EXCP_SDOOR:
122 msr |= 0x5ull << (63 - 45);
123 break;
124 case POWERPC_EXCP_SDOOR_HV:
125 msr |= 0x3ull << (63 - 45);
126 break;
127 case POWERPC_EXCP_HV_MAINT:
128 msr |= 0xaull << (63 - 45);
129 break;
130 default:
131 cpu_abort(cs, "Unsupported exception %d in Power Save mode\n",
132 excp);
133 }
134 excp = POWERPC_EXCP_RESET;
135 }
136 }
137
138
139
140
141
142
143
144
145
146
147
148
149#if defined(TARGET_PPC64)
150 if (excp_model == POWERPC_EXCP_POWER7 ||
151 excp_model == POWERPC_EXCP_POWER8) {
152 lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
153 if (excp_model == POWERPC_EXCP_POWER8) {
154 ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT;
155 } else {
156 ail = 0;
157 }
158 } else
159#endif
160 {
161 lpes0 = true;
162 ail = 0;
163 }
164
165
166
167
168
169 if (excp == POWERPC_EXCP_HV_EMU
170#if defined(TARGET_PPC64)
171 && !((env->mmu_model & POWERPC_MMU_64) && (env->msr_mask & MSR_HVB))
172#endif
173
174 ) {
175 excp = POWERPC_EXCP_PROGRAM;
176 }
177
178 switch (excp) {
179 case POWERPC_EXCP_NONE:
180
181 return;
182 case POWERPC_EXCP_CRITICAL:
183 switch (excp_model) {
184 case POWERPC_EXCP_40x:
185 srr0 = SPR_40x_SRR2;
186 srr1 = SPR_40x_SRR3;
187 break;
188 case POWERPC_EXCP_BOOKE:
189 srr0 = SPR_BOOKE_CSRR0;
190 srr1 = SPR_BOOKE_CSRR1;
191 break;
192 case POWERPC_EXCP_G2:
193 break;
194 default:
195 goto excp_invalid;
196 }
197 break;
198 case POWERPC_EXCP_MCHECK:
199 if (msr_me == 0) {
200
201
202
203 fprintf(stderr, "Machine check while not allowed. "
204 "Entering checkstop state\n");
205 if (qemu_log_separate()) {
206 qemu_log("Machine check while not allowed. "
207 "Entering checkstop state\n");
208 }
209 cs->halted = 1;
210 cpu_interrupt_exittb(cs);
211 }
212 if (env->msr_mask & MSR_HVB) {
213
214
215
216 new_msr |= (target_ulong)MSR_HVB;
217 }
218 ail = 0;
219
220
221 new_msr &= ~((target_ulong)1 << MSR_ME);
222
223
224 switch (excp_model) {
225 case POWERPC_EXCP_40x:
226 srr0 = SPR_40x_SRR2;
227 srr1 = SPR_40x_SRR3;
228 break;
229 case POWERPC_EXCP_BOOKE:
230
231 srr0 = SPR_BOOKE_MCSRR0;
232 srr1 = SPR_BOOKE_MCSRR1;
233 asrr0 = SPR_BOOKE_CSRR0;
234 asrr1 = SPR_BOOKE_CSRR1;
235 break;
236 default:
237 break;
238 }
239 break;
240 case POWERPC_EXCP_DSI:
241 LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx" DAR=" TARGET_FMT_lx
242 "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
243 break;
244 case POWERPC_EXCP_ISI:
245 LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx ", nip=" TARGET_FMT_lx
246 "\n", msr, env->nip);
247 msr |= env->error_code;
248 break;
249 case POWERPC_EXCP_EXTERNAL:
250 cs = CPU(cpu);
251
252 if (!lpes0) {
253 new_msr |= (target_ulong)MSR_HVB;
254 new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
255 srr0 = SPR_HSRR0;
256 srr1 = SPR_HSRR1;
257 }
258 if (env->mpic_proxy) {
259
260 env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
261 }
262 break;
263 case POWERPC_EXCP_ALIGN:
264
265
266
267
268
269 env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
270 break;
271 case POWERPC_EXCP_PROGRAM:
272 switch (env->error_code & ~0xF) {
273 case POWERPC_EXCP_FP:
274 if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
275 LOG_EXCP("Ignore floating point exception\n");
276 cs->exception_index = POWERPC_EXCP_NONE;
277 env->error_code = 0;
278 return;
279 }
280
281
282
283
284
285 msr |= 0x00100000;
286 env->spr[SPR_BOOKE_ESR] = ESR_FP;
287 break;
288 case POWERPC_EXCP_INVAL:
289 LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip);
290 msr |= 0x00080000;
291 env->spr[SPR_BOOKE_ESR] = ESR_PIL;
292 break;
293 case POWERPC_EXCP_PRIV:
294 msr |= 0x00040000;
295 env->spr[SPR_BOOKE_ESR] = ESR_PPR;
296 break;
297 case POWERPC_EXCP_TRAP:
298 msr |= 0x00020000;
299 env->spr[SPR_BOOKE_ESR] = ESR_PTR;
300 break;
301 default:
302
303 cpu_abort(cs, "Invalid program exception %d. Aborting\n",
304 env->error_code);
305 break;
306 }
307 break;
308 case POWERPC_EXCP_SYSCALL:
309 dump_syscall(env);
310 lev = env->error_code;
311
312
313
314
315 env->nip += 4;
316
317
318 if ((lev == 1) && cpu->vhyp) {
319 PPCVirtualHypervisorClass *vhc =
320 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
321 vhc->hypercall(cpu->vhyp, cpu);
322 return;
323 }
324 if (lev == 1) {
325 new_msr |= (target_ulong)MSR_HVB;
326 }
327 break;
328 case POWERPC_EXCP_FPU:
329 case POWERPC_EXCP_APU:
330 case POWERPC_EXCP_DECR:
331 break;
332 case POWERPC_EXCP_FIT:
333
334 LOG_EXCP("FIT exception\n");
335 break;
336 case POWERPC_EXCP_WDT:
337 LOG_EXCP("WDT exception\n");
338 switch (excp_model) {
339 case POWERPC_EXCP_BOOKE:
340 srr0 = SPR_BOOKE_CSRR0;
341 srr1 = SPR_BOOKE_CSRR1;
342 break;
343 default:
344 break;
345 }
346 break;
347 case POWERPC_EXCP_DTLB:
348 case POWERPC_EXCP_ITLB:
349 break;
350 case POWERPC_EXCP_DEBUG:
351 if (env->flags & POWERPC_FLAG_DE) {
352
353 srr0 = SPR_BOOKE_DSRR0;
354 srr1 = SPR_BOOKE_DSRR1;
355 asrr0 = SPR_BOOKE_CSRR0;
356 asrr1 = SPR_BOOKE_CSRR1;
357
358 } else {
359 cpu_abort(cs, "Debug exception triggered on unsupported model\n");
360 }
361 break;
362 case POWERPC_EXCP_SPEU:
363 env->spr[SPR_BOOKE_ESR] = ESR_SPV;
364 break;
365 case POWERPC_EXCP_EFPDI:
366
367 cpu_abort(cs, "Embedded floating point data exception "
368 "is not implemented yet !\n");
369 env->spr[SPR_BOOKE_ESR] = ESR_SPV;
370 break;
371 case POWERPC_EXCP_EFPRI:
372
373 cpu_abort(cs, "Embedded floating point round exception "
374 "is not implemented yet !\n");
375 env->spr[SPR_BOOKE_ESR] = ESR_SPV;
376 break;
377 case POWERPC_EXCP_EPERFM:
378
379 cpu_abort(cs,
380 "Performance counter exception is not implemented yet !\n");
381 break;
382 case POWERPC_EXCP_DOORI:
383 break;
384 case POWERPC_EXCP_DOORCI:
385 srr0 = SPR_BOOKE_CSRR0;
386 srr1 = SPR_BOOKE_CSRR1;
387 break;
388 case POWERPC_EXCP_RESET:
389
390 if (msr_pow) {
391
392 msr |= 0x10000;
393 new_msr |= ((target_ulong)1 << MSR_ME);
394 }
395 if (env->msr_mask & MSR_HVB) {
396
397
398
399 new_msr |= (target_ulong)MSR_HVB;
400 } else {
401 if (msr_pow) {
402 cpu_abort(cs, "Trying to deliver power-saving system reset "
403 "exception %d with no HV support\n", excp);
404 }
405 }
406 ail = 0;
407 break;
408 case POWERPC_EXCP_DSEG:
409 case POWERPC_EXCP_ISEG:
410 case POWERPC_EXCP_TRACE:
411 break;
412 case POWERPC_EXCP_HDECR:
413 case POWERPC_EXCP_HDSI:
414 case POWERPC_EXCP_HISI:
415 case POWERPC_EXCP_HDSEG:
416 case POWERPC_EXCP_HISEG:
417 case POWERPC_EXCP_SDOOR_HV:
418 case POWERPC_EXCP_HV_EMU:
419 srr0 = SPR_HSRR0;
420 srr1 = SPR_HSRR1;
421 new_msr |= (target_ulong)MSR_HVB;
422 new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
423 break;
424 case POWERPC_EXCP_VPU:
425 case POWERPC_EXCP_VSXU:
426 case POWERPC_EXCP_FU:
427#ifdef TARGET_PPC64
428 env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
429#endif
430 break;
431 case POWERPC_EXCP_PIT:
432 LOG_EXCP("PIT exception\n");
433 break;
434 case POWERPC_EXCP_IO:
435
436 cpu_abort(cs, "601 IO error exception is not implemented yet !\n");
437 break;
438 case POWERPC_EXCP_RUNM:
439
440 cpu_abort(cs, "601 run mode exception is not implemented yet !\n");
441 break;
442 case POWERPC_EXCP_EMUL:
443
444 cpu_abort(cs, "602 emulation trap exception "
445 "is not implemented yet !\n");
446 break;
447 case POWERPC_EXCP_IFTLB:
448 switch (excp_model) {
449 case POWERPC_EXCP_602:
450 case POWERPC_EXCP_603:
451 case POWERPC_EXCP_603E:
452 case POWERPC_EXCP_G2:
453 goto tlb_miss_tgpr;
454 case POWERPC_EXCP_7x5:
455 goto tlb_miss;
456 case POWERPC_EXCP_74xx:
457 goto tlb_miss_74xx;
458 default:
459 cpu_abort(cs, "Invalid instruction TLB miss exception\n");
460 break;
461 }
462 break;
463 case POWERPC_EXCP_DLTLB:
464 switch (excp_model) {
465 case POWERPC_EXCP_602:
466 case POWERPC_EXCP_603:
467 case POWERPC_EXCP_603E:
468 case POWERPC_EXCP_G2:
469 goto tlb_miss_tgpr;
470 case POWERPC_EXCP_7x5:
471 goto tlb_miss;
472 case POWERPC_EXCP_74xx:
473 goto tlb_miss_74xx;
474 default:
475 cpu_abort(cs, "Invalid data load TLB miss exception\n");
476 break;
477 }
478 break;
479 case POWERPC_EXCP_DSTLB:
480 switch (excp_model) {
481 case POWERPC_EXCP_602:
482 case POWERPC_EXCP_603:
483 case POWERPC_EXCP_603E:
484 case POWERPC_EXCP_G2:
485 tlb_miss_tgpr:
486
487 if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
488 new_msr |= (target_ulong)1 << MSR_TGPR;
489 hreg_swap_gpr_tgpr(env);
490 }
491 goto tlb_miss;
492 case POWERPC_EXCP_7x5:
493 tlb_miss:
494#if defined(DEBUG_SOFTWARE_TLB)
495 if (qemu_log_enabled()) {
496 const char *es;
497 target_ulong *miss, *cmp;
498 int en;
499
500 if (excp == POWERPC_EXCP_IFTLB) {
501 es = "I";
502 en = 'I';
503 miss = &env->spr[SPR_IMISS];
504 cmp = &env->spr[SPR_ICMP];
505 } else {
506 if (excp == POWERPC_EXCP_DLTLB) {
507 es = "DL";
508 } else {
509 es = "DS";
510 }
511 en = 'D';
512 miss = &env->spr[SPR_DMISS];
513 cmp = &env->spr[SPR_DCMP];
514 }
515 qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
516 TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 "
517 TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
518 env->spr[SPR_HASH1], env->spr[SPR_HASH2],
519 env->error_code);
520 }
521#endif
522 msr |= env->crf[0] << 28;
523 msr |= env->error_code;
524
525 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
526 break;
527 case POWERPC_EXCP_74xx:
528 tlb_miss_74xx:
529#if defined(DEBUG_SOFTWARE_TLB)
530 if (qemu_log_enabled()) {
531 const char *es;
532 target_ulong *miss, *cmp;
533 int en;
534
535 if (excp == POWERPC_EXCP_IFTLB) {
536 es = "I";
537 en = 'I';
538 miss = &env->spr[SPR_TLBMISS];
539 cmp = &env->spr[SPR_PTEHI];
540 } else {
541 if (excp == POWERPC_EXCP_DLTLB) {
542 es = "DL";
543 } else {
544 es = "DS";
545 }
546 en = 'D';
547 miss = &env->spr[SPR_TLBMISS];
548 cmp = &env->spr[SPR_PTEHI];
549 }
550 qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
551 TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
552 env->error_code);
553 }
554#endif
555 msr |= env->error_code;
556 break;
557 default:
558 cpu_abort(cs, "Invalid data store TLB miss exception\n");
559 break;
560 }
561 break;
562 case POWERPC_EXCP_FPA:
563
564 cpu_abort(cs, "Floating point assist exception "
565 "is not implemented yet !\n");
566 break;
567 case POWERPC_EXCP_DABR:
568
569 cpu_abort(cs, "DABR exception is not implemented yet !\n");
570 break;
571 case POWERPC_EXCP_IABR:
572
573 cpu_abort(cs, "IABR exception is not implemented yet !\n");
574 break;
575 case POWERPC_EXCP_SMI:
576
577 cpu_abort(cs, "SMI exception is not implemented yet !\n");
578 break;
579 case POWERPC_EXCP_THERM:
580
581 cpu_abort(cs, "Thermal management exception "
582 "is not implemented yet !\n");
583 break;
584 case POWERPC_EXCP_PERFM:
585
586 cpu_abort(cs,
587 "Performance counter exception is not implemented yet !\n");
588 break;
589 case POWERPC_EXCP_VPUA:
590
591 cpu_abort(cs, "VPU assist exception is not implemented yet !\n");
592 break;
593 case POWERPC_EXCP_SOFTP:
594
595 cpu_abort(cs,
596 "970 soft-patch exception is not implemented yet !\n");
597 break;
598 case POWERPC_EXCP_MAINT:
599
600 cpu_abort(cs,
601 "970 maintenance exception is not implemented yet !\n");
602 break;
603 case POWERPC_EXCP_MEXTBR:
604
605 cpu_abort(cs, "Maskable external exception "
606 "is not implemented yet !\n");
607 break;
608 case POWERPC_EXCP_NMEXTBR:
609
610 cpu_abort(cs, "Non maskable external exception "
611 "is not implemented yet !\n");
612 break;
613 default:
614 excp_invalid:
615 cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
616 break;
617 }
618
619
620 env->spr[srr0] = env->nip;
621
622
623 env->spr[srr1] = msr;
624
625
626 if (!(env->msr_mask & MSR_HVB)) {
627 if (new_msr & MSR_HVB) {
628 cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
629 "no HV support\n", excp);
630 }
631 if (srr0 == SPR_HSRR0) {
632 cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
633 "no HV support\n", excp);
634 }
635 }
636
637
638 if (asrr0 != -1) {
639 env->spr[asrr0] = env->spr[srr0];
640 }
641 if (asrr1 != -1) {
642 env->spr[asrr1] = env->spr[srr1];
643 }
644
645
646
647
648#ifdef TARGET_PPC64
649 if (excp_model == POWERPC_EXCP_POWER7) {
650 if (!(new_msr & MSR_HVB) && (env->spr[SPR_LPCR] & LPCR_ILE)) {
651 new_msr |= (target_ulong)1 << MSR_LE;
652 }
653 } else if (excp_model == POWERPC_EXCP_POWER8) {
654 if (new_msr & MSR_HVB) {
655 if (env->spr[SPR_HID0] & (HID0_HILE | HID0_POWER9_HILE)) {
656 new_msr |= (target_ulong)1 << MSR_LE;
657 }
658 } else if (env->spr[SPR_LPCR] & LPCR_ILE) {
659 new_msr |= (target_ulong)1 << MSR_LE;
660 }
661 } else if (msr_ile) {
662 new_msr |= (target_ulong)1 << MSR_LE;
663 }
664#else
665 if (msr_ile) {
666 new_msr |= (target_ulong)1 << MSR_LE;
667 }
668#endif
669
670
671 vector = env->excp_vectors[excp];
672 if (vector == (target_ulong)-1ULL) {
673 cpu_abort(cs, "Raised an exception without defined vector %d\n",
674 excp);
675 }
676 vector |= env->excp_prefix;
677
678
679
680
681 if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1) ||
682 ((new_msr & MSR_HVB) && !(msr & MSR_HVB))) {
683 ail = 0;
684 }
685
686 if (ail) {
687 new_msr |= (1 << MSR_IR) | (1 << MSR_DR);
688 switch(ail) {
689 case AIL_0001_8000:
690 vector |= 0x18000;
691 break;
692 case AIL_C000_0000_0000_4000:
693 vector |= 0xc000000000004000ull;
694 break;
695 default:
696 cpu_abort(cs, "Invalid AIL combination %d\n", ail);
697 break;
698 }
699 }
700
701#if defined(TARGET_PPC64)
702 if (excp_model == POWERPC_EXCP_BOOKE) {
703 if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
704
705 new_msr |= (target_ulong)1 << MSR_CM;
706 } else {
707 vector = (uint32_t)vector;
708 }
709 } else {
710 if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) {
711 vector = (uint32_t)vector;
712 } else {
713 new_msr |= (target_ulong)1 << MSR_SF;
714 }
715 }
716#endif
717
718
719
720
721
722
723
724 env->msr = new_msr & env->msr_mask;
725 hreg_compute_hflags(env);
726 env->nip = vector;
727
728 cs->exception_index = POWERPC_EXCP_NONE;
729 env->error_code = 0;
730
731
732 env->reserve_addr = -1;
733
734
735
736
737 check_tlb_flush(env, false);
738}
739
740void ppc_cpu_do_interrupt(CPUState *cs)
741{
742 PowerPCCPU *cpu = POWERPC_CPU(cs);
743 CPUPPCState *env = &cpu->env;
744
745 powerpc_excp(cpu, env->excp_model, cs->exception_index);
746}
747
748static void ppc_hw_interrupt(CPUPPCState *env)
749{
750 PowerPCCPU *cpu = ppc_env_get_cpu(env);
751#if 0
752 CPUState *cs = CPU(cpu);
753
754 qemu_log_mask(CPU_LOG_INT, "%s: %p pending %08x req %08x me %d ee %d\n",
755 __func__, env, env->pending_interrupts,
756 cs->interrupt_request, (int)msr_me, (int)msr_ee);
757#endif
758
759 if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
760 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
761 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET);
762 return;
763 }
764
765 if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
766 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
767 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_MCHECK);
768 return;
769 }
770#if 0
771
772 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
773 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
774 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DEBUG);
775 return;
776 }
777#endif
778
779 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
780
781 bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE);
782 if ((msr_ee != 0 || msr_hv == 0) && hdice) {
783
784 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
785 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_HDECR);
786 return;
787 }
788 }
789
790 if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
791 bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
792 if (msr_ee != 0 || (env->has_hv_mode && msr_hv == 0 && !lpes0)) {
793 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_EXTERNAL);
794 return;
795 }
796 }
797 if (msr_ce != 0) {
798
799 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
800
801
802
803#if 0
804 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
805#endif
806 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_CRITICAL);
807 return;
808 }
809 }
810 if (msr_ee != 0) {
811
812 if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
813 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
814 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_WDT);
815 return;
816 }
817 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) {
818 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
819 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORCI);
820 return;
821 }
822
823 if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
824 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
825 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_FIT);
826 return;
827 }
828
829 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
830 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
831 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PIT);
832 return;
833 }
834
835 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
836 if (ppc_decr_clear_on_delivery(env)) {
837 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
838 }
839 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DECR);
840 return;
841 }
842 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
843 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
844 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORI);
845 return;
846 }
847 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDOORBELL)) {
848 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDOORBELL);
849 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_SDOOR_HV);
850 return;
851 }
852 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) {
853 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
854 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PERFM);
855 return;
856 }
857
858 if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
859 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
860 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_THERM);
861 return;
862 }
863 }
864}
865
866void ppc_cpu_do_system_reset(CPUState *cs)
867{
868 PowerPCCPU *cpu = POWERPC_CPU(cs);
869 CPUPPCState *env = &cpu->env;
870
871 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET);
872}
873#endif
874
875bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
876{
877 PowerPCCPU *cpu = POWERPC_CPU(cs);
878 CPUPPCState *env = &cpu->env;
879
880 if (interrupt_request & CPU_INTERRUPT_HARD) {
881 ppc_hw_interrupt(env);
882 if (env->pending_interrupts == 0) {
883 cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
884 }
885 return true;
886 }
887 return false;
888}
889
890#if defined(DEBUG_OP)
891static void cpu_dump_rfi(target_ulong RA, target_ulong msr)
892{
893 qemu_log("Return from exception at " TARGET_FMT_lx " with flags "
894 TARGET_FMT_lx "\n", RA, msr);
895}
896#endif
897
898
899
900
901void raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
902 uint32_t error_code, uintptr_t raddr)
903{
904 CPUState *cs = CPU(ppc_env_get_cpu(env));
905
906 cs->exception_index = exception;
907 env->error_code = error_code;
908 cpu_loop_exit_restore(cs, raddr);
909}
910
911void raise_exception_err(CPUPPCState *env, uint32_t exception,
912 uint32_t error_code)
913{
914 raise_exception_err_ra(env, exception, error_code, 0);
915}
916
917void raise_exception(CPUPPCState *env, uint32_t exception)
918{
919 raise_exception_err_ra(env, exception, 0, 0);
920}
921
922void raise_exception_ra(CPUPPCState *env, uint32_t exception,
923 uintptr_t raddr)
924{
925 raise_exception_err_ra(env, exception, 0, raddr);
926}
927
928void helper_raise_exception_err(CPUPPCState *env, uint32_t exception,
929 uint32_t error_code)
930{
931 raise_exception_err_ra(env, exception, error_code, 0);
932}
933
934void helper_raise_exception(CPUPPCState *env, uint32_t exception)
935{
936 raise_exception_err_ra(env, exception, 0, 0);
937}
938
939#if !defined(CONFIG_USER_ONLY)
940void helper_store_msr(CPUPPCState *env, target_ulong val)
941{
942 uint32_t excp = hreg_store_msr(env, val, 0);
943
944 if (excp != 0) {
945 CPUState *cs = CPU(ppc_env_get_cpu(env));
946 cpu_interrupt_exittb(cs);
947 raise_exception(env, excp);
948 }
949}
950
951#if defined(TARGET_PPC64)
952void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn)
953{
954 CPUState *cs;
955
956 cs = CPU(ppc_env_get_cpu(env));
957 cs->halted = 1;
958 env->in_pm_state = true;
959
960
961
962
963 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
964
965
966
967
968
969
970
971
972 env->msr |= (1ull << MSR_EE);
973 raise_exception(env, EXCP_HLT);
974}
975#endif
976
977static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
978{
979 CPUState *cs = CPU(ppc_env_get_cpu(env));
980
981
982 msr &= ~(1ULL << MSR_POW);
983
984#if defined(TARGET_PPC64)
985
986 if (!msr_is_64bit(env, msr)) {
987 nip = (uint32_t)nip;
988 }
989#else
990 nip = (uint32_t)nip;
991#endif
992
993 env->nip = nip & ~((target_ulong)0x00000003);
994 hreg_store_msr(env, msr, 1);
995#if defined(DEBUG_OP)
996 cpu_dump_rfi(env->nip, env->msr);
997#endif
998
999
1000
1001 cpu_interrupt_exittb(cs);
1002
1003 env->reserve_addr = -1;
1004
1005
1006 check_tlb_flush(env, false);
1007}
1008
1009void helper_rfi(CPUPPCState *env)
1010{
1011 do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful);
1012}
1013
1014#define MSR_BOOK3S_MASK
1015#if defined(TARGET_PPC64)
1016void helper_rfid(CPUPPCState *env)
1017{
1018
1019
1020
1021
1022
1023 do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1]);
1024}
1025
1026void helper_hrfid(CPUPPCState *env)
1027{
1028 do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
1029}
1030#endif
1031
1032
1033
1034void helper_40x_rfci(CPUPPCState *env)
1035{
1036 do_rfi(env, env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3]);
1037}
1038
1039void helper_rfci(CPUPPCState *env)
1040{
1041 do_rfi(env, env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1]);
1042}
1043
1044void helper_rfdi(CPUPPCState *env)
1045{
1046
1047 do_rfi(env, env->spr[SPR_BOOKE_DSRR0], env->spr[SPR_BOOKE_DSRR1]);
1048}
1049
1050void helper_rfmci(CPUPPCState *env)
1051{
1052
1053 do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
1054}
1055#endif
1056
1057void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
1058 uint32_t flags)
1059{
1060 if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
1061 ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
1062 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
1063 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
1064 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
1065 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
1066 POWERPC_EXCP_TRAP, GETPC());
1067 }
1068}
1069
1070#if defined(TARGET_PPC64)
1071void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
1072 uint32_t flags)
1073{
1074 if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
1075 ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
1076 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
1077 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
1078 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) {
1079 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
1080 POWERPC_EXCP_TRAP, GETPC());
1081 }
1082}
1083#endif
1084
1085#if !defined(CONFIG_USER_ONLY)
1086
1087
1088
1089void helper_rfsvc(CPUPPCState *env)
1090{
1091 do_rfi(env, env->lr, env->ctr & 0x0000FFFF);
1092}
1093
1094
1095static int dbell2irq(target_ulong rb)
1096{
1097 int msg = rb & DBELL_TYPE_MASK;
1098 int irq = -1;
1099
1100 switch (msg) {
1101 case DBELL_TYPE_DBELL:
1102 irq = PPC_INTERRUPT_DOORBELL;
1103 break;
1104 case DBELL_TYPE_DBELL_CRIT:
1105 irq = PPC_INTERRUPT_CDOORBELL;
1106 break;
1107 case DBELL_TYPE_G_DBELL:
1108 case DBELL_TYPE_G_DBELL_CRIT:
1109 case DBELL_TYPE_G_DBELL_MC:
1110
1111 default:
1112 break;
1113 }
1114
1115 return irq;
1116}
1117
1118void helper_msgclr(CPUPPCState *env, target_ulong rb)
1119{
1120 int irq = dbell2irq(rb);
1121
1122 if (irq < 0) {
1123 return;
1124 }
1125
1126 env->pending_interrupts &= ~(1 << irq);
1127}
1128
1129void helper_msgsnd(target_ulong rb)
1130{
1131 int irq = dbell2irq(rb);
1132 int pir = rb & DBELL_PIRTAG_MASK;
1133 CPUState *cs;
1134
1135 if (irq < 0) {
1136 return;
1137 }
1138
1139 qemu_mutex_lock_iothread();
1140 CPU_FOREACH(cs) {
1141 PowerPCCPU *cpu = POWERPC_CPU(cs);
1142 CPUPPCState *cenv = &cpu->env;
1143
1144 if ((rb & DBELL_BRDCAST) || (cenv->spr[SPR_BOOKE_PIR] == pir)) {
1145 cenv->pending_interrupts |= 1 << irq;
1146 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
1147 }
1148 }
1149 qemu_mutex_unlock_iothread();
1150}
1151
1152
1153static int book3s_dbell2irq(target_ulong rb)
1154{
1155 int msg = rb & DBELL_TYPE_MASK;
1156
1157
1158
1159
1160 return msg == DBELL_TYPE_DBELL_SERVER ? PPC_INTERRUPT_HDOORBELL : -1;
1161}
1162
1163void helper_book3s_msgclr(CPUPPCState *env, target_ulong rb)
1164{
1165 int irq = book3s_dbell2irq(rb);
1166
1167 if (irq < 0) {
1168 return;
1169 }
1170
1171 env->pending_interrupts &= ~(1 << irq);
1172}
1173
1174void helper_book3s_msgsnd(target_ulong rb)
1175{
1176 int irq = book3s_dbell2irq(rb);
1177 int pir = rb & DBELL_PROCIDTAG_MASK;
1178 CPUState *cs;
1179
1180 if (irq < 0) {
1181 return;
1182 }
1183
1184 qemu_mutex_lock_iothread();
1185 CPU_FOREACH(cs) {
1186 PowerPCCPU *cpu = POWERPC_CPU(cs);
1187 CPUPPCState *cenv = &cpu->env;
1188
1189
1190 if (cenv->spr_cb[SPR_PIR].default_value == pir) {
1191 cenv->pending_interrupts |= 1 << irq;
1192 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
1193 }
1194 }
1195 qemu_mutex_unlock_iothread();
1196}
1197#endif
1198
1199void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
1200 MMUAccessType access_type,
1201 int mmu_idx, uintptr_t retaddr)
1202{
1203 CPUPPCState *env = cs->env_ptr;
1204 uint32_t insn;
1205
1206
1207 cpu_restore_state(cs, retaddr, true);
1208 insn = cpu_ldl_code(env, env->nip);
1209
1210 cs->exception_index = POWERPC_EXCP_ALIGN;
1211 env->error_code = insn & 0x03FF0000;
1212 cpu_loop_exit(cs);
1213}
1214