LXR qemu/hw/alpha/pci.c

   1/*
   2 * QEMU Alpha PCI support functions.
   3 *
   4 * Some of this isn't very Alpha specific at all.
   5 *
   6 * ??? Sparse memory access not implemented.
   7 */
   8
   9#include "qemu/osdep.h"
  10#include "qemu-common.h"
  11#include "alpha_sys.h"
  12#include "qemu/log.h"
  13#include "sysemu/sysemu.h"
  14#include "trace.h"
  15
  16
  17/* Fallback for unassigned PCI I/O operations.  Avoids MCHK.  */
  18
  19static uint64_t ignore_read(void *opaque, hwaddr addr, unsigned size)
  20{
  21    return 0;
  22}
  23
  24static void ignore_write(void *opaque, hwaddr addr, uint64_t v, unsigned size)
  25{
  26}
  27
  28const MemoryRegionOps alpha_pci_ignore_ops = {
  29    .read = ignore_read,
  30    .write = ignore_write,
  31    .endianness = DEVICE_LITTLE_ENDIAN,
  32    .valid = {
  33        .min_access_size = 1,
  34        .max_access_size = 8,
  35    },
  36    .impl = {
  37        .min_access_size = 1,
  38        .max_access_size = 8,
  39    },
  40};
  41
  42
  43/* PCI config space reads/writes, to byte-word addressable memory.  */
  44static uint64_t bw_conf1_read(void *opaque, hwaddr addr,
  45                              unsigned size)
  46{
  47    PCIBus *b = opaque;
  48    return pci_data_read(b, addr, size);
  49}
  50
  51static void bw_conf1_write(void *opaque, hwaddr addr,
  52                           uint64_t val, unsigned size)
  53{
  54    PCIBus *b = opaque;
  55    pci_data_write(b, addr, val, size);
  56}
  57
  58const MemoryRegionOps alpha_pci_conf1_ops = {
  59    .read = bw_conf1_read,
  60    .write = bw_conf1_write,
  61    .endianness = DEVICE_LITTLE_ENDIAN,
  62    .impl = {
  63        .min_access_size = 1,
  64        .max_access_size = 4,
  65    },
  66};
  67
  68/* PCI/EISA Interrupt Acknowledge Cycle.  */
  69
  70static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size)
  71{
  72    return pic_read_irq(isa_pic);
  73}
  74
  75static void special_write(void *opaque, hwaddr addr,
  76                          uint64_t val, unsigned size)
  77{
  78    trace_alpha_pci_iack_write();
  79}
  80
  81const MemoryRegionOps alpha_pci_iack_ops = {
  82    .read = iack_read,
  83    .write = special_write,
  84    .endianness = DEVICE_LITTLE_ENDIAN,
  85    .valid = {
  86        .min_access_size = 4,
  87        .max_access_size = 4,
  88    },
  89    .impl = {
  90        .min_access_size = 4,
  91        .max_access_size = 4,
  92    },
  93};
  94