LXR qemu/hw/char/grlib

   1/*
   2 * QEMU GRLIB APB UART Emulator
   3 *
   4 * Copyright (c) 2010-2011 AdaCore
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#include "qemu/osdep.h"
  26#include "hw/sysbus.h"
  27#include "chardev/char-fe.h"
  28
  29#include "trace.h"
  30
  31#define UART_REG_SIZE 20     /* Size of memory mapped registers */
  32
  33/* UART status register fields */
  34#define UART_DATA_READY           (1 <<  0)
  35#define UART_TRANSMIT_SHIFT_EMPTY (1 <<  1)
  36#define UART_TRANSMIT_FIFO_EMPTY  (1 <<  2)
  37#define UART_BREAK_RECEIVED       (1 <<  3)
  38#define UART_OVERRUN              (1 <<  4)
  39#define UART_PARITY_ERROR         (1 <<  5)
  40#define UART_FRAMING_ERROR        (1 <<  6)
  41#define UART_TRANSMIT_FIFO_HALF   (1 <<  7)
  42#define UART_RECEIVE_FIFO_HALF    (1 <<  8)
  43#define UART_TRANSMIT_FIFO_FULL   (1 <<  9)
  44#define UART_RECEIVE_FIFO_FULL    (1 << 10)
  45
  46/* UART control register fields */
  47#define UART_RECEIVE_ENABLE          (1 <<  0)
  48#define UART_TRANSMIT_ENABLE         (1 <<  1)
  49#define UART_RECEIVE_INTERRUPT       (1 <<  2)
  50#define UART_TRANSMIT_INTERRUPT      (1 <<  3)
  51#define UART_PARITY_SELECT           (1 <<  4)
  52#define UART_PARITY_ENABLE           (1 <<  5)
  53#define UART_FLOW_CONTROL            (1 <<  6)
  54#define UART_LOOPBACK                (1 <<  7)
  55#define UART_EXTERNAL_CLOCK          (1 <<  8)
  56#define UART_RECEIVE_FIFO_INTERRUPT  (1 <<  9)
  57#define UART_TRANSMIT_FIFO_INTERRUPT (1 << 10)
  58#define UART_FIFO_DEBUG_MODE         (1 << 11)
  59#define UART_OUTPUT_ENABLE           (1 << 12)
  60#define UART_FIFO_AVAILABLE          (1 << 31)
  61
  62/* Memory mapped register offsets */
  63#define DATA_OFFSET       0x00
  64#define STATUS_OFFSET     0x04
  65#define CONTROL_OFFSET    0x08
  66#define SCALER_OFFSET     0x0C  /* not supported */
  67#define FIFO_DEBUG_OFFSET 0x10  /* not supported */
  68
  69#define FIFO_LENGTH 1024
  70
  71#define TYPE_GRLIB_APB_UART "grlib,apbuart"
  72#define GRLIB_APB_UART(obj) \
  73    OBJECT_CHECK(UART, (obj), TYPE_GRLIB_APB_UART)
  74
  75typedef struct UART {
  76    SysBusDevice parent_obj;
  77
  78    MemoryRegion iomem;
  79    qemu_irq irq;
  80
  81    CharBackend chr;
  82
  83    /* registers */
  84    uint32_t status;
  85    uint32_t control;
  86
  87    /* FIFO */
  88    char buffer[FIFO_LENGTH];
  89    int  len;
  90    int  current;
  91} UART;
  92
  93static int uart_data_to_read(UART *uart)
  94{
  95    return uart->current < uart->len;
  96}
  97
  98static char uart_pop(UART *uart)
  99{
 100    char ret;
 101
 102    if (uart->len == 0) {
 103        uart->status &= ~UART_DATA_READY;
 104        return 0;
 105    }
 106
 107    ret = uart->buffer[uart->current++];
 108
 109    if (uart->current >= uart->len) {
 110        /* Flush */
 111        uart->len     = 0;
 112        uart->current = 0;
 113    }
 114
 115    if (!uart_data_to_read(uart)) {
 116        uart->status &= ~UART_DATA_READY;
 117    }
 118
 119    return ret;
 120}
 121
 122static void uart_add_to_fifo(UART          *uart,
 123                             const uint8_t *buffer,
 124                             int            length)
 125{
 126    if (uart->len + length > FIFO_LENGTH) {
 127        abort();
 128    }
 129    memcpy(uart->buffer + uart->len, buffer, length);
 130    uart->len += length;
 131}
 132
 133static int grlib_apbuart_can_receive(void *opaque)
 134{
 135    UART *uart = opaque;
 136
 137    return FIFO_LENGTH - uart->len;
 138}
 139
 140static void grlib_apbuart_receive(void *opaque, const uint8_t *buf, int size)
 141{
 142    UART *uart = opaque;
 143
 144    if (uart->control & UART_RECEIVE_ENABLE) {
 145        uart_add_to_fifo(uart, buf, size);
 146
 147        uart->status |= UART_DATA_READY;
 148
 149        if (uart->control & UART_RECEIVE_INTERRUPT) {
 150            qemu_irq_pulse(uart->irq);
 151        }
 152    }
 153}
 154
 155static void grlib_apbuart_event(void *opaque, int event)
 156{
 157    trace_grlib_apbuart_event(event);
 158}
 159
 160
 161static uint64_t grlib_apbuart_read(void *opaque, hwaddr addr,
 162                                   unsigned size)
 163{
 164    UART     *uart = opaque;
 165
 166    addr &= 0xff;
 167
 168    /* Unit registers */
 169    switch (addr) {
 170    case DATA_OFFSET:
 171    case DATA_OFFSET + 3:       /* when only one byte read */
 172        return uart_pop(uart);
 173
 174    case STATUS_OFFSET:
 175        /* Read Only */
 176        return uart->status;
 177
 178    case CONTROL_OFFSET:
 179        return uart->control;
 180
 181    case SCALER_OFFSET:
 182        /* Not supported */
 183        return 0;
 184
 185    default:
 186        trace_grlib_apbuart_readl_unknown(addr);
 187        return 0;
 188    }
 189}
 190
 191static void grlib_apbuart_write(void *opaque, hwaddr addr,
 192                                uint64_t value, unsigned size)
 193{
 194    UART          *uart = opaque;
 195    unsigned char  c    = 0;
 196
 197    addr &= 0xff;
 198
 199    /* Unit registers */
 200    switch (addr) {
 201    case DATA_OFFSET:
 202    case DATA_OFFSET + 3:       /* When only one byte write */
 203        /* Transmit when character device available and transmitter enabled */
 204        if (qemu_chr_fe_backend_connected(&uart->chr) &&
 205            (uart->control & UART_TRANSMIT_ENABLE)) {
 206            c = value & 0xFF;
 207            /* XXX this blocks entire thread. Rewrite to use
 208             * qemu_chr_fe_write and background I/O callbacks */
 209            qemu_chr_fe_write_all(&uart->chr, &c, 1);
 210            /* Generate interrupt */
 211            if (uart->control & UART_TRANSMIT_INTERRUPT) {
 212                qemu_irq_pulse(uart->irq);
 213            }
 214        }
 215        return;
 216
 217    case STATUS_OFFSET:
 218        /* Read Only */
 219        return;
 220
 221    case CONTROL_OFFSET:
 222        uart->control = value;
 223        return;
 224
 225    case SCALER_OFFSET:
 226        /* Not supported */
 227        return;
 228
 229    default:
 230        break;
 231    }
 232
 233    trace_grlib_apbuart_writel_unknown(addr, value);
 234}
 235
 236static const MemoryRegionOps grlib_apbuart_ops = {
 237    .write      = grlib_apbuart_write,
 238    .read       = grlib_apbuart_read,
 239    .endianness = DEVICE_NATIVE_ENDIAN,
 240};
 241
 242static void grlib_apbuart_realize(DeviceState *dev, Error **errp)
 243{
 244    UART *uart = GRLIB_APB_UART(dev);
 245    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 246
 247    qemu_chr_fe_set_handlers(&uart->chr,
 248                             grlib_apbuart_can_receive,
 249                             grlib_apbuart_receive,
 250                             grlib_apbuart_event,
 251                             NULL, uart, NULL, true);
 252
 253    sysbus_init_irq(sbd, &uart->irq);
 254
 255    memory_region_init_io(&uart->iomem, OBJECT(uart), &grlib_apbuart_ops, uart,
 256                          "uart", UART_REG_SIZE);
 257
 258    sysbus_init_mmio(sbd, &uart->iomem);
 259}
 260
 261static void grlib_apbuart_reset(DeviceState *d)
 262{
 263    UART *uart = GRLIB_APB_UART(d);
 264
 265    /* Transmitter FIFO and shift registers are always empty in QEMU */
 266    uart->status =  UART_TRANSMIT_FIFO_EMPTY | UART_TRANSMIT_SHIFT_EMPTY;
 267    /* Everything is off */
 268    uart->control = 0;
 269    /* Flush receive FIFO */
 270    uart->len = 0;
 271    uart->current = 0;
 272}
 273
 274static Property grlib_apbuart_properties[] = {
 275    DEFINE_PROP_CHR("chrdev", UART, chr),
 276    DEFINE_PROP_END_OF_LIST(),
 277};
 278
 279static void grlib_apbuart_class_init(ObjectClass *klass, void *data)
 280{
 281    DeviceClass *dc = DEVICE_CLASS(klass);
 282
 283    dc->realize = grlib_apbuart_realize;
 284    dc->reset = grlib_apbuart_reset;
 285    dc->props = grlib_apbuart_properties;
 286}
 287
 288static const TypeInfo grlib_apbuart_info = {
 289    .name          = TYPE_GRLIB_APB_UART,
 290    .parent        = TYPE_SYS_BUS_DEVICE,
 291    .instance_size = sizeof(UART),
 292    .class_init    = grlib_apbuart_class_init,
 293};
 294
 295static void grlib_apbuart_register_types(void)
 296{
 297    type_register_static(&grlib_apbuart_info);
 298}
 299
 300type_init(grlib_apbuart_register_types)
 301