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21#include "qemu/osdep.h"
22#include "hw/i2c/imx_i2c.h"
23#include "hw/i2c/i2c.h"
24#include "qemu/log.h"
25
26#ifndef DEBUG_IMX_I2C
27#define DEBUG_IMX_I2C 0
28#endif
29
30#define DPRINTF(fmt, args...) \
31 do { \
32 if (DEBUG_IMX_I2C) { \
33 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_I2C, \
34 __func__, ##args); \
35 } \
36 } while (0)
37
38static const char *imx_i2c_get_regname(unsigned offset)
39{
40 switch (offset) {
41 case IADR_ADDR:
42 return "IADR";
43 case IFDR_ADDR:
44 return "IFDR";
45 case I2CR_ADDR:
46 return "I2CR";
47 case I2SR_ADDR:
48 return "I2SR";
49 case I2DR_ADDR:
50 return "I2DR";
51 default:
52 return "[?]";
53 }
54}
55
56static inline bool imx_i2c_is_enabled(IMXI2CState *s)
57{
58 return s->i2cr & I2CR_IEN;
59}
60
61static inline bool imx_i2c_interrupt_is_enabled(IMXI2CState *s)
62{
63 return s->i2cr & I2CR_IIEN;
64}
65
66static inline bool imx_i2c_is_master(IMXI2CState *s)
67{
68 return s->i2cr & I2CR_MSTA;
69}
70
71static void imx_i2c_reset(DeviceState *dev)
72{
73 IMXI2CState *s = IMX_I2C(dev);
74
75 if (s->address != ADDR_RESET) {
76 i2c_end_transfer(s->bus);
77 }
78
79 s->address = ADDR_RESET;
80 s->iadr = IADR_RESET;
81 s->ifdr = IFDR_RESET;
82 s->i2cr = I2CR_RESET;
83 s->i2sr = I2SR_RESET;
84 s->i2dr_read = I2DR_RESET;
85 s->i2dr_write = I2DR_RESET;
86}
87
88static inline void imx_i2c_raise_interrupt(IMXI2CState *s)
89{
90
91
92
93
94 if (imx_i2c_is_enabled(s) && imx_i2c_interrupt_is_enabled(s)) {
95 s->i2sr |= I2SR_IIF;
96 qemu_irq_raise(s->irq);
97 }
98}
99
100static uint64_t imx_i2c_read(void *opaque, hwaddr offset,
101 unsigned size)
102{
103 uint16_t value;
104 IMXI2CState *s = IMX_I2C(opaque);
105
106 switch (offset) {
107 case IADR_ADDR:
108 value = s->iadr;
109 break;
110 case IFDR_ADDR:
111 value = s->ifdr;
112 break;
113 case I2CR_ADDR:
114 value = s->i2cr;
115 break;
116 case I2SR_ADDR:
117 value = s->i2sr;
118 break;
119 case I2DR_ADDR:
120 value = s->i2dr_read;
121
122 if (imx_i2c_is_master(s)) {
123 uint8_t ret = 0xff;
124
125 if (s->address == ADDR_RESET) {
126
127 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read "
128 "without specifying the slave address\n",
129 TYPE_IMX_I2C, __func__);
130 } else if (s->i2cr & I2CR_MTX) {
131 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read "
132 "but MTX is set\n", TYPE_IMX_I2C, __func__);
133 } else {
134
135 ret = i2c_recv(s->bus);
136 imx_i2c_raise_interrupt(s);
137 }
138
139 s->i2dr_read = ret;
140 } else {
141 qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n",
142 TYPE_IMX_I2C, __func__);
143 }
144 break;
145 default:
146 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
147 HWADDR_PRIx "\n", TYPE_IMX_I2C, __func__, offset);
148 value = 0;
149 break;
150 }
151
152 DPRINTF("read %s [0x%" HWADDR_PRIx "] -> 0x%02x\n",
153 imx_i2c_get_regname(offset), offset, value);
154
155 return (uint64_t)value;
156}
157
158static void imx_i2c_write(void *opaque, hwaddr offset,
159 uint64_t value, unsigned size)
160{
161 IMXI2CState *s = IMX_I2C(opaque);
162
163 DPRINTF("write %s [0x%" HWADDR_PRIx "] <- 0x%02x\n",
164 imx_i2c_get_regname(offset), offset, (int)value);
165
166 value &= 0xff;
167
168 switch (offset) {
169 case IADR_ADDR:
170 s->iadr = value & IADR_MASK;
171
172 break;
173 case IFDR_ADDR:
174 s->ifdr = value & IFDR_MASK;
175 break;
176 case I2CR_ADDR:
177 if (imx_i2c_is_enabled(s) && ((value & I2CR_IEN) == 0)) {
178
179 uint16_t iadr = s->iadr;
180 imx_i2c_reset(DEVICE(s));
181 s->iadr = iadr;
182 } else {
183 s->i2cr = value & I2CR_MASK;
184
185 if (imx_i2c_is_master(s)) {
186
187 s->i2sr |= I2SR_IBB;
188 } else {
189
190 s->i2sr &= ~I2SR_IBB;
191
192
193
194
195
196 if (s->address != ADDR_RESET) {
197 i2c_end_transfer(s->bus);
198 s->address = ADDR_RESET;
199 }
200 }
201
202 if (s->i2cr & I2CR_RSTA) {
203
204 if (s->address != ADDR_RESET) {
205 i2c_end_transfer(s->bus);
206 s->address = ADDR_RESET;
207 s->i2cr &= ~I2CR_RSTA;
208 }
209 }
210 }
211 break;
212 case I2SR_ADDR:
213
214
215
216
217 if ((s->i2sr & I2SR_IIF) && !(value & I2SR_IIF)) {
218 s->i2sr &= ~I2SR_IIF;
219 qemu_irq_lower(s->irq);
220 }
221
222
223
224
225 if ((s->i2sr & I2SR_IAL) && !(value & I2SR_IAL)) {
226 s->i2sr &= ~I2SR_IAL;
227 }
228
229 break;
230 case I2DR_ADDR:
231
232 if (!imx_i2c_is_enabled(s)) {
233 break;
234 }
235
236 s->i2dr_write = value & I2DR_MASK;
237
238 if (imx_i2c_is_master(s)) {
239
240 if (s->address == ADDR_RESET) {
241 if (i2c_start_transfer(s->bus, extract32(s->i2dr_write, 1, 7),
242 extract32(s->i2dr_write, 0, 1))) {
243
244 s->i2sr |= I2SR_RXAK;
245 } else {
246 s->address = s->i2dr_write;
247 s->i2sr &= ~I2SR_RXAK;
248 imx_i2c_raise_interrupt(s);
249 }
250 } else {
251 if (i2c_send(s->bus, s->i2dr_write)) {
252
253 s->i2sr |= I2SR_RXAK;
254 s->address = ADDR_RESET;
255 i2c_end_transfer(s->bus);
256 } else {
257 s->i2sr &= ~I2SR_RXAK;
258 imx_i2c_raise_interrupt(s);
259 }
260 }
261 } else {
262 qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n",
263 TYPE_IMX_I2C, __func__);
264 }
265 break;
266 default:
267 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
268 HWADDR_PRIx "\n", TYPE_IMX_I2C, __func__, offset);
269 break;
270 }
271}
272
273static const MemoryRegionOps imx_i2c_ops = {
274 .read = imx_i2c_read,
275 .write = imx_i2c_write,
276 .valid.min_access_size = 1,
277 .valid.max_access_size = 2,
278 .endianness = DEVICE_NATIVE_ENDIAN,
279};
280
281static const VMStateDescription imx_i2c_vmstate = {
282 .name = TYPE_IMX_I2C,
283 .version_id = 1,
284 .minimum_version_id = 1,
285 .fields = (VMStateField[]) {
286 VMSTATE_UINT16(address, IMXI2CState),
287 VMSTATE_UINT16(iadr, IMXI2CState),
288 VMSTATE_UINT16(ifdr, IMXI2CState),
289 VMSTATE_UINT16(i2cr, IMXI2CState),
290 VMSTATE_UINT16(i2sr, IMXI2CState),
291 VMSTATE_UINT16(i2dr_read, IMXI2CState),
292 VMSTATE_UINT16(i2dr_write, IMXI2CState),
293 VMSTATE_END_OF_LIST()
294 }
295};
296
297static void imx_i2c_realize(DeviceState *dev, Error **errp)
298{
299 IMXI2CState *s = IMX_I2C(dev);
300
301 memory_region_init_io(&s->iomem, OBJECT(s), &imx_i2c_ops, s, TYPE_IMX_I2C,
302 IMX_I2C_MEM_SIZE);
303 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
304 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
305 s->bus = i2c_init_bus(DEVICE(dev), NULL);
306}
307
308static void imx_i2c_class_init(ObjectClass *klass, void *data)
309{
310 DeviceClass *dc = DEVICE_CLASS(klass);
311
312 dc->vmsd = &imx_i2c_vmstate;
313 dc->reset = imx_i2c_reset;
314 dc->realize = imx_i2c_realize;
315 dc->desc = "i.MX I2C Controller";
316}
317
318static const TypeInfo imx_i2c_type_info = {
319 .name = TYPE_IMX_I2C,
320 .parent = TYPE_SYS_BUS_DEVICE,
321 .instance_size = sizeof(IMXI2CState),
322 .class_init = imx_i2c_class_init,
323};
324
325static void imx_i2c_register_types(void)
326{
327 type_register_static(&imx_i2c_type_info);
328}
329
330type_init(imx_i2c_register_types)
331