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26#include "qemu/osdep.h"
27#include "hw/hw.h"
28#include "hw/pci/pci.h"
29#include "sysemu/block-backend.h"
30#include "sysemu/sysemu.h"
31#include "sysemu/blockdev.h"
32#include "sysemu/dma.h"
33
34#include "hw/ide/pci.h"
35#include "trace.h"
36
37static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size)
38{
39 BMDMAState *bm = opaque;
40 uint32_t val;
41
42 if (size != 1) {
43 return ((uint64_t)1 << (size * 8)) - 1;
44 }
45
46 switch(addr & 3) {
47 case 0:
48 val = bm->cmd;
49 break;
50 case 2:
51 val = bm->status;
52 break;
53 default:
54 val = 0xff;
55 break;
56 }
57
58 trace_bmdma_read(addr, val);
59 return val;
60}
61
62static void bmdma_write(void *opaque, hwaddr addr,
63 uint64_t val, unsigned size)
64{
65 BMDMAState *bm = opaque;
66
67 if (size != 1) {
68 return;
69 }
70
71 trace_bmdma_write(addr, val);
72
73 switch(addr & 3) {
74 case 0:
75 bmdma_cmd_writeb(bm, val);
76 break;
77 case 2:
78 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
79 break;
80 }
81}
82
83static const MemoryRegionOps piix_bmdma_ops = {
84 .read = bmdma_read,
85 .write = bmdma_write,
86};
87
88static void bmdma_setup_bar(PCIIDEState *d)
89{
90 int i;
91
92 memory_region_init(&d->bmdma_bar, OBJECT(d), "piix-bmdma-container", 16);
93 for(i = 0;i < 2; i++) {
94 BMDMAState *bm = &d->bmdma[i];
95
96 memory_region_init_io(&bm->extra_io, OBJECT(d), &piix_bmdma_ops, bm,
97 "piix-bmdma", 4);
98 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
99 memory_region_init_io(&bm->addr_ioport, OBJECT(d),
100 &bmdma_addr_ioport_ops, bm, "bmdma", 4);
101 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
102 }
103}
104
105static void piix3_reset(void *opaque)
106{
107 PCIIDEState *d = opaque;
108 PCIDevice *pd = PCI_DEVICE(d);
109 uint8_t *pci_conf = pd->config;
110 int i;
111
112 for (i = 0; i < 2; i++) {
113 ide_bus_reset(&d->bus[i]);
114 }
115
116
117 pci_conf[PCI_COMMAND] = 0x00;
118
119 pci_conf[PCI_COMMAND + 1] = 0x00;
120
121 pci_conf[PCI_STATUS] = PCI_STATUS_FAST_BACK;
122 pci_conf[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
123 pci_conf[0x20] = 0x01;
124}
125
126static void pci_piix_init_ports(PCIIDEState *d) {
127 static const struct {
128 int iobase;
129 int iobase2;
130 int isairq;
131 } port_info[] = {
132 {0x1f0, 0x3f6, 14},
133 {0x170, 0x376, 15},
134 };
135 int i;
136
137 for (i = 0; i < 2; i++) {
138 ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
139 ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
140 port_info[i].iobase2);
141 ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
142
143 bmdma_init(&d->bus[i], &d->bmdma[i], d);
144 d->bmdma[i].bus = &d->bus[i];
145 ide_register_restart_cb(&d->bus[i]);
146 }
147}
148
149static void pci_piix_ide_realize(PCIDevice *dev, Error **errp)
150{
151 PCIIDEState *d = PCI_IDE(dev);
152 uint8_t *pci_conf = dev->config;
153
154 pci_conf[PCI_CLASS_PROG] = 0x80;
155
156 qemu_register_reset(piix3_reset, d);
157
158 bmdma_setup_bar(d);
159 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
160
161 vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
162
163 pci_piix_init_ports(d);
164}
165
166int pci_piix3_xen_ide_unplug(DeviceState *dev, bool aux)
167{
168 PCIIDEState *pci_ide;
169 DriveInfo *di;
170 int i;
171 IDEDevice *idedev;
172
173 pci_ide = PCI_IDE(dev);
174
175 for (i = aux ? 1 : 0; i < 4; i++) {
176 di = drive_get_by_index(IF_IDE, i);
177 if (di != NULL && !di->media_cd) {
178 BlockBackend *blk = blk_by_legacy_dinfo(di);
179 DeviceState *ds = blk_get_attached_dev(blk);
180
181 blk_drain(blk);
182 blk_flush(blk);
183
184 if (ds) {
185 blk_detach_dev(blk, ds);
186 }
187 pci_ide->bus[di->bus].ifs[di->unit].blk = NULL;
188 if (!(i % 2)) {
189 idedev = pci_ide->bus[di->bus].master;
190 } else {
191 idedev = pci_ide->bus[di->bus].slave;
192 }
193 idedev->conf.blk = NULL;
194 monitor_remove_blk(blk);
195 blk_unref(blk);
196 }
197 }
198 qdev_reset_all(DEVICE(dev));
199 return 0;
200}
201
202PCIDevice *pci_piix3_xen_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
203{
204 PCIDevice *dev;
205
206 dev = pci_create_simple(bus, devfn, "piix3-ide-xen");
207 pci_ide_create_devs(dev, hd_table);
208 return dev;
209}
210
211static void pci_piix_ide_exitfn(PCIDevice *dev)
212{
213 PCIIDEState *d = PCI_IDE(dev);
214 unsigned i;
215
216 for (i = 0; i < 2; ++i) {
217 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
218 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
219 }
220}
221
222
223
224PCIDevice *pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
225{
226 PCIDevice *dev;
227
228 dev = pci_create_simple(bus, devfn, "piix3-ide");
229 pci_ide_create_devs(dev, hd_table);
230 return dev;
231}
232
233
234
235PCIDevice *pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
236{
237 PCIDevice *dev;
238
239 dev = pci_create_simple(bus, devfn, "piix4-ide");
240 pci_ide_create_devs(dev, hd_table);
241 return dev;
242}
243
244static void piix3_ide_class_init(ObjectClass *klass, void *data)
245{
246 DeviceClass *dc = DEVICE_CLASS(klass);
247 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
248
249 k->realize = pci_piix_ide_realize;
250 k->exit = pci_piix_ide_exitfn;
251 k->vendor_id = PCI_VENDOR_ID_INTEL;
252 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
253 k->class_id = PCI_CLASS_STORAGE_IDE;
254 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
255 dc->hotpluggable = false;
256}
257
258static const TypeInfo piix3_ide_info = {
259 .name = "piix3-ide",
260 .parent = TYPE_PCI_IDE,
261 .class_init = piix3_ide_class_init,
262};
263
264static const TypeInfo piix3_ide_xen_info = {
265 .name = "piix3-ide-xen",
266 .parent = TYPE_PCI_IDE,
267 .class_init = piix3_ide_class_init,
268};
269
270static void piix4_ide_class_init(ObjectClass *klass, void *data)
271{
272 DeviceClass *dc = DEVICE_CLASS(klass);
273 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
274
275 k->realize = pci_piix_ide_realize;
276 k->exit = pci_piix_ide_exitfn;
277 k->vendor_id = PCI_VENDOR_ID_INTEL;
278 k->device_id = PCI_DEVICE_ID_INTEL_82371AB;
279 k->class_id = PCI_CLASS_STORAGE_IDE;
280 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
281 dc->hotpluggable = false;
282}
283
284static const TypeInfo piix4_ide_info = {
285 .name = "piix4-ide",
286 .parent = TYPE_PCI_IDE,
287 .class_init = piix4_ide_class_init,
288};
289
290static void piix_ide_register_types(void)
291{
292 type_register_static(&piix3_ide_info);
293 type_register_static(&piix3_ide_xen_info);
294 type_register_static(&piix4_ide_info);
295}
296
297type_init(piix_ide_register_types)
298
