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21#include "qemu/osdep.h"
22#include "hw/sysbus.h"
23#include "gic_internal.h"
24#include "qapi/error.h"
25#include "qom/cpu.h"
26#include "qemu/log.h"
27#include "trace.h"
28#include "sysemu/kvm.h"
29
30
31
32#ifdef DEBUG_GIC
33#define DEBUG_GIC_GATE 1
34#else
35#define DEBUG_GIC_GATE 0
36#endif
37
38#define DPRINTF(fmt, ...) do { \
39 if (DEBUG_GIC_GATE) { \
40 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \
41 } \
42 } while (0)
43
44static const uint8_t gic_id_11mpcore[] = {
45 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
46};
47
48static const uint8_t gic_id_gicv1[] = {
49 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
50};
51
52static const uint8_t gic_id_gicv2[] = {
53 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
54};
55
56static inline int gic_get_current_cpu(GICState *s)
57{
58 if (s->num_cpu > 1) {
59 return current_cpu->cpu_index;
60 }
61 return 0;
62}
63
64static inline int gic_get_current_vcpu(GICState *s)
65{
66 return gic_get_current_cpu(s) + GIC_NCPU;
67}
68
69
70
71
72static inline bool gic_has_groups(GICState *s)
73{
74 return s->revision == 2 || s->security_extn;
75}
76
77static inline bool gic_cpu_ns_access(GICState *s, int cpu, MemTxAttrs attrs)
78{
79 return !gic_is_vcpu(cpu) && s->security_extn && !attrs.secure;
80}
81
82static inline void gic_get_best_irq(GICState *s, int cpu,
83 int *best_irq, int *best_prio, int *group)
84{
85 int irq;
86 int cm = 1 << cpu;
87
88 *best_irq = 1023;
89 *best_prio = 0x100;
90
91 for (irq = 0; irq < s->num_irq; irq++) {
92 if (GIC_DIST_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) &&
93 (!GIC_DIST_TEST_ACTIVE(irq, cm)) &&
94 (irq < GIC_INTERNAL || GIC_DIST_TARGET(irq) & cm)) {
95 if (GIC_DIST_GET_PRIORITY(irq, cpu) < *best_prio) {
96 *best_prio = GIC_DIST_GET_PRIORITY(irq, cpu);
97 *best_irq = irq;
98 }
99 }
100 }
101
102 if (*best_irq < 1023) {
103 *group = GIC_DIST_TEST_GROUP(*best_irq, cm);
104 }
105}
106
107static inline void gic_get_best_virq(GICState *s, int cpu,
108 int *best_irq, int *best_prio, int *group)
109{
110 int lr_idx = 0;
111
112 *best_irq = 1023;
113 *best_prio = 0x100;
114
115 for (lr_idx = 0; lr_idx < s->num_lrs; lr_idx++) {
116 uint32_t lr_entry = s->h_lr[lr_idx][cpu];
117 int state = GICH_LR_STATE(lr_entry);
118
119 if (state == GICH_LR_STATE_PENDING) {
120 int prio = GICH_LR_PRIORITY(lr_entry);
121
122 if (prio < *best_prio) {
123 *best_prio = prio;
124 *best_irq = GICH_LR_VIRT_ID(lr_entry);
125 *group = GICH_LR_GROUP(lr_entry);
126 }
127 }
128 }
129}
130
131
132
133
134
135
136
137
138
139static inline bool gic_irq_signaling_enabled(GICState *s, int cpu, bool virt,
140 int group_mask)
141{
142 if (!virt && !(s->ctlr & group_mask)) {
143 return false;
144 }
145
146 if (virt && !(s->h_hcr[cpu] & R_GICH_HCR_EN_MASK)) {
147 return false;
148 }
149
150 if (!(s->cpu_ctlr[cpu] & group_mask)) {
151 return false;
152 }
153
154 return true;
155}
156
157
158
159static inline void gic_update_internal(GICState *s, bool virt)
160{
161 int best_irq;
162 int best_prio;
163 int irq_level, fiq_level;
164 int cpu, cpu_iface;
165 int group = 0;
166 qemu_irq *irq_lines = virt ? s->parent_virq : s->parent_irq;
167 qemu_irq *fiq_lines = virt ? s->parent_vfiq : s->parent_fiq;
168
169 for (cpu = 0; cpu < s->num_cpu; cpu++) {
170 cpu_iface = virt ? (cpu + GIC_NCPU) : cpu;
171
172 s->current_pending[cpu_iface] = 1023;
173 if (!gic_irq_signaling_enabled(s, cpu, virt,
174 GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) {
175 qemu_irq_lower(irq_lines[cpu]);
176 qemu_irq_lower(fiq_lines[cpu]);
177 continue;
178 }
179
180 if (virt) {
181 gic_get_best_virq(s, cpu, &best_irq, &best_prio, &group);
182 } else {
183 gic_get_best_irq(s, cpu, &best_irq, &best_prio, &group);
184 }
185
186 if (best_irq != 1023) {
187 trace_gic_update_bestirq(virt ? "vcpu" : "cpu", cpu,
188 best_irq, best_prio,
189 s->priority_mask[cpu_iface],
190 s->running_priority[cpu_iface]);
191 }
192
193 irq_level = fiq_level = 0;
194
195 if (best_prio < s->priority_mask[cpu_iface]) {
196 s->current_pending[cpu_iface] = best_irq;
197 if (best_prio < s->running_priority[cpu_iface]) {
198 if (gic_irq_signaling_enabled(s, cpu, virt, 1 << group)) {
199 if (group == 0 &&
200 s->cpu_ctlr[cpu_iface] & GICC_CTLR_FIQ_EN) {
201 DPRINTF("Raised pending FIQ %d (cpu %d)\n",
202 best_irq, cpu_iface);
203 fiq_level = 1;
204 trace_gic_update_set_irq(cpu, virt ? "vfiq" : "fiq",
205 fiq_level);
206 } else {
207 DPRINTF("Raised pending IRQ %d (cpu %d)\n",
208 best_irq, cpu_iface);
209 irq_level = 1;
210 trace_gic_update_set_irq(cpu, virt ? "virq" : "irq",
211 irq_level);
212 }
213 }
214 }
215 }
216
217 qemu_set_irq(irq_lines[cpu], irq_level);
218 qemu_set_irq(fiq_lines[cpu], fiq_level);
219 }
220}
221
222static void gic_update(GICState *s)
223{
224 gic_update_internal(s, false);
225}
226
227
228
229
230static inline bool gic_lr_entry_is_free(uint32_t entry)
231{
232 return (GICH_LR_STATE(entry) == GICH_LR_STATE_INVALID)
233 && (GICH_LR_HW(entry) || !GICH_LR_EOI(entry));
234}
235
236
237
238
239static inline bool gic_lr_entry_is_eoi(uint32_t entry)
240{
241 return (GICH_LR_STATE(entry) == GICH_LR_STATE_INVALID)
242 && !GICH_LR_HW(entry) && GICH_LR_EOI(entry);
243}
244
245static inline void gic_extract_lr_info(GICState *s, int cpu,
246 int *num_eoi, int *num_valid, int *num_pending)
247{
248 int lr_idx;
249
250 *num_eoi = 0;
251 *num_valid = 0;
252 *num_pending = 0;
253
254 for (lr_idx = 0; lr_idx < s->num_lrs; lr_idx++) {
255 uint32_t *entry = &s->h_lr[lr_idx][cpu];
256
257 if (gic_lr_entry_is_eoi(*entry)) {
258 (*num_eoi)++;
259 }
260
261 if (GICH_LR_STATE(*entry) != GICH_LR_STATE_INVALID) {
262 (*num_valid)++;
263 }
264
265 if (GICH_LR_STATE(*entry) == GICH_LR_STATE_PENDING) {
266 (*num_pending)++;
267 }
268 }
269}
270
271static void gic_compute_misr(GICState *s, int cpu)
272{
273 uint32_t value = 0;
274 int vcpu = cpu + GIC_NCPU;
275
276 int num_eoi, num_valid, num_pending;
277
278 gic_extract_lr_info(s, cpu, &num_eoi, &num_valid, &num_pending);
279
280
281 if (num_eoi) {
282 value |= R_GICH_MISR_EOI_MASK;
283 }
284
285
286 if ((s->h_hcr[cpu] & R_GICH_HCR_UIE_MASK) && (num_valid < 2)) {
287 value |= R_GICH_MISR_U_MASK;
288 }
289
290
291 if ((s->h_hcr[cpu] & R_GICH_HCR_LRENPIE_MASK) &&
292 ((s->h_hcr[cpu] & R_GICH_HCR_EOICount_MASK) != 0)) {
293 value |= R_GICH_MISR_LRENP_MASK;
294 }
295
296
297 if ((s->h_hcr[cpu] & R_GICH_HCR_NPIE_MASK) && (num_pending == 0)) {
298 value |= R_GICH_MISR_NP_MASK;
299 }
300
301
302 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0EIE_MASK) &&
303 (s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP0)) {
304 value |= R_GICH_MISR_VGrp0E_MASK;
305 }
306
307
308 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0DIE_MASK) &&
309 !(s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP0)) {
310 value |= R_GICH_MISR_VGrp0D_MASK;
311 }
312
313
314 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1EIE_MASK) &&
315 (s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP1)) {
316 value |= R_GICH_MISR_VGrp1E_MASK;
317 }
318
319
320 if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1DIE_MASK) &&
321 !(s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP1)) {
322 value |= R_GICH_MISR_VGrp1D_MASK;
323 }
324
325 s->h_misr[cpu] = value;
326}
327
328static void gic_update_maintenance(GICState *s)
329{
330 int cpu = 0;
331 int maint_level;
332
333 for (cpu = 0; cpu < s->num_cpu; cpu++) {
334 gic_compute_misr(s, cpu);
335 maint_level = (s->h_hcr[cpu] & R_GICH_HCR_EN_MASK) && s->h_misr[cpu];
336
337 trace_gic_update_maintenance_irq(cpu, maint_level);
338 qemu_set_irq(s->maintenance_irq[cpu], maint_level);
339 }
340}
341
342static void gic_update_virt(GICState *s)
343{
344 gic_update_internal(s, true);
345 gic_update_maintenance(s);
346}
347
348static void gic_set_irq_11mpcore(GICState *s, int irq, int level,
349 int cm, int target)
350{
351 if (level) {
352 GIC_DIST_SET_LEVEL(irq, cm);
353 if (GIC_DIST_TEST_EDGE_TRIGGER(irq) || GIC_DIST_TEST_ENABLED(irq, cm)) {
354 DPRINTF("Set %d pending mask %x\n", irq, target);
355 GIC_DIST_SET_PENDING(irq, target);
356 }
357 } else {
358 GIC_DIST_CLEAR_LEVEL(irq, cm);
359 }
360}
361
362static void gic_set_irq_generic(GICState *s, int irq, int level,
363 int cm, int target)
364{
365 if (level) {
366 GIC_DIST_SET_LEVEL(irq, cm);
367 DPRINTF("Set %d pending mask %x\n", irq, target);
368 if (GIC_DIST_TEST_EDGE_TRIGGER(irq)) {
369 GIC_DIST_SET_PENDING(irq, target);
370 }
371 } else {
372 GIC_DIST_CLEAR_LEVEL(irq, cm);
373 }
374}
375
376
377static void gic_set_irq(void *opaque, int irq, int level)
378{
379
380
381
382
383
384
385 GICState *s = (GICState *)opaque;
386 int cm, target;
387 if (irq < (s->num_irq - GIC_INTERNAL)) {
388
389 cm = ALL_CPU_MASK;
390 irq += GIC_INTERNAL;
391 target = GIC_DIST_TARGET(irq);
392 } else {
393 int cpu;
394 irq -= (s->num_irq - GIC_INTERNAL);
395 cpu = irq / GIC_INTERNAL;
396 irq %= GIC_INTERNAL;
397 cm = 1 << cpu;
398 target = cm;
399 }
400
401 assert(irq >= GIC_NR_SGIS);
402
403 if (level == GIC_DIST_TEST_LEVEL(irq, cm)) {
404 return;
405 }
406
407 if (s->revision == REV_11MPCORE) {
408 gic_set_irq_11mpcore(s, irq, level, cm, target);
409 } else {
410 gic_set_irq_generic(s, irq, level, cm, target);
411 }
412 trace_gic_set_irq(irq, level, cm, target);
413
414 gic_update(s);
415}
416
417static uint16_t gic_get_current_pending_irq(GICState *s, int cpu,
418 MemTxAttrs attrs)
419{
420 uint16_t pending_irq = s->current_pending[cpu];
421
422 if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) {
423 int group = gic_test_group(s, pending_irq, cpu);
424
425
426
427
428 bool secure = !gic_cpu_ns_access(s, cpu, attrs);
429
430 if (group == 0 && !secure) {
431
432 return 1023;
433 }
434 if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) {
435
436
437
438 return 1022;
439 }
440 }
441 return pending_irq;
442}
443
444static int gic_get_group_priority(GICState *s, int cpu, int irq)
445{
446
447
448
449
450 int bpr;
451 uint32_t mask;
452
453 if (gic_has_groups(s) &&
454 !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) &&
455 gic_test_group(s, irq, cpu)) {
456 bpr = s->abpr[cpu] - 1;
457 assert(bpr >= 0);
458 } else {
459 bpr = s->bpr[cpu];
460 }
461
462
463
464
465
466 mask = ~0U << ((bpr & 7) + 1);
467
468 return gic_get_priority(s, irq, cpu) & mask;
469}
470
471static void gic_activate_irq(GICState *s, int cpu, int irq)
472{
473
474
475
476 int prio = gic_get_group_priority(s, cpu, irq);
477 int min_bpr = gic_is_vcpu(cpu) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR;
478 int preemption_level = prio >> (min_bpr + 1);
479 int regno = preemption_level / 32;
480 int bitno = preemption_level % 32;
481 uint32_t *papr = NULL;
482
483 if (gic_is_vcpu(cpu)) {
484 assert(regno == 0);
485 papr = &s->h_apr[gic_get_vcpu_real_id(cpu)];
486 } else if (gic_has_groups(s) && gic_test_group(s, irq, cpu)) {
487 papr = &s->nsapr[regno][cpu];
488 } else {
489 papr = &s->apr[regno][cpu];
490 }
491
492 *papr |= (1 << bitno);
493
494 s->running_priority[cpu] = prio;
495 gic_set_active(s, irq, cpu);
496}
497
498static int gic_get_prio_from_apr_bits(GICState *s, int cpu)
499{
500
501
502
503 int i;
504
505 if (gic_is_vcpu(cpu)) {
506 uint32_t apr = s->h_apr[gic_get_vcpu_real_id(cpu)];
507 if (apr) {
508 return ctz32(apr) << (GIC_VIRT_MIN_BPR + 1);
509 } else {
510 return 0x100;
511 }
512 }
513
514 for (i = 0; i < GIC_NR_APRS; i++) {
515 uint32_t apr = s->apr[i][cpu] | s->nsapr[i][cpu];
516 if (!apr) {
517 continue;
518 }
519 return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1);
520 }
521 return 0x100;
522}
523
524static void gic_drop_prio(GICState *s, int cpu, int group)
525{
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542 if (gic_is_vcpu(cpu)) {
543 int rcpu = gic_get_vcpu_real_id(cpu);
544
545 if (s->h_apr[rcpu]) {
546
547 s->h_apr[rcpu] &= s->h_apr[rcpu] - 1;
548 }
549 } else {
550 int i;
551
552 for (i = 0; i < GIC_NR_APRS; i++) {
553 uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu];
554 if (!*papr) {
555 continue;
556 }
557
558 *papr &= *papr - 1;
559 break;
560 }
561 }
562
563 s->running_priority[cpu] = gic_get_prio_from_apr_bits(s, cpu);
564}
565
566static inline uint32_t gic_clear_pending_sgi(GICState *s, int irq, int cpu)
567{
568 int src;
569 uint32_t ret;
570
571 if (!gic_is_vcpu(cpu)) {
572
573
574
575
576 assert(s->sgi_pending[irq][cpu] != 0);
577 src = ctz32(s->sgi_pending[irq][cpu]);
578 s->sgi_pending[irq][cpu] &= ~(1 << src);
579 if (s->sgi_pending[irq][cpu] == 0) {
580 gic_clear_pending(s, irq, cpu);
581 }
582 ret = irq | ((src & 0x7) << 10);
583 } else {
584 uint32_t *lr_entry = gic_get_lr_entry(s, irq, cpu);
585 src = GICH_LR_CPUID(*lr_entry);
586
587 gic_clear_pending(s, irq, cpu);
588 ret = irq | (src << 10);
589 }
590
591 return ret;
592}
593
594uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
595{
596 int ret, irq;
597
598
599
600
601
602 irq = gic_get_current_pending_irq(s, cpu, attrs);
603 trace_gic_acknowledge_irq(gic_is_vcpu(cpu) ? "vcpu" : "cpu",
604 gic_get_vcpu_real_id(cpu), irq);
605
606 if (irq >= GIC_MAXIRQ) {
607 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq);
608 return irq;
609 }
610
611 if (gic_get_priority(s, irq, cpu) >= s->running_priority[cpu]) {
612 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq);
613 return 1023;
614 }
615
616 gic_activate_irq(s, cpu, irq);
617
618 if (s->revision == REV_11MPCORE) {
619
620
621
622 gic_clear_pending(s, irq, cpu);
623 ret = irq;
624 } else {
625 if (irq < GIC_NR_SGIS) {
626 ret = gic_clear_pending_sgi(s, irq, cpu);
627 } else {
628 gic_clear_pending(s, irq, cpu);
629 ret = irq;
630 }
631 }
632
633 if (gic_is_vcpu(cpu)) {
634 gic_update_virt(s);
635 } else {
636 gic_update(s);
637 }
638 DPRINTF("ACK %d\n", irq);
639 return ret;
640}
641
642void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val,
643 MemTxAttrs attrs)
644{
645 if (s->security_extn && !attrs.secure) {
646 if (!GIC_DIST_TEST_GROUP(irq, (1 << cpu))) {
647 return;
648 }
649 val = 0x80 | (val >> 1);
650 }
651
652 if (irq < GIC_INTERNAL) {
653 s->priority1[irq][cpu] = val;
654 } else {
655 s->priority2[(irq) - GIC_INTERNAL] = val;
656 }
657}
658
659static uint32_t gic_dist_get_priority(GICState *s, int cpu, int irq,
660 MemTxAttrs attrs)
661{
662 uint32_t prio = GIC_DIST_GET_PRIORITY(irq, cpu);
663
664 if (s->security_extn && !attrs.secure) {
665 if (!GIC_DIST_TEST_GROUP(irq, (1 << cpu))) {
666 return 0;
667 }
668 prio = (prio << 1) & 0xff;
669 }
670 return prio;
671}
672
673static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask,
674 MemTxAttrs attrs)
675{
676 if (gic_cpu_ns_access(s, cpu, attrs)) {
677 if (s->priority_mask[cpu] & 0x80) {
678
679 pmask = 0x80 | (pmask >> 1);
680 } else {
681
682 return;
683 }
684 }
685 s->priority_mask[cpu] = pmask;
686}
687
688static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs)
689{
690 uint32_t pmask = s->priority_mask[cpu];
691
692 if (gic_cpu_ns_access(s, cpu, attrs)) {
693 if (pmask & 0x80) {
694
695 pmask = (pmask << 1) & 0xff;
696 } else {
697
698 pmask = 0;
699 }
700 }
701 return pmask;
702}
703
704static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs)
705{
706 uint32_t ret = s->cpu_ctlr[cpu];
707
708 if (gic_cpu_ns_access(s, cpu, attrs)) {
709
710
711
712
713
714 ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1;
715 }
716 return ret;
717}
718
719static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value,
720 MemTxAttrs attrs)
721{
722 uint32_t mask;
723
724 if (gic_cpu_ns_access(s, cpu, attrs)) {
725
726
727
728 mask = GICC_CTLR_EN_GRP1;
729 if (s->revision == 2) {
730 mask |= GICC_CTLR_EOIMODE_NS;
731 }
732 s->cpu_ctlr[cpu] &= ~mask;
733 s->cpu_ctlr[cpu] |= (value << 1) & mask;
734 } else {
735 if (s->revision == 2) {
736 mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK;
737 } else {
738 mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK;
739 }
740 s->cpu_ctlr[cpu] = value & mask;
741 }
742 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, "
743 "Group1 Interrupts %sabled\n", cpu,
744 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis",
745 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis");
746}
747
748static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs)
749{
750 if ((s->revision != REV_11MPCORE) && (s->running_priority[cpu] > 0xff)) {
751
752 return 0xff;
753 }
754
755 if (gic_cpu_ns_access(s, cpu, attrs)) {
756 if (s->running_priority[cpu] & 0x80) {
757
758
759
760 return s->running_priority[cpu] << 1;
761 } else {
762
763 return 0;
764 }
765 } else {
766 return s->running_priority[cpu];
767 }
768}
769
770
771
772
773static bool gic_eoi_split(GICState *s, int cpu, MemTxAttrs attrs)
774{
775 if (s->revision != 2) {
776
777 return false;
778 }
779 if (gic_cpu_ns_access(s, cpu, attrs)) {
780 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE_NS;
781 }
782 return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE;
783}
784
785static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
786{
787 int group;
788
789 if (irq >= GIC_MAXIRQ || (!gic_is_vcpu(cpu) && irq >= s->num_irq)) {
790
791
792
793
794
795
796
797
798
799 return;
800 }
801
802 if (!gic_eoi_split(s, cpu, attrs)) {
803
804 qemu_log_mask(LOG_GUEST_ERROR,
805 "gic_deactivate_irq: GICC_DIR write when EOIMode clear");
806 return;
807 }
808
809 if (gic_is_vcpu(cpu) && !gic_virq_is_valid(s, irq, cpu)) {
810
811
812
813 int rcpu = gic_get_vcpu_real_id(cpu);
814 s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT;
815
816
817
818
819 gic_update_virt(s);
820 return;
821 }
822
823 group = gic_has_groups(s) && gic_test_group(s, irq, cpu);
824
825 if (gic_cpu_ns_access(s, cpu, attrs) && !group) {
826 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq);
827 return;
828 }
829
830 gic_clear_active(s, irq, cpu);
831}
832
833static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
834{
835 int cm = 1 << cpu;
836 int group;
837
838 DPRINTF("EOI %d\n", irq);
839 if (gic_is_vcpu(cpu)) {
840
841
842
843 bool prio_drop = s->running_priority[cpu] < 0x100;
844
845 if (irq >= GIC_MAXIRQ) {
846
847 return;
848 }
849
850 gic_drop_prio(s, cpu, 0);
851
852 if (!gic_eoi_split(s, cpu, attrs)) {
853 bool valid = gic_virq_is_valid(s, irq, cpu);
854 if (prio_drop && !valid) {
855
856
857
858
859
860
861
862 int rcpu = gic_get_vcpu_real_id(cpu);
863 s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT;
864 } else if (valid) {
865 gic_clear_active(s, irq, cpu);
866 }
867 }
868
869 gic_update_virt(s);
870 return;
871 }
872
873 if (irq >= s->num_irq) {
874
875
876
877
878
879
880
881
882 return;
883 }
884 if (s->running_priority[cpu] == 0x100) {
885 return;
886 }
887
888 if (s->revision == REV_11MPCORE) {
889
890
891 if (!GIC_DIST_TEST_EDGE_TRIGGER(irq) && GIC_DIST_TEST_ENABLED(irq, cm)
892 && GIC_DIST_TEST_LEVEL(irq, cm)
893 && (GIC_DIST_TARGET(irq) & cm) != 0) {
894 DPRINTF("Set %d pending mask %x\n", irq, cm);
895 GIC_DIST_SET_PENDING(irq, cm);
896 }
897 }
898
899 group = gic_has_groups(s) && gic_test_group(s, irq, cpu);
900
901 if (gic_cpu_ns_access(s, cpu, attrs) && !group) {
902 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq);
903 return;
904 }
905
906
907
908
909
910
911 gic_drop_prio(s, cpu, group);
912
913
914 if (!gic_eoi_split(s, cpu, attrs)) {
915 gic_clear_active(s, irq, cpu);
916 }
917 gic_update(s);
918}
919
920static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
921{
922 GICState *s = (GICState *)opaque;
923 uint32_t res;
924 int irq;
925 int i;
926 int cpu;
927 int cm;
928 int mask;
929
930 cpu = gic_get_current_cpu(s);
931 cm = 1 << cpu;
932 if (offset < 0x100) {
933 if (offset == 0) {
934 if (s->security_extn && !attrs.secure) {
935
936
937
938 return extract32(s->ctlr, 1, 1);
939 } else {
940 return s->ctlr;
941 }
942 }
943 if (offset == 4)
944
945 return ((s->num_irq / 32) - 1)
946 | ((s->num_cpu - 1) << 5)
947 | (s->security_extn << 10);
948 if (offset < 0x08)
949 return 0;
950 if (offset >= 0x80) {
951
952
953
954
955 res = 0;
956 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) {
957
958 irq = (offset - 0x080) * 8;
959 if (irq >= s->num_irq) {
960 goto bad_reg;
961 }
962 for (i = 0; i < 8; i++) {
963 if (GIC_DIST_TEST_GROUP(irq + i, cm)) {
964 res |= (1 << i);
965 }
966 }
967 }
968 return res;
969 }
970 goto bad_reg;
971 } else if (offset < 0x200) {
972
973 if (offset < 0x180)
974 irq = (offset - 0x100) * 8;
975 else
976 irq = (offset - 0x180) * 8;
977 if (irq >= s->num_irq)
978 goto bad_reg;
979 res = 0;
980 for (i = 0; i < 8; i++) {
981 if (s->security_extn && !attrs.secure &&
982 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
983 continue;
984 }
985
986 if (GIC_DIST_TEST_ENABLED(irq + i, cm)) {
987 res |= (1 << i);
988 }
989 }
990 } else if (offset < 0x300) {
991
992 if (offset < 0x280)
993 irq = (offset - 0x200) * 8;
994 else
995 irq = (offset - 0x280) * 8;
996 if (irq >= s->num_irq)
997 goto bad_reg;
998 res = 0;
999 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK;
1000 for (i = 0; i < 8; i++) {
1001 if (s->security_extn && !attrs.secure &&
1002 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
1003 continue;
1004 }
1005
1006 if (gic_test_pending(s, irq + i, mask)) {
1007 res |= (1 << i);
1008 }
1009 }
1010 } else if (offset < 0x400) {
1011
1012 if (offset < 0x380) {
1013 irq = (offset - 0x300) * 8;
1014 } else if (s->revision == 2) {
1015 irq = (offset - 0x380) * 8;
1016 } else {
1017 goto bad_reg;
1018 }
1019
1020 if (irq >= s->num_irq)
1021 goto bad_reg;
1022 res = 0;
1023 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK;
1024 for (i = 0; i < 8; i++) {
1025 if (s->security_extn && !attrs.secure &&
1026 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
1027 continue;
1028 }
1029
1030 if (GIC_DIST_TEST_ACTIVE(irq + i, mask)) {
1031 res |= (1 << i);
1032 }
1033 }
1034 } else if (offset < 0x800) {
1035
1036 irq = (offset - 0x400);
1037 if (irq >= s->num_irq)
1038 goto bad_reg;
1039 res = gic_dist_get_priority(s, cpu, irq, attrs);
1040 } else if (offset < 0xc00) {
1041
1042 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) {
1043
1044 res = 0;
1045 } else {
1046 irq = (offset - 0x800);
1047 if (irq >= s->num_irq) {
1048 goto bad_reg;
1049 }
1050 if (irq < 29 && s->revision == REV_11MPCORE) {
1051 res = 0;
1052 } else if (irq < GIC_INTERNAL) {
1053 res = cm;
1054 } else {
1055 res = GIC_DIST_TARGET(irq);
1056 }
1057 }
1058 } else if (offset < 0xf00) {
1059
1060 irq = (offset - 0xc00) * 4;
1061 if (irq >= s->num_irq)
1062 goto bad_reg;
1063 res = 0;
1064 for (i = 0; i < 4; i++) {
1065 if (s->security_extn && !attrs.secure &&
1066 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
1067 continue;
1068 }
1069
1070 if (GIC_DIST_TEST_MODEL(irq + i)) {
1071 res |= (1 << (i * 2));
1072 }
1073 if (GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) {
1074 res |= (2 << (i * 2));
1075 }
1076 }
1077 } else if (offset < 0xf10) {
1078 goto bad_reg;
1079 } else if (offset < 0xf30) {
1080 if (s->revision == REV_11MPCORE) {
1081 goto bad_reg;
1082 }
1083
1084 if (offset < 0xf20) {
1085
1086 irq = (offset - 0xf10);
1087 } else {
1088 irq = (offset - 0xf20);
1089
1090 }
1091
1092 if (s->security_extn && !attrs.secure &&
1093 !GIC_DIST_TEST_GROUP(irq, 1 << cpu)) {
1094 res = 0;
1095 } else {
1096 res = s->sgi_pending[irq][cpu];
1097 }
1098 } else if (offset < 0xfd0) {
1099 goto bad_reg;
1100 } else if (offset < 0x1000) {
1101 if (offset & 3) {
1102 res = 0;
1103 } else {
1104 switch (s->revision) {
1105 case REV_11MPCORE:
1106 res = gic_id_11mpcore[(offset - 0xfd0) >> 2];
1107 break;
1108 case 1:
1109 res = gic_id_gicv1[(offset - 0xfd0) >> 2];
1110 break;
1111 case 2:
1112 res = gic_id_gicv2[(offset - 0xfd0) >> 2];
1113 break;
1114 default:
1115 res = 0;
1116 }
1117 }
1118 } else {
1119 g_assert_not_reached();
1120 }
1121 return res;
1122bad_reg:
1123 qemu_log_mask(LOG_GUEST_ERROR,
1124 "gic_dist_readb: Bad offset %x\n", (int)offset);
1125 return 0;
1126}
1127
1128static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data,
1129 unsigned size, MemTxAttrs attrs)
1130{
1131 switch (size) {
1132 case 1:
1133 *data = gic_dist_readb(opaque, offset, attrs);
1134 break;
1135 case 2:
1136 *data = gic_dist_readb(opaque, offset, attrs);
1137 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8;
1138 break;
1139 case 4:
1140 *data = gic_dist_readb(opaque, offset, attrs);
1141 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8;
1142 *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16;
1143 *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24;
1144 break;
1145 default:
1146 return MEMTX_ERROR;
1147 }
1148
1149 trace_gic_dist_read(offset, size, *data);
1150 return MEMTX_OK;
1151}
1152
1153static void gic_dist_writeb(void *opaque, hwaddr offset,
1154 uint32_t value, MemTxAttrs attrs)
1155{
1156 GICState *s = (GICState *)opaque;
1157 int irq;
1158 int i;
1159 int cpu;
1160
1161 cpu = gic_get_current_cpu(s);
1162 if (offset < 0x100) {
1163 if (offset == 0) {
1164 if (s->security_extn && !attrs.secure) {
1165
1166 s->ctlr = deposit32(s->ctlr, 1, 1, value);
1167 } else if (gic_has_groups(s)) {
1168 s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1);
1169 } else {
1170 s->ctlr = value & GICD_CTLR_EN_GRP0;
1171 }
1172 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n",
1173 s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis",
1174 s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis");
1175 } else if (offset < 4) {
1176
1177 } else if (offset >= 0x80) {
1178
1179
1180
1181 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) {
1182
1183 irq = (offset - 0x80) * 8;
1184 if (irq >= s->num_irq) {
1185 goto bad_reg;
1186 }
1187 for (i = 0; i < 8; i++) {
1188
1189 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
1190 if (value & (1 << i)) {
1191
1192 GIC_DIST_SET_GROUP(irq + i, cm);
1193 } else {
1194
1195 GIC_DIST_CLEAR_GROUP(irq + i, cm);
1196 }
1197 }
1198 }
1199 } else {
1200 goto bad_reg;
1201 }
1202 } else if (offset < 0x180) {
1203
1204 irq = (offset - 0x100) * 8;
1205 if (irq >= s->num_irq)
1206 goto bad_reg;
1207 if (irq < GIC_NR_SGIS) {
1208 value = 0xff;
1209 }
1210
1211 for (i = 0; i < 8; i++) {
1212 if (value & (1 << i)) {
1213 int mask =
1214 (irq < GIC_INTERNAL) ? (1 << cpu)
1215 : GIC_DIST_TARGET(irq + i);
1216 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
1217
1218 if (s->security_extn && !attrs.secure &&
1219 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
1220 continue;
1221 }
1222
1223 if (!GIC_DIST_TEST_ENABLED(irq + i, cm)) {
1224 DPRINTF("Enabled IRQ %d\n", irq + i);
1225 trace_gic_enable_irq(irq + i);
1226 }
1227 GIC_DIST_SET_ENABLED(irq + i, cm);
1228
1229
1230 if (GIC_DIST_TEST_LEVEL(irq + i, mask)
1231 && !GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) {
1232 DPRINTF("Set %d pending mask %x\n", irq + i, mask);
1233 GIC_DIST_SET_PENDING(irq + i, mask);
1234 }
1235 }
1236 }
1237 } else if (offset < 0x200) {
1238
1239 irq = (offset - 0x180) * 8;
1240 if (irq >= s->num_irq)
1241 goto bad_reg;
1242 if (irq < GIC_NR_SGIS) {
1243 value = 0;
1244 }
1245
1246 for (i = 0; i < 8; i++) {
1247 if (value & (1 << i)) {
1248 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
1249
1250 if (s->security_extn && !attrs.secure &&
1251 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
1252 continue;
1253 }
1254
1255 if (GIC_DIST_TEST_ENABLED(irq + i, cm)) {
1256 DPRINTF("Disabled IRQ %d\n", irq + i);
1257 trace_gic_disable_irq(irq + i);
1258 }
1259 GIC_DIST_CLEAR_ENABLED(irq + i, cm);
1260 }
1261 }
1262 } else if (offset < 0x280) {
1263
1264 irq = (offset - 0x200) * 8;
1265 if (irq >= s->num_irq)
1266 goto bad_reg;
1267 if (irq < GIC_NR_SGIS) {
1268 value = 0;
1269 }
1270
1271 for (i = 0; i < 8; i++) {
1272 if (value & (1 << i)) {
1273 if (s->security_extn && !attrs.secure &&
1274 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
1275 continue;
1276 }
1277
1278 GIC_DIST_SET_PENDING(irq + i, GIC_DIST_TARGET(irq + i));
1279 }
1280 }
1281 } else if (offset < 0x300) {
1282
1283 irq = (offset - 0x280) * 8;
1284 if (irq >= s->num_irq)
1285 goto bad_reg;
1286 if (irq < GIC_NR_SGIS) {
1287 value = 0;
1288 }
1289
1290 for (i = 0; i < 8; i++) {
1291 if (s->security_extn && !attrs.secure &&
1292 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
1293 continue;
1294 }
1295
1296
1297
1298
1299 if (value & (1 << i)) {
1300 GIC_DIST_CLEAR_PENDING(irq + i, ALL_CPU_MASK);
1301 }
1302 }
1303 } else if (offset < 0x380) {
1304
1305 if (s->revision != 2) {
1306 goto bad_reg;
1307 }
1308
1309 irq = (offset - 0x300) * 8;
1310 if (irq >= s->num_irq) {
1311 goto bad_reg;
1312 }
1313
1314
1315 int cm = irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK;
1316
1317 for (i = 0; i < 8; i++) {
1318 if (s->security_extn && !attrs.secure &&
1319 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
1320 continue;
1321 }
1322
1323 if (value & (1 << i)) {
1324 GIC_DIST_SET_ACTIVE(irq + i, cm);
1325 }
1326 }
1327 } else if (offset < 0x400) {
1328
1329 if (s->revision != 2) {
1330 goto bad_reg;
1331 }
1332
1333 irq = (offset - 0x380) * 8;
1334 if (irq >= s->num_irq) {
1335 goto bad_reg;
1336 }
1337
1338
1339 int cm = irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK;
1340
1341 for (i = 0; i < 8; i++) {
1342 if (s->security_extn && !attrs.secure &&
1343 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
1344 continue;
1345 }
1346
1347 if (value & (1 << i)) {
1348 GIC_DIST_CLEAR_ACTIVE(irq + i, cm);
1349 }
1350 }
1351 } else if (offset < 0x800) {
1352
1353 irq = (offset - 0x400);
1354 if (irq >= s->num_irq)
1355 goto bad_reg;
1356 gic_dist_set_priority(s, cpu, irq, value, attrs);
1357 } else if (offset < 0xc00) {
1358
1359
1360
1361 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) {
1362 irq = (offset - 0x800);
1363 if (irq >= s->num_irq) {
1364 goto bad_reg;
1365 }
1366 if (irq < 29 && s->revision == REV_11MPCORE) {
1367 value = 0;
1368 } else if (irq < GIC_INTERNAL) {
1369 value = ALL_CPU_MASK;
1370 }
1371 s->irq_target[irq] = value & ALL_CPU_MASK;
1372 }
1373 } else if (offset < 0xf00) {
1374
1375 irq = (offset - 0xc00) * 4;
1376 if (irq >= s->num_irq)
1377 goto bad_reg;
1378 if (irq < GIC_NR_SGIS)
1379 value |= 0xaa;
1380 for (i = 0; i < 4; i++) {
1381 if (s->security_extn && !attrs.secure &&
1382 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
1383 continue;
1384 }
1385
1386 if (s->revision == REV_11MPCORE) {
1387 if (value & (1 << (i * 2))) {
1388 GIC_DIST_SET_MODEL(irq + i);
1389 } else {
1390 GIC_DIST_CLEAR_MODEL(irq + i);
1391 }
1392 }
1393 if (value & (2 << (i * 2))) {
1394 GIC_DIST_SET_EDGE_TRIGGER(irq + i);
1395 } else {
1396 GIC_DIST_CLEAR_EDGE_TRIGGER(irq + i);
1397 }
1398 }
1399 } else if (offset < 0xf10) {
1400
1401 goto bad_reg;
1402 } else if (offset < 0xf20) {
1403
1404 if (s->revision == REV_11MPCORE) {
1405 goto bad_reg;
1406 }
1407 irq = (offset - 0xf10);
1408
1409 if (!s->security_extn || attrs.secure ||
1410 GIC_DIST_TEST_GROUP(irq, 1 << cpu)) {
1411 s->sgi_pending[irq][cpu] &= ~value;
1412 if (s->sgi_pending[irq][cpu] == 0) {
1413 GIC_DIST_CLEAR_PENDING(irq, 1 << cpu);
1414 }
1415 }
1416 } else if (offset < 0xf30) {
1417
1418 if (s->revision == REV_11MPCORE) {
1419 goto bad_reg;
1420 }
1421 irq = (offset - 0xf20);
1422
1423 if (!s->security_extn || attrs.secure ||
1424 GIC_DIST_TEST_GROUP(irq, 1 << cpu)) {
1425 GIC_DIST_SET_PENDING(irq, 1 << cpu);
1426 s->sgi_pending[irq][cpu] |= value;
1427 }
1428 } else {
1429 goto bad_reg;
1430 }
1431 gic_update(s);
1432 return;
1433bad_reg:
1434 qemu_log_mask(LOG_GUEST_ERROR,
1435 "gic_dist_writeb: Bad offset %x\n", (int)offset);
1436}
1437
1438static void gic_dist_writew(void *opaque, hwaddr offset,
1439 uint32_t value, MemTxAttrs attrs)
1440{
1441 gic_dist_writeb(opaque, offset, value & 0xff, attrs);
1442 gic_dist_writeb(opaque, offset + 1, value >> 8, attrs);
1443}
1444
1445static void gic_dist_writel(void *opaque, hwaddr offset,
1446 uint32_t value, MemTxAttrs attrs)
1447{
1448 GICState *s = (GICState *)opaque;
1449 if (offset == 0xf00) {
1450 int cpu;
1451 int irq;
1452 int mask;
1453 int target_cpu;
1454
1455 cpu = gic_get_current_cpu(s);
1456 irq = value & 0x3ff;
1457 switch ((value >> 24) & 3) {
1458 case 0:
1459 mask = (value >> 16) & ALL_CPU_MASK;
1460 break;
1461 case 1:
1462 mask = ALL_CPU_MASK ^ (1 << cpu);
1463 break;
1464 case 2:
1465 mask = 1 << cpu;
1466 break;
1467 default:
1468 DPRINTF("Bad Soft Int target filter\n");
1469 mask = ALL_CPU_MASK;
1470 break;
1471 }
1472 GIC_DIST_SET_PENDING(irq, mask);
1473 target_cpu = ctz32(mask);
1474 while (target_cpu < GIC_NCPU) {
1475 s->sgi_pending[irq][target_cpu] |= (1 << cpu);
1476 mask &= ~(1 << target_cpu);
1477 target_cpu = ctz32(mask);
1478 }
1479 gic_update(s);
1480 return;
1481 }
1482 gic_dist_writew(opaque, offset, value & 0xffff, attrs);
1483 gic_dist_writew(opaque, offset + 2, value >> 16, attrs);
1484}
1485
1486static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data,
1487 unsigned size, MemTxAttrs attrs)
1488{
1489 trace_gic_dist_write(offset, size, data);
1490
1491 switch (size) {
1492 case 1:
1493 gic_dist_writeb(opaque, offset, data, attrs);
1494 return MEMTX_OK;
1495 case 2:
1496 gic_dist_writew(opaque, offset, data, attrs);
1497 return MEMTX_OK;
1498 case 4:
1499 gic_dist_writel(opaque, offset, data, attrs);
1500 return MEMTX_OK;
1501 default:
1502 return MEMTX_ERROR;
1503 }
1504}
1505
1506static inline uint32_t gic_apr_ns_view(GICState *s, int cpu, int regno)
1507{
1508
1509
1510
1511 switch (GIC_MIN_BPR) {
1512 case 0:
1513 if (regno < 2) {
1514 return s->nsapr[regno + 2][cpu];
1515 }
1516 break;
1517 case 1:
1518 if (regno == 0) {
1519 return s->nsapr[regno + 1][cpu];
1520 }
1521 break;
1522 case 2:
1523 if (regno == 0) {
1524 return extract32(s->nsapr[0][cpu], 16, 16);
1525 }
1526 break;
1527 case 3:
1528 if (regno == 0) {
1529 return extract32(s->nsapr[0][cpu], 8, 8);
1530 }
1531 break;
1532 default:
1533 g_assert_not_reached();
1534 }
1535 return 0;
1536}
1537
1538static inline void gic_apr_write_ns_view(GICState *s, int cpu, int regno,
1539 uint32_t value)
1540{
1541
1542 switch (GIC_MIN_BPR) {
1543 case 0:
1544 if (regno < 2) {
1545 s->nsapr[regno + 2][cpu] = value;
1546 }
1547 break;
1548 case 1:
1549 if (regno == 0) {
1550 s->nsapr[regno + 1][cpu] = value;
1551 }
1552 break;
1553 case 2:
1554 if (regno == 0) {
1555 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 16, 16, value);
1556 }
1557 break;
1558 case 3:
1559 if (regno == 0) {
1560 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 8, 8, value);
1561 }
1562 break;
1563 default:
1564 g_assert_not_reached();
1565 }
1566}
1567
1568static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset,
1569 uint64_t *data, MemTxAttrs attrs)
1570{
1571 switch (offset) {
1572 case 0x00:
1573 *data = gic_get_cpu_control(s, cpu, attrs);
1574 break;
1575 case 0x04:
1576 *data = gic_get_priority_mask(s, cpu, attrs);
1577 break;
1578 case 0x08:
1579 if (gic_cpu_ns_access(s, cpu, attrs)) {
1580 if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) {
1581
1582 *data = MIN(s->bpr[cpu] + 1, 7);
1583 } else {
1584
1585 *data = s->abpr[cpu];
1586 }
1587 } else {
1588 *data = s->bpr[cpu];
1589 }
1590 break;
1591 case 0x0c:
1592 *data = gic_acknowledge_irq(s, cpu, attrs);
1593 break;
1594 case 0x14:
1595 *data = gic_get_running_priority(s, cpu, attrs);
1596 break;
1597 case 0x18:
1598 *data = gic_get_current_pending_irq(s, cpu, attrs);
1599 break;
1600 case 0x1c:
1601
1602
1603
1604
1605
1606 if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) {
1607 *data = 0;
1608 } else {
1609 *data = s->abpr[cpu];
1610 }
1611 break;
1612 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1613 {
1614 int regno = (offset - 0xd0) / 4;
1615 int nr_aprs = gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS;
1616
1617 if (regno >= nr_aprs || s->revision != 2) {
1618 *data = 0;
1619 } else if (gic_is_vcpu(cpu)) {
1620 *data = s->h_apr[gic_get_vcpu_real_id(cpu)];
1621 } else if (gic_cpu_ns_access(s, cpu, attrs)) {
1622
1623 *data = gic_apr_ns_view(s, regno, cpu);
1624 } else {
1625 *data = s->apr[regno][cpu];
1626 }
1627 break;
1628 }
1629 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1630 {
1631 int regno = (offset - 0xe0) / 4;
1632
1633 if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) ||
1634 gic_cpu_ns_access(s, cpu, attrs) || gic_is_vcpu(cpu)) {
1635 *data = 0;
1636 } else {
1637 *data = s->nsapr[regno][cpu];
1638 }
1639 break;
1640 }
1641 default:
1642 qemu_log_mask(LOG_GUEST_ERROR,
1643 "gic_cpu_read: Bad offset %x\n", (int)offset);
1644 *data = 0;
1645 break;
1646 }
1647
1648 trace_gic_cpu_read(gic_is_vcpu(cpu) ? "vcpu" : "cpu",
1649 gic_get_vcpu_real_id(cpu), offset, *data);
1650 return MEMTX_OK;
1651}
1652
1653static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset,
1654 uint32_t value, MemTxAttrs attrs)
1655{
1656 trace_gic_cpu_write(gic_is_vcpu(cpu) ? "vcpu" : "cpu",
1657 gic_get_vcpu_real_id(cpu), offset, value);
1658
1659 switch (offset) {
1660 case 0x00:
1661 gic_set_cpu_control(s, cpu, value, attrs);
1662 break;
1663 case 0x04:
1664 gic_set_priority_mask(s, cpu, value, attrs);
1665 break;
1666 case 0x08:
1667 if (gic_cpu_ns_access(s, cpu, attrs)) {
1668 if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) {
1669
1670 return MEMTX_OK;
1671 } else {
1672 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR);
1673 }
1674 } else {
1675 int min_bpr = gic_is_vcpu(cpu) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR;
1676 s->bpr[cpu] = MAX(value & 0x7, min_bpr);
1677 }
1678 break;
1679 case 0x10:
1680 gic_complete_irq(s, cpu, value & 0x3ff, attrs);
1681 return MEMTX_OK;
1682 case 0x1c:
1683 if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) {
1684
1685 return MEMTX_OK;
1686 } else {
1687 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR);
1688 }
1689 break;
1690 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1691 {
1692 int regno = (offset - 0xd0) / 4;
1693 int nr_aprs = gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS;
1694
1695 if (regno >= nr_aprs || s->revision != 2) {
1696 return MEMTX_OK;
1697 }
1698 if (gic_is_vcpu(cpu)) {
1699 s->h_apr[gic_get_vcpu_real_id(cpu)] = value;
1700 } else if (gic_cpu_ns_access(s, cpu, attrs)) {
1701
1702 gic_apr_write_ns_view(s, regno, cpu, value);
1703 } else {
1704 s->apr[regno][cpu] = value;
1705 }
1706 break;
1707 }
1708 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1709 {
1710 int regno = (offset - 0xe0) / 4;
1711
1712 if (regno >= GIC_NR_APRS || s->revision != 2) {
1713 return MEMTX_OK;
1714 }
1715 if (gic_is_vcpu(cpu)) {
1716 return MEMTX_OK;
1717 }
1718 if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) {
1719 return MEMTX_OK;
1720 }
1721 s->nsapr[regno][cpu] = value;
1722 break;
1723 }
1724 case 0x1000:
1725
1726 gic_deactivate_irq(s, cpu, value & 0x3ff, attrs);
1727 break;
1728 default:
1729 qemu_log_mask(LOG_GUEST_ERROR,
1730 "gic_cpu_write: Bad offset %x\n", (int)offset);
1731 return MEMTX_OK;
1732 }
1733
1734 if (gic_is_vcpu(cpu)) {
1735 gic_update_virt(s);
1736 } else {
1737 gic_update(s);
1738 }
1739
1740 return MEMTX_OK;
1741}
1742
1743
1744static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data,
1745 unsigned size, MemTxAttrs attrs)
1746{
1747 GICState *s = (GICState *)opaque;
1748 return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs);
1749}
1750
1751static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr,
1752 uint64_t value, unsigned size,
1753 MemTxAttrs attrs)
1754{
1755 GICState *s = (GICState *)opaque;
1756 return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs);
1757}
1758
1759
1760
1761
1762static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data,
1763 unsigned size, MemTxAttrs attrs)
1764{
1765 GICState **backref = (GICState **)opaque;
1766 GICState *s = *backref;
1767 int id = (backref - s->backref);
1768 return gic_cpu_read(s, id, addr, data, attrs);
1769}
1770
1771static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr,
1772 uint64_t value, unsigned size,
1773 MemTxAttrs attrs)
1774{
1775 GICState **backref = (GICState **)opaque;
1776 GICState *s = *backref;
1777 int id = (backref - s->backref);
1778 return gic_cpu_write(s, id, addr, value, attrs);
1779}
1780
1781static MemTxResult gic_thisvcpu_read(void *opaque, hwaddr addr, uint64_t *data,
1782 unsigned size, MemTxAttrs attrs)
1783{
1784 GICState *s = (GICState *)opaque;
1785
1786 return gic_cpu_read(s, gic_get_current_vcpu(s), addr, data, attrs);
1787}
1788
1789static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr,
1790 uint64_t value, unsigned size,
1791 MemTxAttrs attrs)
1792{
1793 GICState *s = (GICState *)opaque;
1794
1795 return gic_cpu_write(s, gic_get_current_vcpu(s), addr, value, attrs);
1796}
1797
1798static uint32_t gic_compute_eisr(GICState *s, int cpu, int lr_start)
1799{
1800 int lr_idx;
1801 uint32_t ret = 0;
1802
1803 for (lr_idx = lr_start; lr_idx < s->num_lrs; lr_idx++) {
1804 uint32_t *entry = &s->h_lr[lr_idx][cpu];
1805 ret = deposit32(ret, lr_idx - lr_start, 1,
1806 gic_lr_entry_is_eoi(*entry));
1807 }
1808
1809 return ret;
1810}
1811
1812static uint32_t gic_compute_elrsr(GICState *s, int cpu, int lr_start)
1813{
1814 int lr_idx;
1815 uint32_t ret = 0;
1816
1817 for (lr_idx = lr_start; lr_idx < s->num_lrs; lr_idx++) {
1818 uint32_t *entry = &s->h_lr[lr_idx][cpu];
1819 ret = deposit32(ret, lr_idx - lr_start, 1,
1820 gic_lr_entry_is_free(*entry));
1821 }
1822
1823 return ret;
1824}
1825
1826static void gic_vmcr_write(GICState *s, uint32_t value, MemTxAttrs attrs)
1827{
1828 int vcpu = gic_get_current_vcpu(s);
1829 uint32_t ctlr;
1830 uint32_t abpr;
1831 uint32_t bpr;
1832 uint32_t prio_mask;
1833
1834 ctlr = FIELD_EX32(value, GICH_VMCR, VMCCtlr);
1835 abpr = FIELD_EX32(value, GICH_VMCR, VMABP);
1836 bpr = FIELD_EX32(value, GICH_VMCR, VMBP);
1837 prio_mask = FIELD_EX32(value, GICH_VMCR, VMPriMask) << 3;
1838
1839 gic_set_cpu_control(s, vcpu, ctlr, attrs);
1840 s->abpr[vcpu] = MAX(abpr, GIC_VIRT_MIN_ABPR);
1841 s->bpr[vcpu] = MAX(bpr, GIC_VIRT_MIN_BPR);
1842 gic_set_priority_mask(s, vcpu, prio_mask, attrs);
1843}
1844
1845static MemTxResult gic_hyp_read(void *opaque, int cpu, hwaddr addr,
1846 uint64_t *data, MemTxAttrs attrs)
1847{
1848 GICState *s = ARM_GIC(opaque);
1849 int vcpu = cpu + GIC_NCPU;
1850
1851 switch (addr) {
1852 case A_GICH_HCR:
1853 *data = s->h_hcr[cpu];
1854 break;
1855
1856 case A_GICH_VTR:
1857 *data = FIELD_DP32(0, GICH_VTR, ListRegs, s->num_lrs - 1);
1858 *data = FIELD_DP32(*data, GICH_VTR, PREbits,
1859 GIC_VIRT_MAX_GROUP_PRIO_BITS - 1);
1860 *data = FIELD_DP32(*data, GICH_VTR, PRIbits,
1861 (7 - GIC_VIRT_MIN_BPR) - 1);
1862 break;
1863
1864 case A_GICH_VMCR:
1865 *data = FIELD_DP32(0, GICH_VMCR, VMCCtlr,
1866 extract32(s->cpu_ctlr[vcpu], 0, 10));
1867 *data = FIELD_DP32(*data, GICH_VMCR, VMABP, s->abpr[vcpu]);
1868 *data = FIELD_DP32(*data, GICH_VMCR, VMBP, s->bpr[vcpu]);
1869 *data = FIELD_DP32(*data, GICH_VMCR, VMPriMask,
1870 extract32(s->priority_mask[vcpu], 3, 5));
1871 break;
1872
1873 case A_GICH_MISR:
1874 *data = s->h_misr[cpu];
1875 break;
1876
1877 case A_GICH_EISR0:
1878 case A_GICH_EISR1:
1879 *data = gic_compute_eisr(s, cpu, (addr - A_GICH_EISR0) * 8);
1880 break;
1881
1882 case A_GICH_ELRSR0:
1883 case A_GICH_ELRSR1:
1884 *data = gic_compute_elrsr(s, cpu, (addr - A_GICH_ELRSR0) * 8);
1885 break;
1886
1887 case A_GICH_APR:
1888 *data = s->h_apr[cpu];
1889 break;
1890
1891 case A_GICH_LR0 ... A_GICH_LR63:
1892 {
1893 int lr_idx = (addr - A_GICH_LR0) / 4;
1894
1895 if (lr_idx > s->num_lrs) {
1896 *data = 0;
1897 } else {
1898 *data = s->h_lr[lr_idx][cpu];
1899 }
1900 break;
1901 }
1902
1903 default:
1904 qemu_log_mask(LOG_GUEST_ERROR,
1905 "gic_hyp_read: Bad offset %" HWADDR_PRIx "\n", addr);
1906 return MEMTX_OK;
1907 }
1908
1909 trace_gic_hyp_read(addr, *data);
1910 return MEMTX_OK;
1911}
1912
1913static MemTxResult gic_hyp_write(void *opaque, int cpu, hwaddr addr,
1914 uint64_t value, MemTxAttrs attrs)
1915{
1916 GICState *s = ARM_GIC(opaque);
1917 int vcpu = cpu + GIC_NCPU;
1918
1919 trace_gic_hyp_write(addr, value);
1920
1921 switch (addr) {
1922 case A_GICH_HCR:
1923 s->h_hcr[cpu] = value & GICH_HCR_MASK;
1924 break;
1925
1926 case A_GICH_VMCR:
1927 gic_vmcr_write(s, value, attrs);
1928 break;
1929
1930 case A_GICH_APR:
1931 s->h_apr[cpu] = value;
1932 s->running_priority[vcpu] = gic_get_prio_from_apr_bits(s, vcpu);
1933 break;
1934
1935 case A_GICH_LR0 ... A_GICH_LR63:
1936 {
1937 int lr_idx = (addr - A_GICH_LR0) / 4;
1938
1939 if (lr_idx > s->num_lrs) {
1940 return MEMTX_OK;
1941 }
1942
1943 s->h_lr[lr_idx][cpu] = value & GICH_LR_MASK;
1944 trace_gic_lr_entry(cpu, lr_idx, s->h_lr[lr_idx][cpu]);
1945 break;
1946 }
1947
1948 default:
1949 qemu_log_mask(LOG_GUEST_ERROR,
1950 "gic_hyp_write: Bad offset %" HWADDR_PRIx "\n", addr);
1951 return MEMTX_OK;
1952 }
1953
1954 gic_update_virt(s);
1955 return MEMTX_OK;
1956}
1957
1958static MemTxResult gic_thiscpu_hyp_read(void *opaque, hwaddr addr, uint64_t *data,
1959 unsigned size, MemTxAttrs attrs)
1960{
1961 GICState *s = (GICState *)opaque;
1962
1963 return gic_hyp_read(s, gic_get_current_cpu(s), addr, data, attrs);
1964}
1965
1966static MemTxResult gic_thiscpu_hyp_write(void *opaque, hwaddr addr,
1967 uint64_t value, unsigned size,
1968 MemTxAttrs attrs)
1969{
1970 GICState *s = (GICState *)opaque;
1971
1972 return gic_hyp_write(s, gic_get_current_cpu(s), addr, value, attrs);
1973}
1974
1975static MemTxResult gic_do_hyp_read(void *opaque, hwaddr addr, uint64_t *data,
1976 unsigned size, MemTxAttrs attrs)
1977{
1978 GICState **backref = (GICState **)opaque;
1979 GICState *s = *backref;
1980 int id = (backref - s->backref);
1981
1982 return gic_hyp_read(s, id, addr, data, attrs);
1983}
1984
1985static MemTxResult gic_do_hyp_write(void *opaque, hwaddr addr,
1986 uint64_t value, unsigned size,
1987 MemTxAttrs attrs)
1988{
1989 GICState **backref = (GICState **)opaque;
1990 GICState *s = *backref;
1991 int id = (backref - s->backref);
1992
1993 return gic_hyp_write(s, id + GIC_NCPU, addr, value, attrs);
1994
1995}
1996
1997static const MemoryRegionOps gic_ops[2] = {
1998 {
1999 .read_with_attrs = gic_dist_read,
2000 .write_with_attrs = gic_dist_write,
2001 .endianness = DEVICE_NATIVE_ENDIAN,
2002 },
2003 {
2004 .read_with_attrs = gic_thiscpu_read,
2005 .write_with_attrs = gic_thiscpu_write,
2006 .endianness = DEVICE_NATIVE_ENDIAN,
2007 }
2008};
2009
2010static const MemoryRegionOps gic_cpu_ops = {
2011 .read_with_attrs = gic_do_cpu_read,
2012 .write_with_attrs = gic_do_cpu_write,
2013 .endianness = DEVICE_NATIVE_ENDIAN,
2014};
2015
2016static const MemoryRegionOps gic_virt_ops[2] = {
2017 {
2018 .read_with_attrs = gic_thiscpu_hyp_read,
2019 .write_with_attrs = gic_thiscpu_hyp_write,
2020 .endianness = DEVICE_NATIVE_ENDIAN,
2021 },
2022 {
2023 .read_with_attrs = gic_thisvcpu_read,
2024 .write_with_attrs = gic_thisvcpu_write,
2025 .endianness = DEVICE_NATIVE_ENDIAN,
2026 }
2027};
2028
2029static const MemoryRegionOps gic_viface_ops = {
2030 .read_with_attrs = gic_do_hyp_read,
2031 .write_with_attrs = gic_do_hyp_write,
2032 .endianness = DEVICE_NATIVE_ENDIAN,
2033};
2034
2035static void arm_gic_realize(DeviceState *dev, Error **errp)
2036{
2037
2038 int i;
2039 GICState *s = ARM_GIC(dev);
2040 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
2041 ARMGICClass *agc = ARM_GIC_GET_CLASS(s);
2042 Error *local_err = NULL;
2043
2044 agc->parent_realize(dev, &local_err);
2045 if (local_err) {
2046 error_propagate(errp, local_err);
2047 return;
2048 }
2049
2050 if (kvm_enabled() && !kvm_arm_supports_user_irq()) {
2051 error_setg(errp, "KVM with user space irqchip only works when the "
2052 "host kernel supports KVM_CAP_ARM_USER_IRQ");
2053 return;
2054 }
2055
2056
2057
2058
2059
2060 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops, gic_virt_ops);
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070 for (i = 0; i < s->num_cpu; i++) {
2071 s->backref[i] = s;
2072 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops,
2073 &s->backref[i], "gic_cpu", 0x100);
2074 sysbus_init_mmio(sbd, &s->cpuiomem[i+1]);
2075 }
2076
2077
2078
2079
2080 if (s->virt_extn) {
2081 for (i = 0; i < s->num_cpu; i++) {
2082 memory_region_init_io(&s->vifaceiomem[i + 1], OBJECT(s),
2083 &gic_viface_ops, &s->backref[i],
2084 "gic_viface", 0x200);
2085 sysbus_init_mmio(sbd, &s->vifaceiomem[i + 1]);
2086 }
2087 }
2088
2089}
2090
2091static void arm_gic_class_init(ObjectClass *klass, void *data)
2092{
2093 DeviceClass *dc = DEVICE_CLASS(klass);
2094 ARMGICClass *agc = ARM_GIC_CLASS(klass);
2095
2096 device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_realize);
2097}
2098
2099static const TypeInfo arm_gic_info = {
2100 .name = TYPE_ARM_GIC,
2101 .parent = TYPE_ARM_GIC_COMMON,
2102 .instance_size = sizeof(GICState),
2103 .class_init = arm_gic_class_init,
2104 .class_size = sizeof(ARMGICClass),
2105};
2106
2107static void arm_gic_register_types(void)
2108{
2109 type_register_static(&arm_gic_info);
2110}
2111
2112type_init(arm_gic_register_types)
2113