1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "gic_internal.h"
24#include "hw/arm/linux-boot-if.h"
25
26static int gic_pre_save(void *opaque)
27{
28 GICState *s = (GICState *)opaque;
29 ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
30
31 if (c->pre_save) {
32 c->pre_save(s);
33 }
34
35 return 0;
36}
37
38static int gic_post_load(void *opaque, int version_id)
39{
40 GICState *s = (GICState *)opaque;
41 ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
42
43 if (c->post_load) {
44 c->post_load(s);
45 }
46 return 0;
47}
48
49static bool gic_virt_state_needed(void *opaque)
50{
51 GICState *s = (GICState *)opaque;
52
53 return s->virt_extn;
54}
55
56static const VMStateDescription vmstate_gic_irq_state = {
57 .name = "arm_gic_irq_state",
58 .version_id = 1,
59 .minimum_version_id = 1,
60 .fields = (VMStateField[]) {
61 VMSTATE_UINT8(enabled, gic_irq_state),
62 VMSTATE_UINT8(pending, gic_irq_state),
63 VMSTATE_UINT8(active, gic_irq_state),
64 VMSTATE_UINT8(level, gic_irq_state),
65 VMSTATE_BOOL(model, gic_irq_state),
66 VMSTATE_BOOL(edge_trigger, gic_irq_state),
67 VMSTATE_UINT8(group, gic_irq_state),
68 VMSTATE_END_OF_LIST()
69 }
70};
71
72static const VMStateDescription vmstate_gic_virt_state = {
73 .name = "arm_gic_virt_state",
74 .version_id = 1,
75 .minimum_version_id = 1,
76 .needed = gic_virt_state_needed,
77 .fields = (VMStateField[]) {
78
79 VMSTATE_UINT32_ARRAY(h_hcr, GICState, GIC_NCPU),
80 VMSTATE_UINT32_ARRAY(h_misr, GICState, GIC_NCPU),
81 VMSTATE_UINT32_2DARRAY(h_lr, GICState, GIC_MAX_LR, GIC_NCPU),
82 VMSTATE_UINT32_ARRAY(h_apr, GICState, GIC_NCPU),
83
84
85 VMSTATE_UINT32_SUB_ARRAY(cpu_ctlr, GICState, GIC_NCPU, GIC_NCPU),
86 VMSTATE_UINT16_SUB_ARRAY(priority_mask, GICState, GIC_NCPU, GIC_NCPU),
87 VMSTATE_UINT16_SUB_ARRAY(running_priority, GICState, GIC_NCPU, GIC_NCPU),
88 VMSTATE_UINT16_SUB_ARRAY(current_pending, GICState, GIC_NCPU, GIC_NCPU),
89 VMSTATE_UINT8_SUB_ARRAY(bpr, GICState, GIC_NCPU, GIC_NCPU),
90 VMSTATE_UINT8_SUB_ARRAY(abpr, GICState, GIC_NCPU, GIC_NCPU),
91
92 VMSTATE_END_OF_LIST()
93 }
94};
95
96static const VMStateDescription vmstate_gic = {
97 .name = "arm_gic",
98 .version_id = 12,
99 .minimum_version_id = 12,
100 .pre_save = gic_pre_save,
101 .post_load = gic_post_load,
102 .fields = (VMStateField[]) {
103 VMSTATE_UINT32(ctlr, GICState),
104 VMSTATE_UINT32_SUB_ARRAY(cpu_ctlr, GICState, 0, GIC_NCPU),
105 VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1,
106 vmstate_gic_irq_state, gic_irq_state),
107 VMSTATE_UINT8_ARRAY(irq_target, GICState, GIC_MAXIRQ),
108 VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, GIC_NCPU),
109 VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL),
110 VMSTATE_UINT8_2DARRAY(sgi_pending, GICState, GIC_NR_SGIS, GIC_NCPU),
111 VMSTATE_UINT16_SUB_ARRAY(priority_mask, GICState, 0, GIC_NCPU),
112 VMSTATE_UINT16_SUB_ARRAY(running_priority, GICState, 0, GIC_NCPU),
113 VMSTATE_UINT16_SUB_ARRAY(current_pending, GICState, 0, GIC_NCPU),
114 VMSTATE_UINT8_SUB_ARRAY(bpr, GICState, 0, GIC_NCPU),
115 VMSTATE_UINT8_SUB_ARRAY(abpr, GICState, 0, GIC_NCPU),
116 VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU),
117 VMSTATE_UINT32_2DARRAY(nsapr, GICState, GIC_NR_APRS, GIC_NCPU),
118 VMSTATE_END_OF_LIST()
119 },
120 .subsections = (const VMStateDescription * []) {
121 &vmstate_gic_virt_state,
122 NULL
123 }
124};
125
126void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
127 const MemoryRegionOps *ops,
128 const MemoryRegionOps *virt_ops)
129{
130 SysBusDevice *sbd = SYS_BUS_DEVICE(s);
131 int i = s->num_irq - GIC_INTERNAL;
132
133
134
135
136
137
138
139
140 i += (GIC_INTERNAL * s->num_cpu);
141 qdev_init_gpio_in(DEVICE(s), handler, i);
142
143 for (i = 0; i < s->num_cpu; i++) {
144 sysbus_init_irq(sbd, &s->parent_irq[i]);
145 }
146 for (i = 0; i < s->num_cpu; i++) {
147 sysbus_init_irq(sbd, &s->parent_fiq[i]);
148 }
149 for (i = 0; i < s->num_cpu; i++) {
150 sysbus_init_irq(sbd, &s->parent_virq[i]);
151 }
152 for (i = 0; i < s->num_cpu; i++) {
153 sysbus_init_irq(sbd, &s->parent_vfiq[i]);
154 }
155 if (s->virt_extn) {
156 for (i = 0; i < s->num_cpu; i++) {
157 sysbus_init_irq(sbd, &s->maintenance_irq[i]);
158 }
159 }
160
161
162 memory_region_init_io(&s->iomem, OBJECT(s), ops, s, "gic_dist", 0x1000);
163 sysbus_init_mmio(sbd, &s->iomem);
164
165
166
167
168 memory_region_init_io(&s->cpuiomem[0], OBJECT(s), ops ? &ops[1] : NULL,
169 s, "gic_cpu", s->revision == 2 ? 0x2000 : 0x100);
170 sysbus_init_mmio(sbd, &s->cpuiomem[0]);
171
172 if (s->virt_extn) {
173 memory_region_init_io(&s->vifaceiomem[0], OBJECT(s), virt_ops,
174 s, "gic_viface", 0x1000);
175 sysbus_init_mmio(sbd, &s->vifaceiomem[0]);
176
177 memory_region_init_io(&s->vcpuiomem, OBJECT(s),
178 virt_ops ? &virt_ops[1] : NULL,
179 s, "gic_vcpu", 0x2000);
180 sysbus_init_mmio(sbd, &s->vcpuiomem);
181 }
182}
183
184static void arm_gic_common_realize(DeviceState *dev, Error **errp)
185{
186 GICState *s = ARM_GIC_COMMON(dev);
187 int num_irq = s->num_irq;
188
189 if (s->num_cpu > GIC_NCPU) {
190 error_setg(errp, "requested %u CPUs exceeds GIC maximum %d",
191 s->num_cpu, GIC_NCPU);
192 return;
193 }
194 if (s->num_irq > GIC_MAXIRQ) {
195 error_setg(errp,
196 "requested %u interrupt lines exceeds GIC maximum %d",
197 num_irq, GIC_MAXIRQ);
198 return;
199 }
200
201
202
203
204 if (s->num_irq < 32 || (s->num_irq % 32)) {
205 error_setg(errp,
206 "%d interrupt lines unsupported: not divisible by 32",
207 num_irq);
208 return;
209 }
210
211 if (s->security_extn &&
212 (s->revision == REV_11MPCORE)) {
213 error_setg(errp, "this GIC revision does not implement "
214 "the security extensions");
215 return;
216 }
217
218 if (s->virt_extn) {
219 if (s->revision != 2) {
220 error_setg(errp, "GIC virtualization extensions are only "
221 "supported by revision 2");
222 return;
223 }
224
225
226
227
228
229 s->num_lrs = 4;
230 }
231}
232
233static inline void arm_gic_common_reset_irq_state(GICState *s, int first_cpu,
234 int resetprio)
235{
236 int i, j;
237
238 for (i = first_cpu; i < first_cpu + s->num_cpu; i++) {
239 if (s->revision == REV_11MPCORE) {
240 s->priority_mask[i] = 0xf0;
241 } else {
242 s->priority_mask[i] = resetprio;
243 }
244 s->current_pending[i] = 1023;
245 s->running_priority[i] = 0x100;
246 s->cpu_ctlr[i] = 0;
247 s->bpr[i] = gic_is_vcpu(i) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR;
248 s->abpr[i] = gic_is_vcpu(i) ? GIC_VIRT_MIN_ABPR : GIC_MIN_ABPR;
249
250 if (!gic_is_vcpu(i)) {
251 for (j = 0; j < GIC_INTERNAL; j++) {
252 s->priority1[j][i] = resetprio;
253 }
254 for (j = 0; j < GIC_NR_SGIS; j++) {
255 s->sgi_pending[j][i] = 0;
256 }
257 }
258 }
259}
260
261static void arm_gic_common_reset(DeviceState *dev)
262{
263 GICState *s = ARM_GIC_COMMON(dev);
264 int i, j;
265 int resetprio;
266
267
268
269
270
271
272
273
274 if (s->security_extn && s->irq_reset_nonsecure) {
275 resetprio = 0x80;
276 } else {
277 resetprio = 0;
278 }
279
280 memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
281 arm_gic_common_reset_irq_state(s, 0, resetprio);
282
283 if (s->virt_extn) {
284
285
286
287 arm_gic_common_reset_irq_state(s, GIC_NCPU, 0);
288 }
289
290 for (i = 0; i < GIC_NR_SGIS; i++) {
291 GIC_DIST_SET_ENABLED(i, ALL_CPU_MASK);
292 GIC_DIST_SET_EDGE_TRIGGER(i);
293 }
294
295 for (i = 0; i < ARRAY_SIZE(s->priority2); i++) {
296 s->priority2[i] = resetprio;
297 }
298
299 for (i = 0; i < GIC_MAXIRQ; i++) {
300
301 if (s->num_cpu == 1) {
302 s->irq_target[i] = 1;
303 } else {
304 s->irq_target[i] = 0;
305 }
306 }
307 if (s->security_extn && s->irq_reset_nonsecure) {
308 for (i = 0; i < GIC_MAXIRQ; i++) {
309 GIC_DIST_SET_GROUP(i, ALL_CPU_MASK);
310 }
311 }
312
313 if (s->virt_extn) {
314 for (i = 0; i < s->num_lrs; i++) {
315 for (j = 0; j < s->num_cpu; j++) {
316 s->h_lr[i][j] = 0;
317 }
318 }
319
320 for (i = 0; i < s->num_cpu; i++) {
321 s->h_hcr[i] = 0;
322 s->h_misr[i] = 0;
323 }
324 }
325
326 s->ctlr = 0;
327}
328
329static void arm_gic_common_linux_init(ARMLinuxBootIf *obj,
330 bool secure_boot)
331{
332 GICState *s = ARM_GIC_COMMON(obj);
333
334 if (s->security_extn && !secure_boot) {
335
336
337
338
339
340
341
342 s->irq_reset_nonsecure = true;
343 }
344}
345
346static Property arm_gic_common_properties[] = {
347 DEFINE_PROP_UINT32("num-cpu", GICState, num_cpu, 1),
348 DEFINE_PROP_UINT32("num-irq", GICState, num_irq, 32),
349
350
351
352 DEFINE_PROP_UINT32("revision", GICState, revision, 1),
353
354 DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0),
355
356 DEFINE_PROP_BOOL("has-virtualization-extensions", GICState, virt_extn, 0),
357 DEFINE_PROP_END_OF_LIST(),
358};
359
360static void arm_gic_common_class_init(ObjectClass *klass, void *data)
361{
362 DeviceClass *dc = DEVICE_CLASS(klass);
363 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
364
365 dc->reset = arm_gic_common_reset;
366 dc->realize = arm_gic_common_realize;
367 dc->props = arm_gic_common_properties;
368 dc->vmsd = &vmstate_gic;
369 albifc->arm_linux_init = arm_gic_common_linux_init;
370}
371
372static const TypeInfo arm_gic_common_type = {
373 .name = TYPE_ARM_GIC_COMMON,
374 .parent = TYPE_SYS_BUS_DEVICE,
375 .instance_size = sizeof(GICState),
376 .class_size = sizeof(ARMGICCommonClass),
377 .class_init = arm_gic_common_class_init,
378 .abstract = true,
379 .interfaces = (InterfaceInfo []) {
380 { TYPE_ARM_LINUX_BOOT_IF },
381 { },
382 },
383};
384
385static void register_types(void)
386{
387 type_register_static(&arm_gic_common_type);
388}
389
390type_init(register_types)
391