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18#include "qemu/osdep.h"
19#include "qapi/error.h"
20#include "hw/sysbus.h"
21#include "hw/intc/arm_gicv3.h"
22#include "gicv3_internal.h"
23
24static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio)
25{
26
27
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30
31
32
33 if (prio < cs->hppi.prio) {
34 return true;
35 }
36
37
38
39
40 if (prio == cs->hppi.prio && irq <= cs->hppi.irq) {
41 return true;
42 }
43 return false;
44}
45
46static uint32_t gicd_int_pending(GICv3State *s, int irq)
47{
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59
60 uint32_t pend, grpmask;
61 uint32_t pending = *gic_bmp_ptr32(s->pending, irq);
62 uint32_t edge_trigger = *gic_bmp_ptr32(s->edge_trigger, irq);
63 uint32_t level = *gic_bmp_ptr32(s->level, irq);
64 uint32_t group = *gic_bmp_ptr32(s->group, irq);
65 uint32_t grpmod = *gic_bmp_ptr32(s->grpmod, irq);
66 uint32_t enable = *gic_bmp_ptr32(s->enabled, irq);
67 uint32_t active = *gic_bmp_ptr32(s->active, irq);
68
69 pend = pending | (~edge_trigger & level);
70 pend &= enable;
71 pend &= ~active;
72
73 if (s->gicd_ctlr & GICD_CTLR_DS) {
74 grpmod = 0;
75 }
76
77 grpmask = 0;
78 if (s->gicd_ctlr & GICD_CTLR_EN_GRP1NS) {
79 grpmask |= group;
80 }
81 if (s->gicd_ctlr & GICD_CTLR_EN_GRP1S) {
82 grpmask |= (~group & grpmod);
83 }
84 if (s->gicd_ctlr & GICD_CTLR_EN_GRP0) {
85 grpmask |= (~group & ~grpmod);
86 }
87 pend &= grpmask;
88
89 return pend;
90}
91
92static uint32_t gicr_int_pending(GICv3CPUState *cs)
93{
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105 uint32_t pend, grpmask, grpmod;
106
107 pend = cs->gicr_ipendr0 | (~cs->edge_trigger & cs->level);
108 pend &= cs->gicr_ienabler0;
109 pend &= ~cs->gicr_iactiver0;
110
111 if (cs->gic->gicd_ctlr & GICD_CTLR_DS) {
112 grpmod = 0;
113 } else {
114 grpmod = cs->gicr_igrpmodr0;
115 }
116
117 grpmask = 0;
118 if (cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP1NS) {
119 grpmask |= cs->gicr_igroupr0;
120 }
121 if (cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP1S) {
122 grpmask |= (~cs->gicr_igroupr0 & grpmod);
123 }
124 if (cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP0) {
125 grpmask |= (~cs->gicr_igroupr0 & ~grpmod);
126 }
127 pend &= grpmask;
128
129 return pend;
130}
131
132
133
134
135static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
136{
137
138
139
140 bool seenbetter = false;
141 uint8_t prio;
142 int i;
143 uint32_t pend;
144
145
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148 pend = gicr_int_pending(cs);
149
150 if (pend) {
151 for (i = 0; i < GIC_INTERNAL; i++) {
152 if (!(pend & (1 << i))) {
153 continue;
154 }
155 prio = cs->gicr_ipriorityr[i];
156 if (irqbetter(cs, i, prio)) {
157 cs->hppi.irq = i;
158 cs->hppi.prio = prio;
159 seenbetter = true;
160 }
161 }
162 }
163
164 if (seenbetter) {
165 cs->hppi.grp = gicv3_irq_group(cs->gic, cs, cs->hppi.irq);
166 }
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179 if (!seenbetter && cs->hppi.prio != 0xff && cs->hppi.irq < GIC_INTERNAL) {
180 gicv3_full_update_noirqset(cs->gic);
181 }
182}
183
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186
187
188void gicv3_redist_update(GICv3CPUState *cs)
189{
190 gicv3_redist_update_noirqset(cs);
191 gicv3_cpuif_update(cs);
192}
193
194
195
196
197
198static void gicv3_update_noirqset(GICv3State *s, int start, int len)
199{
200 int i;
201 uint8_t prio;
202 uint32_t pend = 0;
203
204 assert(start >= GIC_INTERNAL);
205 assert(len > 0);
206
207 for (i = 0; i < s->num_cpu; i++) {
208 s->cpu[i].seenbetter = false;
209 }
210
211
212 for (i = start; i < start + len; i++) {
213 GICv3CPUState *cs;
214
215 if (i == start || (i & 0x1f) == 0) {
216
217 pend = gicd_int_pending(s, i & ~0x1f);
218 }
219
220 if (!(pend & (1 << (i & 0x1f)))) {
221 continue;
222 }
223 cs = s->gicd_irouter_target[i];
224 if (!cs) {
225
226
227
228 continue;
229 }
230 prio = s->gicd_ipriority[i];
231 if (irqbetter(cs, i, prio)) {
232 cs->hppi.irq = i;
233 cs->hppi.prio = prio;
234 cs->seenbetter = true;
235 }
236 }
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249 for (i = 0; i < s->num_cpu; i++) {
250 GICv3CPUState *cs = &s->cpu[i];
251
252 if (cs->seenbetter) {
253 cs->hppi.grp = gicv3_irq_group(cs->gic, cs, cs->hppi.irq);
254 }
255
256 if (!cs->seenbetter && cs->hppi.prio != 0xff &&
257 cs->hppi.irq >= start && cs->hppi.irq < start + len) {
258 gicv3_full_update_noirqset(s);
259 break;
260 }
261 }
262}
263
264void gicv3_update(GICv3State *s, int start, int len)
265{
266 int i;
267
268 gicv3_update_noirqset(s, start, len);
269 for (i = 0; i < s->num_cpu; i++) {
270 gicv3_cpuif_update(&s->cpu[i]);
271 }
272}
273
274void gicv3_full_update_noirqset(GICv3State *s)
275{
276
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279 int i;
280
281 for (i = 0; i < s->num_cpu; i++) {
282 s->cpu[i].hppi.prio = 0xff;
283 }
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289
290 gicv3_update_noirqset(s, GIC_INTERNAL, s->num_irq - GIC_INTERNAL);
291
292 for (i = 0; i < s->num_cpu; i++) {
293 gicv3_redist_update_noirqset(&s->cpu[i]);
294 }
295}
296
297void gicv3_full_update(GICv3State *s)
298{
299
300
301
302 int i;
303
304 gicv3_full_update_noirqset(s);
305 for (i = 0; i < s->num_cpu; i++) {
306 gicv3_cpuif_update(&s->cpu[i]);
307 }
308}
309
310
311static void gicv3_set_irq(void *opaque, int irq, int level)
312{
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314
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316
317
318
319 GICv3State *s = opaque;
320
321 if (irq < (s->num_irq - GIC_INTERNAL)) {
322
323 gicv3_dist_set_irq(s, irq + GIC_INTERNAL, level);
324 } else {
325
326 int cpu;
327
328 irq -= (s->num_irq - GIC_INTERNAL);
329 cpu = irq / GIC_INTERNAL;
330 irq %= GIC_INTERNAL;
331 assert(cpu < s->num_cpu);
332
333
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335 assert(irq >= GIC_NR_SGIS);
336 gicv3_redist_set_irq(&s->cpu[cpu], irq, level);
337 }
338}
339
340static void arm_gicv3_post_load(GICv3State *s)
341{
342
343
344
345 gicv3_full_update_noirqset(s);
346
347 gicv3_cache_all_target_cpustates(s);
348}
349
350static const MemoryRegionOps gic_ops[] = {
351 {
352 .read_with_attrs = gicv3_dist_read,
353 .write_with_attrs = gicv3_dist_write,
354 .endianness = DEVICE_NATIVE_ENDIAN,
355 },
356 {
357 .read_with_attrs = gicv3_redist_read,
358 .write_with_attrs = gicv3_redist_write,
359 .endianness = DEVICE_NATIVE_ENDIAN,
360 }
361};
362
363static void arm_gic_realize(DeviceState *dev, Error **errp)
364{
365
366 GICv3State *s = ARM_GICV3(dev);
367 ARMGICv3Class *agc = ARM_GICV3_GET_CLASS(s);
368 Error *local_err = NULL;
369
370 agc->parent_realize(dev, &local_err);
371 if (local_err) {
372 error_propagate(errp, local_err);
373 return;
374 }
375
376 if (s->nb_redist_regions != 1) {
377 error_setg(errp, "VGICv3 redist region number(%d) not equal to 1",
378 s->nb_redist_regions);
379 return;
380 }
381
382 gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops, &local_err);
383 if (local_err) {
384 error_propagate(errp, local_err);
385 return;
386 }
387
388 gicv3_init_cpuif(s);
389}
390
391static void arm_gicv3_class_init(ObjectClass *klass, void *data)
392{
393 DeviceClass *dc = DEVICE_CLASS(klass);
394 ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass);
395 ARMGICv3Class *agc = ARM_GICV3_CLASS(klass);
396
397 agcc->post_load = arm_gicv3_post_load;
398 device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_realize);
399}
400
401static const TypeInfo arm_gicv3_info = {
402 .name = TYPE_ARM_GICV3,
403 .parent = TYPE_ARM_GICV3_COMMON,
404 .instance_size = sizeof(GICv3State),
405 .class_init = arm_gicv3_class_init,
406 .class_size = sizeof(ARMGICv3Class),
407};
408
409static void arm_gicv3_register_types(void)
410{
411 type_register_static(&arm_gicv3_info);
412}
413
414type_init(arm_gicv3_register_types)
415