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24#include "qemu/osdep.h"
25#include "qapi/error.h"
26#include "qom/cpu.h"
27#include "hw/intc/arm_gicv3_common.h"
28#include "gicv3_internal.h"
29#include "hw/arm/linux-boot-if.h"
30#include "sysemu/kvm.h"
31
32
33static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs)
34{
35 if (cs->gicd_no_migration_shift_bug) {
36 return;
37 }
38
39
40
41
42
43
44
45
46 memmove(cs->group, (uint8_t *)cs->group + GIC_INTERNAL / 8,
47 sizeof(cs->group) - GIC_INTERNAL / 8);
48 memmove(cs->grpmod, (uint8_t *)cs->grpmod + GIC_INTERNAL / 8,
49 sizeof(cs->grpmod) - GIC_INTERNAL / 8);
50 memmove(cs->enabled, (uint8_t *)cs->enabled + GIC_INTERNAL / 8,
51 sizeof(cs->enabled) - GIC_INTERNAL / 8);
52 memmove(cs->pending, (uint8_t *)cs->pending + GIC_INTERNAL / 8,
53 sizeof(cs->pending) - GIC_INTERNAL / 8);
54 memmove(cs->active, (uint8_t *)cs->active + GIC_INTERNAL / 8,
55 sizeof(cs->active) - GIC_INTERNAL / 8);
56 memmove(cs->edge_trigger, (uint8_t *)cs->edge_trigger + GIC_INTERNAL / 8,
57 sizeof(cs->edge_trigger) - GIC_INTERNAL / 8);
58
59
60
61
62
63
64 cs->gicd_no_migration_shift_bug = true;
65}
66
67static int gicv3_pre_save(void *opaque)
68{
69 GICv3State *s = (GICv3State *)opaque;
70 ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s);
71
72 if (c->pre_save) {
73 c->pre_save(s);
74 }
75
76 return 0;
77}
78
79static int gicv3_post_load(void *opaque, int version_id)
80{
81 GICv3State *s = (GICv3State *)opaque;
82 ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s);
83
84 gicv3_gicd_no_migration_shift_bug_post_load(s);
85
86 if (c->post_load) {
87 c->post_load(s);
88 }
89 return 0;
90}
91
92static bool virt_state_needed(void *opaque)
93{
94 GICv3CPUState *cs = opaque;
95
96 return cs->num_list_regs != 0;
97}
98
99static const VMStateDescription vmstate_gicv3_cpu_virt = {
100 .name = "arm_gicv3_cpu/virt",
101 .version_id = 1,
102 .minimum_version_id = 1,
103 .needed = virt_state_needed,
104 .fields = (VMStateField[]) {
105 VMSTATE_UINT64_2DARRAY(ich_apr, GICv3CPUState, 3, 4),
106 VMSTATE_UINT64(ich_hcr_el2, GICv3CPUState),
107 VMSTATE_UINT64_ARRAY(ich_lr_el2, GICv3CPUState, GICV3_LR_MAX),
108 VMSTATE_UINT64(ich_vmcr_el2, GICv3CPUState),
109 VMSTATE_END_OF_LIST()
110 }
111};
112
113static int vmstate_gicv3_cpu_pre_load(void *opaque)
114{
115 GICv3CPUState *cs = opaque;
116
117
118
119
120
121
122 cs->icc_sre_el1 = 0x7;
123 return 0;
124}
125
126static bool icc_sre_el1_reg_needed(void *opaque)
127{
128 GICv3CPUState *cs = opaque;
129
130 return cs->icc_sre_el1 != 7;
131}
132
133const VMStateDescription vmstate_gicv3_cpu_sre_el1 = {
134 .name = "arm_gicv3_cpu/sre_el1",
135 .version_id = 1,
136 .minimum_version_id = 1,
137 .needed = icc_sre_el1_reg_needed,
138 .fields = (VMStateField[]) {
139 VMSTATE_UINT64(icc_sre_el1, GICv3CPUState),
140 VMSTATE_END_OF_LIST()
141 }
142};
143
144static const VMStateDescription vmstate_gicv3_cpu = {
145 .name = "arm_gicv3_cpu",
146 .version_id = 1,
147 .minimum_version_id = 1,
148 .pre_load = vmstate_gicv3_cpu_pre_load,
149 .fields = (VMStateField[]) {
150 VMSTATE_UINT32(level, GICv3CPUState),
151 VMSTATE_UINT32(gicr_ctlr, GICv3CPUState),
152 VMSTATE_UINT32_ARRAY(gicr_statusr, GICv3CPUState, 2),
153 VMSTATE_UINT32(gicr_waker, GICv3CPUState),
154 VMSTATE_UINT64(gicr_propbaser, GICv3CPUState),
155 VMSTATE_UINT64(gicr_pendbaser, GICv3CPUState),
156 VMSTATE_UINT32(gicr_igroupr0, GICv3CPUState),
157 VMSTATE_UINT32(gicr_ienabler0, GICv3CPUState),
158 VMSTATE_UINT32(gicr_ipendr0, GICv3CPUState),
159 VMSTATE_UINT32(gicr_iactiver0, GICv3CPUState),
160 VMSTATE_UINT32(edge_trigger, GICv3CPUState),
161 VMSTATE_UINT32(gicr_igrpmodr0, GICv3CPUState),
162 VMSTATE_UINT32(gicr_nsacr, GICv3CPUState),
163 VMSTATE_UINT8_ARRAY(gicr_ipriorityr, GICv3CPUState, GIC_INTERNAL),
164 VMSTATE_UINT64_ARRAY(icc_ctlr_el1, GICv3CPUState, 2),
165 VMSTATE_UINT64(icc_pmr_el1, GICv3CPUState),
166 VMSTATE_UINT64_ARRAY(icc_bpr, GICv3CPUState, 3),
167 VMSTATE_UINT64_2DARRAY(icc_apr, GICv3CPUState, 3, 4),
168 VMSTATE_UINT64_ARRAY(icc_igrpen, GICv3CPUState, 3),
169 VMSTATE_UINT64(icc_ctlr_el3, GICv3CPUState),
170 VMSTATE_END_OF_LIST()
171 },
172 .subsections = (const VMStateDescription * []) {
173 &vmstate_gicv3_cpu_virt,
174 &vmstate_gicv3_cpu_sre_el1,
175 NULL
176 }
177};
178
179static int gicv3_pre_load(void *opaque)
180{
181 GICv3State *cs = opaque;
182
183
184
185
186
187
188
189
190
191
192
193
194 if (kvm_enabled()) {
195 cs->gicd_no_migration_shift_bug = false;
196 }
197
198 return 0;
199}
200
201static bool needed_always(void *opaque)
202{
203 return true;
204}
205
206const VMStateDescription vmstate_gicv3_gicd_no_migration_shift_bug = {
207 .name = "arm_gicv3/gicd_no_migration_shift_bug",
208 .version_id = 1,
209 .minimum_version_id = 1,
210 .needed = needed_always,
211 .fields = (VMStateField[]) {
212 VMSTATE_BOOL(gicd_no_migration_shift_bug, GICv3State),
213 VMSTATE_END_OF_LIST()
214 }
215};
216
217static const VMStateDescription vmstate_gicv3 = {
218 .name = "arm_gicv3",
219 .version_id = 1,
220 .minimum_version_id = 1,
221 .pre_load = gicv3_pre_load,
222 .pre_save = gicv3_pre_save,
223 .post_load = gicv3_post_load,
224 .priority = MIG_PRI_GICV3,
225 .fields = (VMStateField[]) {
226 VMSTATE_UINT32(gicd_ctlr, GICv3State),
227 VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2),
228 VMSTATE_UINT32_ARRAY(group, GICv3State, GICV3_BMP_SIZE),
229 VMSTATE_UINT32_ARRAY(grpmod, GICv3State, GICV3_BMP_SIZE),
230 VMSTATE_UINT32_ARRAY(enabled, GICv3State, GICV3_BMP_SIZE),
231 VMSTATE_UINT32_ARRAY(pending, GICv3State, GICV3_BMP_SIZE),
232 VMSTATE_UINT32_ARRAY(active, GICv3State, GICV3_BMP_SIZE),
233 VMSTATE_UINT32_ARRAY(level, GICv3State, GICV3_BMP_SIZE),
234 VMSTATE_UINT32_ARRAY(edge_trigger, GICv3State, GICV3_BMP_SIZE),
235 VMSTATE_UINT8_ARRAY(gicd_ipriority, GICv3State, GICV3_MAXIRQ),
236 VMSTATE_UINT64_ARRAY(gicd_irouter, GICv3State, GICV3_MAXIRQ),
237 VMSTATE_UINT32_ARRAY(gicd_nsacr, GICv3State,
238 DIV_ROUND_UP(GICV3_MAXIRQ, 16)),
239 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, GICv3State, num_cpu,
240 vmstate_gicv3_cpu, GICv3CPUState),
241 VMSTATE_END_OF_LIST()
242 },
243 .subsections = (const VMStateDescription * []) {
244 &vmstate_gicv3_gicd_no_migration_shift_bug,
245 NULL
246 }
247};
248
249void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
250 const MemoryRegionOps *ops, Error **errp)
251{
252 SysBusDevice *sbd = SYS_BUS_DEVICE(s);
253 int rdist_capacity = 0;
254 int i;
255
256 for (i = 0; i < s->nb_redist_regions; i++) {
257 rdist_capacity += s->redist_region_count[i];
258 }
259 if (rdist_capacity < s->num_cpu) {
260 error_setg(errp, "Capacity of the redist regions(%d) "
261 "is less than number of vcpus(%d)",
262 rdist_capacity, s->num_cpu);
263 return;
264 }
265
266
267
268
269
270
271
272
273 i = s->num_irq - GIC_INTERNAL + GIC_INTERNAL * s->num_cpu;
274 qdev_init_gpio_in(DEVICE(s), handler, i);
275
276 for (i = 0; i < s->num_cpu; i++) {
277 sysbus_init_irq(sbd, &s->cpu[i].parent_irq);
278 }
279 for (i = 0; i < s->num_cpu; i++) {
280 sysbus_init_irq(sbd, &s->cpu[i].parent_fiq);
281 }
282 for (i = 0; i < s->num_cpu; i++) {
283 sysbus_init_irq(sbd, &s->cpu[i].parent_virq);
284 }
285 for (i = 0; i < s->num_cpu; i++) {
286 sysbus_init_irq(sbd, &s->cpu[i].parent_vfiq);
287 }
288
289 memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s,
290 "gicv3_dist", 0x10000);
291 sysbus_init_mmio(sbd, &s->iomem_dist);
292
293 s->iomem_redist = g_new0(MemoryRegion, s->nb_redist_regions);
294 for (i = 0; i < s->nb_redist_regions; i++) {
295 char *name = g_strdup_printf("gicv3_redist_region[%d]", i);
296
297 memory_region_init_io(&s->iomem_redist[i], OBJECT(s),
298 ops ? &ops[1] : NULL, s, name,
299 s->redist_region_count[i] * GICV3_REDIST_SIZE);
300 sysbus_init_mmio(sbd, &s->iomem_redist[i]);
301 g_free(name);
302 }
303}
304
305static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
306{
307 GICv3State *s = ARM_GICV3_COMMON(dev);
308 int i;
309
310
311
312
313
314
315 if (s->revision != 3) {
316 error_setg(errp, "unsupported GIC revision %d", s->revision);
317 return;
318 }
319
320 if (s->num_irq > GICV3_MAXIRQ) {
321 error_setg(errp,
322 "requested %u interrupt lines exceeds GIC maximum %d",
323 s->num_irq, GICV3_MAXIRQ);
324 return;
325 }
326 if (s->num_irq < GIC_INTERNAL) {
327 error_setg(errp,
328 "requested %u interrupt lines is below GIC minimum %d",
329 s->num_irq, GIC_INTERNAL);
330 return;
331 }
332
333
334
335
336
337
338 if (s->num_irq % 32) {
339 error_setg(errp,
340 "%d interrupt lines unsupported: not divisible by 32",
341 s->num_irq);
342 return;
343 }
344
345 s->cpu = g_new0(GICv3CPUState, s->num_cpu);
346
347 for (i = 0; i < s->num_cpu; i++) {
348 CPUState *cpu = qemu_get_cpu(i);
349 uint64_t cpu_affid;
350 int last;
351
352 s->cpu[i].cpu = cpu;
353 s->cpu[i].gic = s;
354
355 gicv3_set_gicv3state(cpu, &s->cpu[i]);
356
357
358
359
360
361
362
363
364
365
366
367
368
369 cpu_affid = object_property_get_uint(OBJECT(cpu), "mp-affinity", NULL);
370 last = (i == s->num_cpu - 1);
371
372
373
374
375 cpu_affid = ((cpu_affid & 0xFF00000000ULL) >> 8) |
376 (cpu_affid & 0xFFFFFF);
377 s->cpu[i].gicr_typer = (cpu_affid << 32) |
378 (1 << 24) |
379 (i << 8) |
380 (last << 4);
381 }
382}
383
384static void arm_gicv3_finalize(Object *obj)
385{
386 GICv3State *s = ARM_GICV3_COMMON(obj);
387
388 g_free(s->redist_region_count);
389}
390
391static void arm_gicv3_common_reset(DeviceState *dev)
392{
393 GICv3State *s = ARM_GICV3_COMMON(dev);
394 int i;
395
396 for (i = 0; i < s->num_cpu; i++) {
397 GICv3CPUState *cs = &s->cpu[i];
398
399 cs->level = 0;
400 cs->gicr_ctlr = 0;
401 cs->gicr_statusr[GICV3_S] = 0;
402 cs->gicr_statusr[GICV3_NS] = 0;
403 cs->gicr_waker = GICR_WAKER_ProcessorSleep | GICR_WAKER_ChildrenAsleep;
404 cs->gicr_propbaser = 0;
405 cs->gicr_pendbaser = 0;
406
407
408
409
410
411 if (s->irq_reset_nonsecure) {
412 cs->gicr_igroupr0 = 0xffffffff;
413 } else {
414 cs->gicr_igroupr0 = 0;
415 }
416
417 cs->gicr_ienabler0 = 0;
418 cs->gicr_ipendr0 = 0;
419 cs->gicr_iactiver0 = 0;
420 cs->edge_trigger = 0xffff;
421 cs->gicr_igrpmodr0 = 0;
422 cs->gicr_nsacr = 0;
423 memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr));
424
425 cs->hppi.prio = 0xff;
426
427
428
429
430 }
431
432
433 if (s->security_extn) {
434 s->gicd_ctlr = GICD_CTLR_ARE_S | GICD_CTLR_ARE_NS;
435 } else {
436 s->gicd_ctlr = GICD_CTLR_DS | GICD_CTLR_ARE;
437 }
438
439 s->gicd_statusr[GICV3_S] = 0;
440 s->gicd_statusr[GICV3_NS] = 0;
441
442 memset(s->group, 0, sizeof(s->group));
443 memset(s->grpmod, 0, sizeof(s->grpmod));
444 memset(s->enabled, 0, sizeof(s->enabled));
445 memset(s->pending, 0, sizeof(s->pending));
446 memset(s->active, 0, sizeof(s->active));
447 memset(s->level, 0, sizeof(s->level));
448 memset(s->edge_trigger, 0, sizeof(s->edge_trigger));
449 memset(s->gicd_ipriority, 0, sizeof(s->gicd_ipriority));
450 memset(s->gicd_irouter, 0, sizeof(s->gicd_irouter));
451 memset(s->gicd_nsacr, 0, sizeof(s->gicd_nsacr));
452
453
454
455
456
457
458 gicv3_cache_all_target_cpustates(s);
459
460 if (s->irq_reset_nonsecure) {
461
462
463
464
465
466 for (i = GIC_INTERNAL; i < s->num_irq; i++) {
467 gicv3_gicd_group_set(s, i);
468 }
469 }
470 s->gicd_no_migration_shift_bug = true;
471}
472
473static void arm_gic_common_linux_init(ARMLinuxBootIf *obj,
474 bool secure_boot)
475{
476 GICv3State *s = ARM_GICV3_COMMON(obj);
477
478 if (s->security_extn && !secure_boot) {
479
480
481
482
483
484
485
486 s->irq_reset_nonsecure = true;
487 }
488}
489
490static Property arm_gicv3_common_properties[] = {
491 DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1),
492 DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
493 DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
494 DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
495 DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions,
496 redist_region_count, qdev_prop_uint32, uint32_t),
497 DEFINE_PROP_END_OF_LIST(),
498};
499
500static void arm_gicv3_common_class_init(ObjectClass *klass, void *data)
501{
502 DeviceClass *dc = DEVICE_CLASS(klass);
503 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
504
505 dc->reset = arm_gicv3_common_reset;
506 dc->realize = arm_gicv3_common_realize;
507 dc->props = arm_gicv3_common_properties;
508 dc->vmsd = &vmstate_gicv3;
509 albifc->arm_linux_init = arm_gic_common_linux_init;
510}
511
512static const TypeInfo arm_gicv3_common_type = {
513 .name = TYPE_ARM_GICV3_COMMON,
514 .parent = TYPE_SYS_BUS_DEVICE,
515 .instance_size = sizeof(GICv3State),
516 .class_size = sizeof(ARMGICv3CommonClass),
517 .class_init = arm_gicv3_common_class_init,
518 .instance_finalize = arm_gicv3_finalize,
519 .abstract = true,
520 .interfaces = (InterfaceInfo []) {
521 { TYPE_ARM_LINUX_BOOT_IF },
522 { },
523 },
524};
525
526static void register_types(void)
527{
528 type_register_static(&arm_gicv3_common_type);
529}
530
531type_init(register_types)
532