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18#include "qemu/osdep.h"
19#include "qapi/error.h"
20#include "qemu-common.h"
21#include "exec/address-spaces.h"
22#include "hw/boards.h"
23#include "hw/qdev-properties.h"
24#include "cpu.h"
25#include "boot.h"
26
27#include "hw/intc/xlnx-zynqmp-ipi.h"
28#include "hw/intc/xlnx-pmu-iomod-intc.h"
29
30
31
32#define TYPE_XLNX_ZYNQMP_PMU_SOC "xlnx,zynqmp-pmu-soc"
33#define XLNX_ZYNQMP_PMU_SOC(obj) OBJECT_CHECK(XlnxZynqMPPMUSoCState, (obj), \
34 TYPE_XLNX_ZYNQMP_PMU_SOC)
35
36#define XLNX_ZYNQMP_PMU_ROM_SIZE 0x8000
37#define XLNX_ZYNQMP_PMU_ROM_ADDR 0xFFD00000
38#define XLNX_ZYNQMP_PMU_RAM_ADDR 0xFFDC0000
39
40#define XLNX_ZYNQMP_PMU_INTC_ADDR 0xFFD40000
41
42#define XLNX_ZYNQMP_PMU_NUM_IPIS 4
43
44static const uint64_t ipi_addr[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
45 0xFF340000, 0xFF350000, 0xFF360000, 0xFF370000,
46};
47static const uint64_t ipi_irq[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
48 19, 20, 21, 22,
49};
50
51typedef struct XlnxZynqMPPMUSoCState {
52
53 DeviceState parent_obj;
54
55
56 MicroBlazeCPU cpu;
57 XlnxPMUIOIntc intc;
58} XlnxZynqMPPMUSoCState;
59
60
61static void xlnx_zynqmp_pmu_soc_init(Object *obj)
62{
63 XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(obj);
64
65 object_initialize_child(obj, "pmu-cpu", &s->cpu, sizeof(s->cpu),
66 TYPE_MICROBLAZE_CPU, &error_abort, NULL);
67
68 sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc),
69 TYPE_XLNX_PMU_IO_INTC);
70}
71
72static void xlnx_zynqmp_pmu_soc_realize(DeviceState *dev, Error **errp)
73{
74 XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(dev);
75 Error *err = NULL;
76
77 object_property_set_uint(OBJECT(&s->cpu), XLNX_ZYNQMP_PMU_ROM_ADDR,
78 "base-vectors", &error_abort);
79 object_property_set_bool(OBJECT(&s->cpu), true, "use-stack-protection",
80 &error_abort);
81 object_property_set_uint(OBJECT(&s->cpu), 0, "use-fpu", &error_abort);
82 object_property_set_uint(OBJECT(&s->cpu), 0, "use-hw-mul", &error_abort);
83 object_property_set_bool(OBJECT(&s->cpu), true, "use-barrel",
84 &error_abort);
85 object_property_set_bool(OBJECT(&s->cpu), true, "use-msr-instr",
86 &error_abort);
87 object_property_set_bool(OBJECT(&s->cpu), true, "use-pcmp-instr",
88 &error_abort);
89 object_property_set_bool(OBJECT(&s->cpu), false, "use-mmu", &error_abort);
90 object_property_set_bool(OBJECT(&s->cpu), true, "endianness",
91 &error_abort);
92 object_property_set_str(OBJECT(&s->cpu), "8.40.b", "version",
93 &error_abort);
94 object_property_set_uint(OBJECT(&s->cpu), 0, "pvr", &error_abort);
95 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
96 if (err) {
97 error_propagate(errp, err);
98 return;
99 }
100
101 object_property_set_uint(OBJECT(&s->intc), 0x10, "intc-intr-size",
102 &error_abort);
103 object_property_set_uint(OBJECT(&s->intc), 0x0, "intc-level-edge",
104 &error_abort);
105 object_property_set_uint(OBJECT(&s->intc), 0xffff, "intc-positive",
106 &error_abort);
107 object_property_set_bool(OBJECT(&s->intc), true, "realized", &err);
108 if (err) {
109 error_propagate(errp, err);
110 return;
111 }
112 sysbus_mmio_map(SYS_BUS_DEVICE(&s->intc), 0, XLNX_ZYNQMP_PMU_INTC_ADDR);
113 sysbus_connect_irq(SYS_BUS_DEVICE(&s->intc), 0,
114 qdev_get_gpio_in(DEVICE(&s->cpu), MB_CPU_IRQ));
115}
116
117static void xlnx_zynqmp_pmu_soc_class_init(ObjectClass *oc, void *data)
118{
119 DeviceClass *dc = DEVICE_CLASS(oc);
120
121 dc->realize = xlnx_zynqmp_pmu_soc_realize;
122}
123
124static const TypeInfo xlnx_zynqmp_pmu_soc_type_info = {
125 .name = TYPE_XLNX_ZYNQMP_PMU_SOC,
126 .parent = TYPE_DEVICE,
127 .instance_size = sizeof(XlnxZynqMPPMUSoCState),
128 .instance_init = xlnx_zynqmp_pmu_soc_init,
129 .class_init = xlnx_zynqmp_pmu_soc_class_init,
130};
131
132static void xlnx_zynqmp_pmu_soc_register_types(void)
133{
134 type_register_static(&xlnx_zynqmp_pmu_soc_type_info);
135}
136
137type_init(xlnx_zynqmp_pmu_soc_register_types)
138
139
140
141static void xlnx_zynqmp_pmu_init(MachineState *machine)
142{
143 XlnxZynqMPPMUSoCState *pmu = g_new0(XlnxZynqMPPMUSoCState, 1);
144 MemoryRegion *address_space_mem = get_system_memory();
145 MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);
146 MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);
147 XlnxZynqMPIPI *ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];
148 qemu_irq irq[32];
149 int i;
150
151
152 memory_region_init_rom(pmu_rom, NULL, "xlnx-zynqmp-pmu.rom",
153 XLNX_ZYNQMP_PMU_ROM_SIZE, &error_fatal);
154 memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_ROM_ADDR,
155 pmu_rom);
156
157
158 memory_region_init_ram(pmu_ram, NULL, "xlnx-zynqmp-pmu.ram",
159 machine->ram_size, &error_fatal);
160 memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_RAM_ADDR,
161 pmu_ram);
162
163
164 object_initialize(pmu, sizeof(XlnxZynqMPPMUSoCState), TYPE_XLNX_ZYNQMP_PMU_SOC);
165 object_property_add_child(OBJECT(machine), "pmu", OBJECT(pmu),
166 &error_abort);
167 object_property_set_bool(OBJECT(pmu), true, "realized", &error_fatal);
168
169 for (i = 0; i < 32; i++) {
170 irq[i] = qdev_get_gpio_in(DEVICE(&pmu->intc), i);
171 }
172
173
174 for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
175 ipi[i] = g_new0(XlnxZynqMPIPI, 1);
176 object_initialize(ipi[i], sizeof(XlnxZynqMPIPI), TYPE_XLNX_ZYNQMP_IPI);
177 qdev_set_parent_bus(DEVICE(ipi[i]), sysbus_get_default());
178 }
179
180 for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
181 object_property_set_bool(OBJECT(ipi[i]), true, "realized",
182 &error_abort);
183 sysbus_mmio_map(SYS_BUS_DEVICE(ipi[i]), 0, ipi_addr[i]);
184 sysbus_connect_irq(SYS_BUS_DEVICE(ipi[i]), 0, irq[ipi_irq[i]]);
185 }
186
187
188 microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
189 machine->ram_size,
190 machine->initrd_filename,
191 machine->dtb,
192 NULL);
193}
194
195static void xlnx_zynqmp_pmu_machine_init(MachineClass *mc)
196{
197 mc->desc = "Xilinx ZynqMP PMU machine";
198 mc->init = xlnx_zynqmp_pmu_init;
199}
200
201DEFINE_MACHINE("xlnx-zynqmp-pmu", xlnx_zynqmp_pmu_machine_init)
202
203
