LXR qemu/hw/misc/exynos4210

   1/*
   2 *  Exynos4210 Clock Controller Emulation
   3 *
   4 *  Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
   5 *
   6 *  This program is free software; you can redistribute it and/or modify it
   7 *  under the terms of the GNU General Public License as published by the
   8 *  Free Software Foundation; either version 2 of the License, or
   9 *  (at your option) any later version.
  10 *
  11 *  This program is distributed in the hope that it will be useful, but WITHOUT
  12 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  14 *  for more details.
  15 *
  16 *  You should have received a copy of the GNU General Public License along
  17 *  with this program; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#include "qemu/osdep.h"
  21#include "hw/sysbus.h"
  22#include "qemu/log.h"
  23
  24#define TYPE_EXYNOS4210_CLK             "exynos4210.clk"
  25#define EXYNOS4210_CLK(obj) \
  26    OBJECT_CHECK(Exynos4210ClkState, (obj), TYPE_EXYNOS4210_CLK)
  27
  28#define CLK_PLL_LOCKED                  BIT(29)
  29
  30#define EXYNOS4210_CLK_REGS_MEM_SIZE    0x15104
  31
  32typedef struct Exynos4210Reg {
  33    const char   *name; /* for debug only */
  34    uint32_t     offset;
  35    uint32_t     reset_value;
  36} Exynos4210Reg;
  37
  38/* Clock controller register base: 0x10030000 */
  39static const Exynos4210Reg exynos4210_clk_regs[] = {
  40    {"EPLL_LOCK",                     0xc010, 0x00000fff},
  41    {"VPLL_LOCK",                     0xc020, 0x00000fff},
  42    {"EPLL_CON0",                     0xc110, 0x00300301 | CLK_PLL_LOCKED},
  43    {"EPLL_CON1",                     0xc114, 0x00000000},
  44    {"VPLL_CON0",                     0xc120, 0x00240201 | CLK_PLL_LOCKED},
  45    {"VPLL_CON1",                     0xc124, 0x66010464},
  46    {"APLL_LOCK",                    0x14000, 0x00000fff},
  47    {"MPLL_LOCK",                    0x14004, 0x00000fff},
  48    {"APLL_CON0",                    0x14100, 0x00c80601 | CLK_PLL_LOCKED},
  49    {"APLL_CON1",                    0x14104, 0x0000001c},
  50    {"MPLL_CON0",                    0x14108, 0x00c80601 | CLK_PLL_LOCKED},
  51    {"MPLL_CON1",                    0x1410c, 0x0000001c},
  52};
  53
  54#define EXYNOS4210_REGS_NUM       ARRAY_SIZE(exynos4210_clk_regs)
  55
  56typedef struct Exynos4210ClkState {
  57    SysBusDevice parent_obj;
  58
  59    MemoryRegion iomem;
  60    uint32_t reg[EXYNOS4210_REGS_NUM];
  61} Exynos4210ClkState;
  62
  63static uint64_t exynos4210_clk_read(void *opaque, hwaddr offset,
  64                                    unsigned size)
  65{
  66    const Exynos4210ClkState *s = (Exynos4210ClkState *)opaque;
  67    const Exynos4210Reg *regs = exynos4210_clk_regs;
  68    unsigned int i;
  69
  70    for (i = 0; i < EXYNOS4210_REGS_NUM; i++) {
  71        if (regs->offset == offset) {
  72            return s->reg[i];
  73        }
  74        regs++;
  75    }
  76    qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read offset 0x%04x\n",
  77                  __func__, (uint32_t)offset);
  78    return 0;
  79}
  80
  81static void exynos4210_clk_write(void *opaque, hwaddr offset,
  82                                 uint64_t val, unsigned size)
  83{
  84    Exynos4210ClkState *s = (Exynos4210ClkState *)opaque;
  85    const Exynos4210Reg *regs = exynos4210_clk_regs;
  86    unsigned int i;
  87
  88    for (i = 0; i < EXYNOS4210_REGS_NUM; i++) {
  89        if (regs->offset == offset) {
  90            s->reg[i] = val;
  91            return;
  92        }
  93        regs++;
  94    }
  95    qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write offset 0x%04x\n",
  96                  __func__, (uint32_t)offset);
  97}
  98
  99static const MemoryRegionOps exynos4210_clk_ops = {
 100    .read = exynos4210_clk_read,
 101    .write = exynos4210_clk_write,
 102    .endianness = DEVICE_NATIVE_ENDIAN,
 103    .valid = {
 104        .min_access_size = 4,
 105        .max_access_size = 4,
 106        .unaligned = false
 107    }
 108};
 109
 110static void exynos4210_clk_reset(DeviceState *dev)
 111{
 112    Exynos4210ClkState *s = EXYNOS4210_CLK(dev);
 113    unsigned int i;
 114
 115    /* Set default values for registers */
 116    for (i = 0; i < EXYNOS4210_REGS_NUM; i++) {
 117        s->reg[i] = exynos4210_clk_regs[i].reset_value;
 118    }
 119}
 120
 121static void exynos4210_clk_init(Object *obj)
 122{
 123    Exynos4210ClkState *s = EXYNOS4210_CLK(obj);
 124    SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 125
 126    /* memory mapping */
 127    memory_region_init_io(&s->iomem, obj, &exynos4210_clk_ops, s,
 128                          TYPE_EXYNOS4210_CLK, EXYNOS4210_CLK_REGS_MEM_SIZE);
 129    sysbus_init_mmio(dev, &s->iomem);
 130}
 131
 132static const VMStateDescription exynos4210_clk_vmstate = {
 133    .name = TYPE_EXYNOS4210_CLK,
 134    .version_id = 1,
 135    .minimum_version_id = 1,
 136    .fields = (VMStateField[]) {
 137        VMSTATE_UINT32_ARRAY(reg, Exynos4210ClkState, EXYNOS4210_REGS_NUM),
 138        VMSTATE_END_OF_LIST()
 139    }
 140};
 141
 142static void exynos4210_clk_class_init(ObjectClass *klass, void *data)
 143{
 144    DeviceClass *dc = DEVICE_CLASS(klass);
 145
 146    dc->reset = exynos4210_clk_reset;
 147    dc->vmsd = &exynos4210_clk_vmstate;
 148}
 149
 150static const TypeInfo exynos4210_clk_info = {
 151    .name          = TYPE_EXYNOS4210_CLK,
 152    .parent        = TYPE_SYS_BUS_DEVICE,
 153    .instance_size = sizeof(Exynos4210ClkState),
 154    .instance_init = exynos4210_clk_init,
 155    .class_init    = exynos4210_clk_class_init,
 156};
 157
 158static void exynos4210_clk_register(void)
 159{
 160    qemu_log_mask(LOG_GUEST_ERROR, "Clock init\n");
 161    type_register_static(&exynos4210_clk_info);
 162}
 163
 164type_init(exynos4210_clk_register)
 165