LXR qemu/hw/misc/mips

   1/*
   2 * Cluster Power Controller emulation
   3 *
   4 * Copyright (c) 2016 Imagination Technologies
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#include "qemu/osdep.h"
  21#include "qapi/error.h"
  22#include "cpu.h"
  23#include "qemu/log.h"
  24#include "hw/sysbus.h"
  25
  26#include "hw/misc/mips_cpc.h"
  27
  28static inline uint64_t cpc_vp_run_mask(MIPSCPCState *cpc)
  29{
  30    return (1ULL << cpc->num_vp) - 1;
  31}
  32
  33static void mips_cpu_reset_async_work(CPUState *cs, run_on_cpu_data data)
  34{
  35    MIPSCPCState *cpc = (MIPSCPCState *) data.host_ptr;
  36
  37    cpu_reset(cs);
  38    cpc->vp_running |= 1ULL << cs->cpu_index;
  39}
  40
  41static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)
  42{
  43    CPUState *cs = first_cpu;
  44
  45    CPU_FOREACH(cs) {
  46        uint64_t i = 1ULL << cs->cpu_index;
  47        if (i & vp_run & ~cpc->vp_running) {
  48            /*
  49             * To avoid racing with a CPU we are just kicking off.
  50             * We do the final bit of preparation for the work in
  51             * the target CPUs context.
  52             */
  53            async_safe_run_on_cpu(cs, mips_cpu_reset_async_work,
  54                                  RUN_ON_CPU_HOST_PTR(cpc));
  55        }
  56    }
  57}
  58
  59static void cpc_stop_vp(MIPSCPCState *cpc, uint64_t vp_stop)
  60{
  61    CPUState *cs = first_cpu;
  62
  63    CPU_FOREACH(cs) {
  64        uint64_t i = 1ULL << cs->cpu_index;
  65        if (i & vp_stop & cpc->vp_running) {
  66            cpu_interrupt(cs, CPU_INTERRUPT_HALT);
  67            cpc->vp_running &= ~i;
  68        }
  69    }
  70}
  71
  72static void cpc_write(void *opaque, hwaddr offset, uint64_t data,
  73                      unsigned size)
  74{
  75    MIPSCPCState *s = opaque;
  76
  77    switch (offset) {
  78    case CPC_CL_BASE_OFS + CPC_VP_RUN_OFS:
  79    case CPC_CO_BASE_OFS + CPC_VP_RUN_OFS:
  80        cpc_run_vp(s, data & cpc_vp_run_mask(s));
  81        break;
  82    case CPC_CL_BASE_OFS + CPC_VP_STOP_OFS:
  83    case CPC_CO_BASE_OFS + CPC_VP_STOP_OFS:
  84        cpc_stop_vp(s, data & cpc_vp_run_mask(s));
  85        break;
  86    default:
  87        qemu_log_mask(LOG_UNIMP,
  88                      "%s: Bad offset 0x%x\n",  __func__, (int)offset);
  89        break;
  90    }
  91
  92    return;
  93}
  94
  95static uint64_t cpc_read(void *opaque, hwaddr offset, unsigned size)
  96{
  97    MIPSCPCState *s = opaque;
  98
  99    switch (offset) {
 100    case CPC_CL_BASE_OFS + CPC_VP_RUNNING_OFS:
 101    case CPC_CO_BASE_OFS + CPC_VP_RUNNING_OFS:
 102        return s->vp_running;
 103    default:
 104        qemu_log_mask(LOG_UNIMP,
 105                      "%s: Bad offset 0x%x\n",  __func__, (int)offset);
 106        return 0;
 107    }
 108}
 109
 110static const MemoryRegionOps cpc_ops = {
 111    .read = cpc_read,
 112    .write = cpc_write,
 113    .endianness = DEVICE_NATIVE_ENDIAN,
 114    .impl = {
 115        .max_access_size = 8,
 116    },
 117};
 118
 119static void mips_cpc_init(Object *obj)
 120{
 121    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 122    MIPSCPCState *s = MIPS_CPC(obj);
 123
 124    memory_region_init_io(&s->mr, OBJECT(s), &cpc_ops, s, "mips-cpc",
 125                          CPC_ADDRSPACE_SZ);
 126    sysbus_init_mmio(sbd, &s->mr);
 127}
 128
 129static void mips_cpc_realize(DeviceState *dev, Error **errp)
 130{
 131    MIPSCPCState *s = MIPS_CPC(dev);
 132
 133    if (s->vp_start_running > cpc_vp_run_mask(s)) {
 134        error_setg(errp,
 135                   "incorrect vp_start_running 0x%" PRIx64 " for num_vp = %d",
 136                   s->vp_running, s->num_vp);
 137        return;
 138    }
 139}
 140
 141static void mips_cpc_reset(DeviceState *dev)
 142{
 143    MIPSCPCState *s = MIPS_CPC(dev);
 144
 145    /* Reflect the fact that all VPs are halted on reset */
 146    s->vp_running = 0;
 147
 148    /* Put selected VPs into run state */
 149    cpc_run_vp(s, s->vp_start_running);
 150}
 151
 152static const VMStateDescription vmstate_mips_cpc = {
 153    .name = "mips-cpc",
 154    .version_id = 0,
 155    .minimum_version_id = 0,
 156    .fields = (VMStateField[]) {
 157        VMSTATE_UINT64(vp_running, MIPSCPCState),
 158        VMSTATE_END_OF_LIST()
 159    },
 160};
 161
 162static Property mips_cpc_properties[] = {
 163    DEFINE_PROP_UINT32("num-vp", MIPSCPCState, num_vp, 0x1),
 164    DEFINE_PROP_UINT64("vp-start-running", MIPSCPCState, vp_start_running, 0x1),
 165    DEFINE_PROP_END_OF_LIST(),
 166};
 167
 168static void mips_cpc_class_init(ObjectClass *klass, void *data)
 169{
 170    DeviceClass *dc = DEVICE_CLASS(klass);
 171
 172    dc->realize = mips_cpc_realize;
 173    dc->reset = mips_cpc_reset;
 174    dc->vmsd = &vmstate_mips_cpc;
 175    dc->props = mips_cpc_properties;
 176}
 177
 178static const TypeInfo mips_cpc_info = {
 179    .name          = TYPE_MIPS_CPC,
 180    .parent        = TYPE_SYS_BUS_DEVICE,
 181    .instance_size = sizeof(MIPSCPCState),
 182    .instance_init = mips_cpc_init,
 183    .class_init    = mips_cpc_class_init,
 184};
 185
 186static void mips_cpc_register_types(void)
 187{
 188    type_register_static(&mips_cpc_info);
 189}
 190
 191type_init(mips_cpc_register_types)
 192