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20#include "qemu/osdep.h"
21#include "qemu/units.h"
22#include "qemu/log.h"
23#include "qapi/error.h"
24#include "cpu.h"
25#include "exec/exec-all.h"
26#include "hw/misc/mips_itu.h"
27
28#define ITC_TAG_ADDRSPACE_SZ (ITC_ADDRESSMAP_NUM * 8)
29
30
31#define ITC_STORAGE_ADDRSPACE_SZ 0x1000
32
33#define ITC_FIFO_NUM_MAX 16
34#define ITC_SEMAPH_NUM_MAX 16
35#define ITC_AM1_NUMENTRIES_OFS 20
36
37#define ITC_CELL_PV_MAX_VAL 0xFFFF
38
39#define ITC_CELL_TAG_FIFO_DEPTH 28
40#define ITC_CELL_TAG_FIFO_PTR 18
41#define ITC_CELL_TAG_FIFO 17
42#define ITC_CELL_TAG_T 16
43#define ITC_CELL_TAG_F 1
44#define ITC_CELL_TAG_E 0
45
46#define ITC_AM0_BASE_ADDRESS_MASK 0xFFFFFC00ULL
47#define ITC_AM0_EN_MASK 0x1
48
49#define ITC_AM1_ADDR_MASK_MASK 0x1FC00
50#define ITC_AM1_ENTRY_GRAIN_MASK 0x7
51
52typedef enum ITCView {
53 ITCVIEW_BYPASS = 0,
54 ITCVIEW_CONTROL = 1,
55 ITCVIEW_EF_SYNC = 2,
56 ITCVIEW_EF_TRY = 3,
57 ITCVIEW_PV_SYNC = 4,
58 ITCVIEW_PV_TRY = 5,
59 ITCVIEW_PV_ICR0 = 15,
60} ITCView;
61
62#define ITC_ICR0_CELL_NUM 16
63#define ITC_ICR0_BLK_GRAIN 8
64#define ITC_ICR0_BLK_GRAIN_MASK 0x7
65#define ITC_ICR0_ERR_AXI 2
66#define ITC_ICR0_ERR_PARITY 1
67#define ITC_ICR0_ERR_EXEC 0
68
69MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu)
70{
71 return &itu->tag_io;
72}
73
74static uint64_t itc_tag_read(void *opaque, hwaddr addr, unsigned size)
75{
76 MIPSITUState *tag = (MIPSITUState *)opaque;
77 uint64_t index = addr >> 3;
78
79 if (index >= ITC_ADDRESSMAP_NUM) {
80 qemu_log_mask(LOG_GUEST_ERROR, "Read 0x%" PRIx64 "\n", addr);
81 return 0;
82 }
83
84 return tag->ITCAddressMap[index];
85}
86
87void itc_reconfigure(MIPSITUState *tag)
88{
89 uint64_t *am = &tag->ITCAddressMap[0];
90 MemoryRegion *mr = &tag->storage_io;
91 hwaddr address = am[0] & ITC_AM0_BASE_ADDRESS_MASK;
92 uint64_t size = (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK);
93 bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0;
94
95 if (tag->saar_present) {
96 address = ((*(uint64_t *) tag->saar) & 0xFFFFFFFFE000ULL) << 4;
97 size = 1ULL << ((*(uint64_t *) tag->saar >> 1) & 0x1f);
98 is_enabled = *(uint64_t *) tag->saar & 1;
99 }
100
101 memory_region_transaction_begin();
102 if (!(size & (size - 1))) {
103 memory_region_set_size(mr, size);
104 }
105 memory_region_set_address(mr, address);
106 memory_region_set_enabled(mr, is_enabled);
107 memory_region_transaction_commit();
108}
109
110static void itc_tag_write(void *opaque, hwaddr addr,
111 uint64_t data, unsigned size)
112{
113 MIPSITUState *tag = (MIPSITUState *)opaque;
114 uint64_t *am = &tag->ITCAddressMap[0];
115 uint64_t am_old, mask;
116 uint64_t index = addr >> 3;
117
118 switch (index) {
119 case 0:
120 mask = ITC_AM0_BASE_ADDRESS_MASK | ITC_AM0_EN_MASK;
121 break;
122 case 1:
123 mask = ITC_AM1_ADDR_MASK_MASK | ITC_AM1_ENTRY_GRAIN_MASK;
124 break;
125 default:
126 qemu_log_mask(LOG_GUEST_ERROR, "Bad write 0x%" PRIx64 "\n", addr);
127 return;
128 }
129
130 am_old = am[index];
131 am[index] = (data & mask) | (am_old & ~mask);
132 if (am_old != am[index]) {
133 itc_reconfigure(tag);
134 }
135}
136
137static const MemoryRegionOps itc_tag_ops = {
138 .read = itc_tag_read,
139 .write = itc_tag_write,
140 .impl = {
141 .max_access_size = 8,
142 },
143 .endianness = DEVICE_NATIVE_ENDIAN,
144};
145
146static inline uint32_t get_num_cells(MIPSITUState *s)
147{
148 return s->num_fifo + s->num_semaphores;
149}
150
151static inline ITCView get_itc_view(hwaddr addr)
152{
153 return (addr >> 3) & 0xf;
154}
155
156static inline int get_cell_stride_shift(const MIPSITUState *s)
157{
158
159 if (s->saar_present) {
160 return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) &
161 ITC_ICR0_BLK_GRAIN_MASK);
162 } else {
163 return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK);
164 }
165}
166
167static inline ITCStorageCell *get_cell(MIPSITUState *s,
168 hwaddr addr)
169{
170 uint32_t cell_idx = addr >> get_cell_stride_shift(s);
171 uint32_t num_cells = get_num_cells(s);
172
173 if (cell_idx >= num_cells) {
174 cell_idx = num_cells - 1;
175 }
176
177 return &s->cell[cell_idx];
178}
179
180static void wake_blocked_threads(ITCStorageCell *c)
181{
182 CPUState *cs;
183 CPU_FOREACH(cs) {
184 if (cs->halted && (c->blocked_threads & (1ULL << cs->cpu_index))) {
185 cpu_interrupt(cs, CPU_INTERRUPT_WAKE);
186 }
187 }
188 c->blocked_threads = 0;
189}
190
191static void QEMU_NORETURN block_thread_and_exit(ITCStorageCell *c)
192{
193 c->blocked_threads |= 1ULL << current_cpu->cpu_index;
194 current_cpu->halted = 1;
195 current_cpu->exception_index = EXCP_HLT;
196 cpu_loop_exit_restore(current_cpu, current_cpu->mem_io_pc);
197}
198
199
200
201static inline uint64_t view_bypass_read(ITCStorageCell *c)
202{
203 if (c->tag.FIFO) {
204 return c->data[c->fifo_out];
205 } else {
206 return c->data[0];
207 }
208}
209
210static inline void view_bypass_write(ITCStorageCell *c, uint64_t val)
211{
212 if (c->tag.FIFO && (c->tag.FIFOPtr > 0)) {
213 int idx = (c->fifo_out + c->tag.FIFOPtr - 1) % ITC_CELL_DEPTH;
214 c->data[idx] = val;
215 }
216
217
218}
219
220
221
222static inline uint64_t view_control_read(ITCStorageCell *c)
223{
224 return ((uint64_t)c->tag.FIFODepth << ITC_CELL_TAG_FIFO_DEPTH) |
225 (c->tag.FIFOPtr << ITC_CELL_TAG_FIFO_PTR) |
226 (c->tag.FIFO << ITC_CELL_TAG_FIFO) |
227 (c->tag.T << ITC_CELL_TAG_T) |
228 (c->tag.E << ITC_CELL_TAG_E) |
229 (c->tag.F << ITC_CELL_TAG_F);
230}
231
232static inline void view_control_write(ITCStorageCell *c, uint64_t val)
233{
234 c->tag.T = (val >> ITC_CELL_TAG_T) & 1;
235 c->tag.E = (val >> ITC_CELL_TAG_E) & 1;
236 c->tag.F = (val >> ITC_CELL_TAG_F) & 1;
237
238 if (c->tag.E) {
239 c->tag.FIFOPtr = 0;
240 }
241}
242
243
244
245static uint64_t view_ef_common_read(ITCStorageCell *c, bool blocking)
246{
247 uint64_t ret = 0;
248
249 if (!c->tag.FIFO) {
250 return 0;
251 }
252
253 c->tag.F = 0;
254
255 if (blocking && c->tag.E) {
256 block_thread_and_exit(c);
257 }
258
259 if (c->blocked_threads) {
260 wake_blocked_threads(c);
261 }
262
263 if (c->tag.FIFOPtr > 0) {
264 ret = c->data[c->fifo_out];
265 c->fifo_out = (c->fifo_out + 1) % ITC_CELL_DEPTH;
266 c->tag.FIFOPtr--;
267 }
268
269 if (c->tag.FIFOPtr == 0) {
270 c->tag.E = 1;
271 }
272
273 return ret;
274}
275
276static uint64_t view_ef_sync_read(ITCStorageCell *c)
277{
278 return view_ef_common_read(c, true);
279}
280
281static uint64_t view_ef_try_read(ITCStorageCell *c)
282{
283 return view_ef_common_read(c, false);
284}
285
286static inline void view_ef_common_write(ITCStorageCell *c, uint64_t val,
287 bool blocking)
288{
289 if (!c->tag.FIFO) {
290 return;
291 }
292
293 c->tag.E = 0;
294
295 if (blocking && c->tag.F) {
296 block_thread_and_exit(c);
297 }
298
299 if (c->blocked_threads) {
300 wake_blocked_threads(c);
301 }
302
303 if (c->tag.FIFOPtr < ITC_CELL_DEPTH) {
304 int idx = (c->fifo_out + c->tag.FIFOPtr) % ITC_CELL_DEPTH;
305 c->data[idx] = val;
306 c->tag.FIFOPtr++;
307 }
308
309 if (c->tag.FIFOPtr == ITC_CELL_DEPTH) {
310 c->tag.F = 1;
311 }
312}
313
314static void view_ef_sync_write(ITCStorageCell *c, uint64_t val)
315{
316 view_ef_common_write(c, val, true);
317}
318
319static void view_ef_try_write(ITCStorageCell *c, uint64_t val)
320{
321 view_ef_common_write(c, val, false);
322}
323
324
325
326static uint64_t view_pv_common_read(ITCStorageCell *c, bool blocking)
327{
328 uint64_t ret = c->data[0];
329
330 if (c->tag.FIFO) {
331 return 0;
332 }
333
334 if (c->data[0] > 0) {
335 c->data[0]--;
336 } else if (blocking) {
337 block_thread_and_exit(c);
338 }
339
340 return ret;
341}
342
343static uint64_t view_pv_sync_read(ITCStorageCell *c)
344{
345 return view_pv_common_read(c, true);
346}
347
348static uint64_t view_pv_try_read(ITCStorageCell *c)
349{
350 return view_pv_common_read(c, false);
351}
352
353static inline void view_pv_common_write(ITCStorageCell *c)
354{
355 if (c->tag.FIFO) {
356 return;
357 }
358
359 if (c->data[0] < ITC_CELL_PV_MAX_VAL) {
360 c->data[0]++;
361 }
362
363 if (c->blocked_threads) {
364 wake_blocked_threads(c);
365 }
366}
367
368static void view_pv_sync_write(ITCStorageCell *c)
369{
370 view_pv_common_write(c);
371}
372
373static void view_pv_try_write(ITCStorageCell *c)
374{
375 view_pv_common_write(c);
376}
377
378static void raise_exception(int excp)
379{
380 current_cpu->exception_index = excp;
381 cpu_loop_exit(current_cpu);
382}
383
384static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
385{
386 MIPSITUState *s = (MIPSITUState *)opaque;
387 ITCStorageCell *cell = get_cell(s, addr);
388 ITCView view = get_itc_view(addr);
389 uint64_t ret = -1;
390
391 switch (size) {
392 case 1:
393 case 2:
394 s->icr0 |= 1 << ITC_ICR0_ERR_AXI;
395 raise_exception(EXCP_DBE);
396 return 0;
397 }
398
399 switch (view) {
400 case ITCVIEW_BYPASS:
401 ret = view_bypass_read(cell);
402 break;
403 case ITCVIEW_CONTROL:
404 ret = view_control_read(cell);
405 break;
406 case ITCVIEW_EF_SYNC:
407 ret = view_ef_sync_read(cell);
408 break;
409 case ITCVIEW_EF_TRY:
410 ret = view_ef_try_read(cell);
411 break;
412 case ITCVIEW_PV_SYNC:
413 ret = view_pv_sync_read(cell);
414 break;
415 case ITCVIEW_PV_TRY:
416 ret = view_pv_try_read(cell);
417 break;
418 case ITCVIEW_PV_ICR0:
419 ret = s->icr0;
420 break;
421 default:
422 qemu_log_mask(LOG_GUEST_ERROR,
423 "itc_storage_read: Bad ITC View %d\n", (int)view);
424 break;
425 }
426
427 return ret;
428}
429
430static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data,
431 unsigned size)
432{
433 MIPSITUState *s = (MIPSITUState *)opaque;
434 ITCStorageCell *cell = get_cell(s, addr);
435 ITCView view = get_itc_view(addr);
436
437 switch (size) {
438 case 1:
439 case 2:
440 s->icr0 |= 1 << ITC_ICR0_ERR_AXI;
441 raise_exception(EXCP_DBE);
442 return;
443 }
444
445 switch (view) {
446 case ITCVIEW_BYPASS:
447 view_bypass_write(cell, data);
448 break;
449 case ITCVIEW_CONTROL:
450 view_control_write(cell, data);
451 break;
452 case ITCVIEW_EF_SYNC:
453 view_ef_sync_write(cell, data);
454 break;
455 case ITCVIEW_EF_TRY:
456 view_ef_try_write(cell, data);
457 break;
458 case ITCVIEW_PV_SYNC:
459 view_pv_sync_write(cell);
460 break;
461 case ITCVIEW_PV_TRY:
462 view_pv_try_write(cell);
463 break;
464 case ITCVIEW_PV_ICR0:
465 if (data & 0x7) {
466
467 s->icr0 &= ~(data & 0x7);
468 }
469
470 s->icr0 &= ~0x700;
471 s->icr0 |= data & 0x700;
472 break;
473 default:
474 qemu_log_mask(LOG_GUEST_ERROR,
475 "itc_storage_write: Bad ITC View %d\n", (int)view);
476 break;
477 }
478
479}
480
481static const MemoryRegionOps itc_storage_ops = {
482 .read = itc_storage_read,
483 .write = itc_storage_write,
484 .endianness = DEVICE_NATIVE_ENDIAN,
485};
486
487static void itc_reset_cells(MIPSITUState *s)
488{
489 int i;
490
491 memset(s->cell, 0, get_num_cells(s) * sizeof(s->cell[0]));
492
493 for (i = 0; i < s->num_fifo; i++) {
494 s->cell[i].tag.E = 1;
495 s->cell[i].tag.FIFO = 1;
496 s->cell[i].tag.FIFODepth = ITC_CELL_DEPTH_SHIFT;
497 }
498}
499
500static void mips_itu_init(Object *obj)
501{
502 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
503 MIPSITUState *s = MIPS_ITU(obj);
504
505 memory_region_init_io(&s->storage_io, OBJECT(s), &itc_storage_ops, s,
506 "mips-itc-storage", ITC_STORAGE_ADDRSPACE_SZ);
507 sysbus_init_mmio(sbd, &s->storage_io);
508
509 memory_region_init_io(&s->tag_io, OBJECT(s), &itc_tag_ops, s,
510 "mips-itc-tag", ITC_TAG_ADDRSPACE_SZ);
511}
512
513static void mips_itu_realize(DeviceState *dev, Error **errp)
514{
515 MIPSITUState *s = MIPS_ITU(dev);
516
517 if (s->num_fifo > ITC_FIFO_NUM_MAX) {
518 error_setg(errp, "Exceed maximum number of FIFO cells: %d",
519 s->num_fifo);
520 return;
521 }
522 if (s->num_semaphores > ITC_SEMAPH_NUM_MAX) {
523 error_setg(errp, "Exceed maximum number of Semaphore cells: %d",
524 s->num_semaphores);
525 return;
526 }
527
528 s->cell = g_new(ITCStorageCell, get_num_cells(s));
529}
530
531static void mips_itu_reset(DeviceState *dev)
532{
533 MIPSITUState *s = MIPS_ITU(dev);
534
535 if (s->saar_present) {
536 *(uint64_t *) s->saar = 0x11 << 1;
537 s->icr0 = get_num_cells(s) << ITC_ICR0_CELL_NUM;
538 } else {
539 s->ITCAddressMap[0] = 0;
540 s->ITCAddressMap[1] =
541 ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) |
542 (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS);
543 }
544 itc_reconfigure(s);
545
546 itc_reset_cells(s);
547}
548
549static Property mips_itu_properties[] = {
550 DEFINE_PROP_INT32("num-fifo", MIPSITUState, num_fifo,
551 ITC_FIFO_NUM_MAX),
552 DEFINE_PROP_INT32("num-semaphores", MIPSITUState, num_semaphores,
553 ITC_SEMAPH_NUM_MAX),
554 DEFINE_PROP_BOOL("saar-present", MIPSITUState, saar_present, false),
555 DEFINE_PROP_END_OF_LIST(),
556};
557
558static void mips_itu_class_init(ObjectClass *klass, void *data)
559{
560 DeviceClass *dc = DEVICE_CLASS(klass);
561
562 dc->props = mips_itu_properties;
563 dc->realize = mips_itu_realize;
564 dc->reset = mips_itu_reset;
565}
566
567static const TypeInfo mips_itu_info = {
568 .name = TYPE_MIPS_ITU,
569 .parent = TYPE_SYS_BUS_DEVICE,
570 .instance_size = sizeof(MIPSITUState),
571 .instance_init = mips_itu_init,
572 .class_init = mips_itu_class_init,
573};
574
575static void mips_itu_register_types(void)
576{
577 type_register_static(&mips_itu_info);
578}
579
580type_init(mips_itu_register_types)
581
