LXR qemu/hw/misc/mps2-scc.c

   1/*
   2 * ARM MPS2 SCC emulation
   3 *
   4 * Copyright (c) 2017 Linaro Limited
   5 * Written by Peter Maydell
   6 *
   7 *  This program is free software; you can redistribute it and/or modify
   8 *  it under the terms of the GNU General Public License version 2 or
   9 *  (at your option) any later version.
  10 */
  11
  12/* This is a model of the SCC (Serial Communication Controller)
  13 * found in the FPGA images of MPS2 development boards.
  14 *
  15 * Documentation of it can be found in the MPS2 TRM:
  16 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100112_0100_03_en/index.html
  17 * and also in the Application Notes documenting individual FPGA images.
  18 */
  19
  20#include "qemu/osdep.h"
  21#include "qemu/log.h"
  22#include "trace.h"
  23#include "hw/sysbus.h"
  24#include "hw/registerfields.h"
  25#include "hw/misc/mps2-scc.h"
  26
  27REG32(CFG0, 0)
  28REG32(CFG1, 4)
  29REG32(CFG3, 0xc)
  30REG32(CFG4, 0x10)
  31REG32(CFGDATA_RTN, 0xa0)
  32REG32(CFGDATA_OUT, 0xa4)
  33REG32(CFGCTRL, 0xa8)
  34    FIELD(CFGCTRL, DEVICE, 0, 12)
  35    FIELD(CFGCTRL, RES1, 12, 8)
  36    FIELD(CFGCTRL, FUNCTION, 20, 6)
  37    FIELD(CFGCTRL, RES2, 26, 4)
  38    FIELD(CFGCTRL, WRITE, 30, 1)
  39    FIELD(CFGCTRL, START, 31, 1)
  40REG32(CFGSTAT, 0xac)
  41    FIELD(CFGSTAT, DONE, 0, 1)
  42    FIELD(CFGSTAT, ERROR, 1, 1)
  43REG32(DLL, 0x100)
  44REG32(AID, 0xFF8)
  45REG32(ID, 0xFFC)
  46
  47/* Handle a write via the SYS_CFG channel to the specified function/device.
  48 * Return false on error (reported to guest via SYS_CFGCTRL ERROR bit).
  49 */
  50static bool scc_cfg_write(MPS2SCC *s, unsigned function,
  51                          unsigned device, uint32_t value)
  52{
  53    trace_mps2_scc_cfg_write(function, device, value);
  54
  55    if (function != 1 || device >= NUM_OSCCLK) {
  56        qemu_log_mask(LOG_GUEST_ERROR,
  57                      "MPS2 SCC config write: bad function %d device %d\n",
  58                      function, device);
  59        return false;
  60    }
  61
  62    s->oscclk[device] = value;
  63    return true;
  64}
  65
  66/* Handle a read via the SYS_CFG channel to the specified function/device.
  67 * Return false on error (reported to guest via SYS_CFGCTRL ERROR bit),
  68 * or set *value on success.
  69 */
  70static bool scc_cfg_read(MPS2SCC *s, unsigned function,
  71                         unsigned device, uint32_t *value)
  72{
  73    if (function != 1 || device >= NUM_OSCCLK) {
  74        qemu_log_mask(LOG_GUEST_ERROR,
  75                      "MPS2 SCC config read: bad function %d device %d\n",
  76                      function, device);
  77        return false;
  78    }
  79
  80    *value = s->oscclk[device];
  81
  82    trace_mps2_scc_cfg_read(function, device, *value);
  83    return true;
  84}
  85
  86static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
  87{
  88    MPS2SCC *s = MPS2_SCC(opaque);
  89    uint64_t r;
  90
  91    switch (offset) {
  92    case A_CFG0:
  93        r = s->cfg0;
  94        break;
  95    case A_CFG1:
  96        r = s->cfg1;
  97        break;
  98    case A_CFG3:
  99        /* These are user-settable DIP switches on the board. We don't
 100         * model that, so just return zeroes.
 101         */
 102        r = 0;
 103        break;
 104    case A_CFG4:
 105        r = s->cfg4;
 106        break;
 107    case A_CFGDATA_RTN:
 108        r = s->cfgdata_rtn;
 109        break;
 110    case A_CFGDATA_OUT:
 111        r = s->cfgdata_out;
 112        break;
 113    case A_CFGCTRL:
 114        r = s->cfgctrl;
 115        break;
 116    case A_CFGSTAT:
 117        r = s->cfgstat;
 118        break;
 119    case A_DLL:
 120        r = s->dll;
 121        break;
 122    case A_AID:
 123        r = s->aid;
 124        break;
 125    case A_ID:
 126        r = s->id;
 127        break;
 128    default:
 129        qemu_log_mask(LOG_GUEST_ERROR,
 130                      "MPS2 SCC read: bad offset %x\n", (int) offset);
 131        r = 0;
 132        break;
 133    }
 134
 135    trace_mps2_scc_read(offset, r, size);
 136    return r;
 137}
 138
 139static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
 140                           unsigned size)
 141{
 142    MPS2SCC *s = MPS2_SCC(opaque);
 143
 144    trace_mps2_scc_write(offset, value, size);
 145
 146    switch (offset) {
 147    case A_CFG0:
 148        /* TODO on some boards bit 0 controls RAM remapping */
 149        s->cfg0 = value;
 150        break;
 151    case A_CFG1:
 152        /* CFG1 bits [7:0] control the board LEDs. We don't currently have
 153         * a mechanism for displaying this graphically, so use a trace event.
 154         */
 155        trace_mps2_scc_leds(value & 0x80 ? '*' : '.',
 156                            value & 0x40 ? '*' : '.',
 157                            value & 0x20 ? '*' : '.',
 158                            value & 0x10 ? '*' : '.',
 159                            value & 0x08 ? '*' : '.',
 160                            value & 0x04 ? '*' : '.',
 161                            value & 0x02 ? '*' : '.',
 162                            value & 0x01 ? '*' : '.');
 163        s->cfg1 = value;
 164        break;
 165    case A_CFGDATA_OUT:
 166        s->cfgdata_out = value;
 167        break;
 168    case A_CFGCTRL:
 169        /* Writing to CFGCTRL clears SYS_CFGSTAT */
 170        s->cfgstat = 0;
 171        s->cfgctrl = value & ~(R_CFGCTRL_RES1_MASK |
 172                               R_CFGCTRL_RES2_MASK |
 173                               R_CFGCTRL_START_MASK);
 174
 175        if (value & R_CFGCTRL_START_MASK) {
 176            /* Start bit set -- do a read or write (instantaneously) */
 177            int device = extract32(s->cfgctrl, R_CFGCTRL_DEVICE_SHIFT,
 178                                   R_CFGCTRL_DEVICE_LENGTH);
 179            int function = extract32(s->cfgctrl, R_CFGCTRL_FUNCTION_SHIFT,
 180                                     R_CFGCTRL_FUNCTION_LENGTH);
 181
 182            s->cfgstat = R_CFGSTAT_DONE_MASK;
 183            if (s->cfgctrl & R_CFGCTRL_WRITE_MASK) {
 184                if (!scc_cfg_write(s, function, device, s->cfgdata_out)) {
 185                    s->cfgstat |= R_CFGSTAT_ERROR_MASK;
 186                }
 187            } else {
 188                uint32_t result;
 189                if (!scc_cfg_read(s, function, device, &result)) {
 190                    s->cfgstat |= R_CFGSTAT_ERROR_MASK;
 191                } else {
 192                    s->cfgdata_rtn = result;
 193                }
 194            }
 195        }
 196        break;
 197    case A_DLL:
 198        /* DLL stands for Digital Locked Loop.
 199         * Bits [31:24] (DLL_LOCK_MASK) are writable, and indicate a
 200         * mask of which of the DLL_LOCKED bits [16:23] should be ORed
 201         * together to determine the ALL_UNMASKED_DLLS_LOCKED bit [0].
 202         * For QEMU, our DLLs are always locked, so we can leave bit 0
 203         * as 1 always and don't need to recalculate it.
 204         */
 205        s->dll = deposit32(s->dll, 24, 8, extract32(value, 24, 8));
 206        break;
 207    default:
 208        qemu_log_mask(LOG_GUEST_ERROR,
 209                      "MPS2 SCC write: bad offset 0x%x\n", (int) offset);
 210        break;
 211    }
 212}
 213
 214static const MemoryRegionOps mps2_scc_ops = {
 215    .read = mps2_scc_read,
 216    .write = mps2_scc_write,
 217    .endianness = DEVICE_LITTLE_ENDIAN,
 218};
 219
 220static void mps2_scc_reset(DeviceState *dev)
 221{
 222    MPS2SCC *s = MPS2_SCC(dev);
 223    int i;
 224
 225    trace_mps2_scc_reset();
 226    s->cfg0 = 0;
 227    s->cfg1 = 0;
 228    s->cfgdata_rtn = 0;
 229    s->cfgdata_out = 0;
 230    s->cfgctrl = 0x100000;
 231    s->cfgstat = 0;
 232    s->dll = 0xffff0001;
 233    for (i = 0; i < NUM_OSCCLK; i++) {
 234        s->oscclk[i] = s->oscclk_reset[i];
 235    }
 236}
 237
 238static void mps2_scc_init(Object *obj)
 239{
 240    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 241    MPS2SCC *s = MPS2_SCC(obj);
 242
 243    memory_region_init_io(&s->iomem, obj, &mps2_scc_ops, s, "mps2-scc", 0x1000);
 244    sysbus_init_mmio(sbd, &s->iomem);
 245}
 246
 247static void mps2_scc_realize(DeviceState *dev, Error **errp)
 248{
 249}
 250
 251static const VMStateDescription mps2_scc_vmstate = {
 252    .name = "mps2-scc",
 253    .version_id = 1,
 254    .minimum_version_id = 1,
 255    .fields = (VMStateField[]) {
 256        VMSTATE_UINT32(cfg0, MPS2SCC),
 257        VMSTATE_UINT32(cfg1, MPS2SCC),
 258        VMSTATE_UINT32(cfgdata_rtn, MPS2SCC),
 259        VMSTATE_UINT32(cfgdata_out, MPS2SCC),
 260        VMSTATE_UINT32(cfgctrl, MPS2SCC),
 261        VMSTATE_UINT32(cfgstat, MPS2SCC),
 262        VMSTATE_UINT32(dll, MPS2SCC),
 263        VMSTATE_UINT32_ARRAY(oscclk, MPS2SCC, NUM_OSCCLK),
 264        VMSTATE_END_OF_LIST()
 265    }
 266};
 267
 268static Property mps2_scc_properties[] = {
 269    /* Values for various read-only ID registers (which are specific
 270     * to the board model or FPGA image)
 271     */
 272    DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0),
 273    DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0),
 274    DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0),
 275    /* These are the initial settings for the source clocks on the board.
 276     * In hardware they can be configured via a config file read by the
 277     * motherboard configuration controller to suit the FPGA image.
 278     * These default values are used by most of the standard FPGA images.
 279     */
 280    DEFINE_PROP_UINT32("oscclk0", MPS2SCC, oscclk_reset[0], 50000000),
 281    DEFINE_PROP_UINT32("oscclk1", MPS2SCC, oscclk_reset[1], 24576000),
 282    DEFINE_PROP_UINT32("oscclk2", MPS2SCC, oscclk_reset[2], 25000000),
 283    DEFINE_PROP_END_OF_LIST(),
 284};
 285
 286static void mps2_scc_class_init(ObjectClass *klass, void *data)
 287{
 288    DeviceClass *dc = DEVICE_CLASS(klass);
 289
 290    dc->realize = mps2_scc_realize;
 291    dc->vmsd = &mps2_scc_vmstate;
 292    dc->reset = mps2_scc_reset;
 293    dc->props = mps2_scc_properties;
 294}
 295
 296static const TypeInfo mps2_scc_info = {
 297    .name = TYPE_MPS2_SCC,
 298    .parent = TYPE_SYS_BUS_DEVICE,
 299    .instance_size = sizeof(MPS2SCC),
 300    .instance_init = mps2_scc_init,
 301    .class_init = mps2_scc_class_init,
 302};
 303
 304static void mps2_scc_register_types(void)
 305{
 306    type_register_static(&mps2_scc_info);
 307}
 308
 309type_init(mps2_scc_register_types);
 310