LXR qemu/hw/openrisc/openrisc

   1/*
   2 * OpenRISC simulator for use as an IIS.
   3 *
   4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
   5 *                         Feng Gao <gf91597@gmail.com>
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * Lesser General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "qemu/error-report.h"
  23#include "qapi/error.h"
  24#include "qemu-common.h"
  25#include "cpu.h"
  26#include "hw/hw.h"
  27#include "hw/boards.h"
  28#include "elf.h"
  29#include "hw/char/serial.h"
  30#include "net/net.h"
  31#include "hw/loader.h"
  32#include "exec/address-spaces.h"
  33#include "sysemu/sysemu.h"
  34#include "hw/sysbus.h"
  35#include "sysemu/qtest.h"
  36
  37#define KERNEL_LOAD_ADDR 0x100
  38
  39static struct openrisc_boot_info {
  40    uint32_t bootstrap_pc;
  41} boot_info;
  42
  43static void main_cpu_reset(void *opaque)
  44{
  45    OpenRISCCPU *cpu = opaque;
  46    CPUState *cs = CPU(cpu);
  47
  48    cpu_reset(CPU(cpu));
  49
  50    cpu_set_pc(cs, boot_info.bootstrap_pc);
  51}
  52
  53static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors,
  54                                  int num_cpus, qemu_irq **cpu_irqs,
  55                                  int irq_pin, NICInfo *nd)
  56{
  57    DeviceState *dev;
  58    SysBusDevice *s;
  59    int i;
  60
  61    dev = qdev_create(NULL, "open_eth");
  62    qdev_set_nic_properties(dev, nd);
  63    qdev_init_nofail(dev);
  64
  65    s = SYS_BUS_DEVICE(dev);
  66    for (i = 0; i < num_cpus; i++) {
  67        sysbus_connect_irq(s, 0, cpu_irqs[i][irq_pin]);
  68    }
  69    sysbus_mmio_map(s, 0, base);
  70    sysbus_mmio_map(s, 1, descriptors);
  71}
  72
  73static void openrisc_sim_ompic_init(hwaddr base, int num_cpus,
  74                                    qemu_irq **cpu_irqs, int irq_pin)
  75{
  76    DeviceState *dev;
  77    SysBusDevice *s;
  78    int i;
  79
  80    dev = qdev_create(NULL, "or1k-ompic");
  81    qdev_prop_set_uint32(dev, "num-cpus", num_cpus);
  82    qdev_init_nofail(dev);
  83
  84    s = SYS_BUS_DEVICE(dev);
  85    for (i = 0; i < num_cpus; i++) {
  86        sysbus_connect_irq(s, i, cpu_irqs[i][irq_pin]);
  87    }
  88    sysbus_mmio_map(s, 0, base);
  89}
  90
  91static void openrisc_load_kernel(ram_addr_t ram_size,
  92                                 const char *kernel_filename)
  93{
  94    long kernel_size;
  95    uint64_t elf_entry;
  96    hwaddr entry;
  97
  98    if (kernel_filename && !qtest_enabled()) {
  99        kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
 100                               &elf_entry, NULL, NULL, 1, EM_OPENRISC,
 101                               1, 0);
 102        entry = elf_entry;
 103        if (kernel_size < 0) {
 104            kernel_size = load_uimage(kernel_filename,
 105                                      &entry, NULL, NULL, NULL, NULL);
 106        }
 107        if (kernel_size < 0) {
 108            kernel_size = load_image_targphys(kernel_filename,
 109                                              KERNEL_LOAD_ADDR,
 110                                              ram_size - KERNEL_LOAD_ADDR);
 111        }
 112
 113        if (entry <= 0) {
 114            entry = KERNEL_LOAD_ADDR;
 115        }
 116
 117        if (kernel_size < 0) {
 118            error_report("couldn't load the kernel '%s'", kernel_filename);
 119            exit(1);
 120        }
 121        boot_info.bootstrap_pc = entry;
 122    }
 123}
 124
 125static void openrisc_sim_init(MachineState *machine)
 126{
 127    ram_addr_t ram_size = machine->ram_size;
 128    const char *kernel_filename = machine->kernel_filename;
 129    OpenRISCCPU *cpu = NULL;
 130    MemoryRegion *ram;
 131    qemu_irq *cpu_irqs[2];
 132    qemu_irq serial_irq;
 133    int n;
 134
 135    for (n = 0; n < smp_cpus; n++) {
 136        cpu = OPENRISC_CPU(cpu_create(machine->cpu_type));
 137        if (cpu == NULL) {
 138            fprintf(stderr, "Unable to find CPU definition!\n");
 139            exit(1);
 140        }
 141        cpu_openrisc_pic_init(cpu);
 142        cpu_irqs[n] = (qemu_irq *) cpu->env.irq;
 143
 144        cpu_openrisc_clock_init(cpu);
 145
 146        qemu_register_reset(main_cpu_reset, cpu);
 147    }
 148
 149    ram = g_malloc(sizeof(*ram));
 150    memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal);
 151    memory_region_add_subregion(get_system_memory(), 0, ram);
 152
 153    if (nd_table[0].used) {
 154        openrisc_sim_net_init(0x92000000, 0x92000400, smp_cpus,
 155                              cpu_irqs, 4, nd_table);
 156    }
 157
 158    if (smp_cpus > 1) {
 159        openrisc_sim_ompic_init(0x98000000, smp_cpus, cpu_irqs, 1);
 160
 161        serial_irq = qemu_irq_split(cpu_irqs[0][2], cpu_irqs[1][2]);
 162    } else {
 163        serial_irq = cpu_irqs[0][2];
 164    }
 165
 166    serial_mm_init(get_system_memory(), 0x90000000, 0, serial_irq,
 167                   115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
 168
 169    openrisc_load_kernel(ram_size, kernel_filename);
 170}
 171
 172static void openrisc_sim_machine_init(MachineClass *mc)
 173{
 174    mc->desc = "or1k simulation";
 175    mc->init = openrisc_sim_init;
 176    mc->max_cpus = 2;
 177    mc->is_default = 1;
 178    mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200");
 179}
 180
 181DEFINE_MACHINE("or1k-sim", openrisc_sim_machine_init)
 182