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25#include "qemu/osdep.h"
26#include "qemu/units.h"
27#include "cpu.h"
28#include "hw/sysbus.h"
29#include "hw/hw.h"
30#include "hw/char/serial.h"
31#include "hw/block/flash.h"
32#include "sysemu/sysemu.h"
33#include "sysemu/qtest.h"
34#include "hw/boards.h"
35#include "sysemu/device_tree.h"
36#include "hw/loader.h"
37#include "elf.h"
38#include "qemu/error-report.h"
39#include "qemu/log.h"
40#include "qemu/option.h"
41#include "exec/address-spaces.h"
42
43#include "hw/ppc/ppc.h"
44#include "hw/ppc/ppc4xx.h"
45#include "ppc405.h"
46
47#define EPAPR_MAGIC (0x45504150)
48#define FLASH_SIZE (16 * MiB)
49
50#define INTC_BASEADDR 0x81800000
51#define UART16550_BASEADDR 0x83e01003
52#define TIMER_BASEADDR 0x83c00000
53#define PFLASH_BASEADDR 0xfc000000
54
55#define TIMER_IRQ 3
56#define UART16550_IRQ 9
57
58static struct boot_info
59{
60 uint32_t bootstrap_pc;
61 uint32_t cmdline;
62 uint32_t fdt;
63 uint32_t ima_size;
64 void *vfdt;
65} boot_info;
66
67
68static void mmubooke_create_initial_mapping(CPUPPCState *env,
69 target_ulong va,
70 hwaddr pa)
71{
72 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
73
74 tlb->attr = 0;
75 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
76 tlb->size = 1U << 31;
77 tlb->EPN = va & TARGET_PAGE_MASK;
78 tlb->RPN = pa & TARGET_PAGE_MASK;
79 tlb->PID = 0;
80
81 tlb = &env->tlb.tlbe[1];
82 tlb->attr = 0;
83 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
84 tlb->size = 1U << 31;
85 tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
86 tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
87 tlb->PID = 0;
88}
89
90static PowerPCCPU *ppc440_init_xilinx(ram_addr_t *ram_size,
91 int do_init,
92 const char *cpu_type,
93 uint32_t sysclk)
94{
95 PowerPCCPU *cpu;
96 CPUPPCState *env;
97 qemu_irq *irqs;
98
99 cpu = POWERPC_CPU(cpu_create(cpu_type));
100 env = &cpu->env;
101
102 ppc_booke_timers_init(cpu, sysclk, 0);
103
104 ppc_dcr_init(env, NULL, NULL);
105
106
107 irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB);
108 irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
109 irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
110 ppcuic_init(env, irqs, 0x0C0, 0, 1);
111 return cpu;
112}
113
114static void main_cpu_reset(void *opaque)
115{
116 PowerPCCPU *cpu = opaque;
117 CPUPPCState *env = &cpu->env;
118 struct boot_info *bi = env->load_info;
119
120 cpu_reset(CPU(cpu));
121
122
123
124
125
126
127
128
129
130 env->gpr[1] = (16 * MiB) - 8;
131
132 env->gpr[3] = bi->fdt;
133 env->nip = bi->bootstrap_pc;
134
135
136 mmubooke_create_initial_mapping(env, 0, 0);
137 env->gpr[6] = tswap32(EPAPR_MAGIC);
138 env->gpr[7] = bi->ima_size;
139}
140
141#define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb"
142static int xilinx_load_device_tree(hwaddr addr,
143 uint32_t ramsize,
144 hwaddr initrd_base,
145 hwaddr initrd_size,
146 const char *kernel_cmdline)
147{
148 char *path;
149 int fdt_size;
150 void *fdt = NULL;
151 int r;
152 const char *dtb_filename;
153
154 dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
155 if (dtb_filename) {
156 fdt = load_device_tree(dtb_filename, &fdt_size);
157 if (!fdt) {
158 error_report("Error while loading device tree file '%s'",
159 dtb_filename);
160 }
161 } else {
162
163 fdt = load_device_tree("ppc.dtb", &fdt_size);
164 if (!fdt) {
165 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
166 if (path) {
167 fdt = load_device_tree(path, &fdt_size);
168 g_free(path);
169 }
170 }
171 }
172 if (!fdt) {
173 return 0;
174 }
175
176 r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
177 initrd_base);
178 if (r < 0) {
179 error_report("couldn't set /chosen/linux,initrd-start");
180 }
181
182 r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
183 (initrd_base + initrd_size));
184 if (r < 0) {
185 error_report("couldn't set /chosen/linux,initrd-end");
186 }
187
188 r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
189 if (r < 0)
190 fprintf(stderr, "couldn't set /chosen/bootargs\n");
191 cpu_physical_memory_write(addr, fdt, fdt_size);
192 return fdt_size;
193}
194
195static void virtex_init(MachineState *machine)
196{
197 ram_addr_t ram_size = machine->ram_size;
198 const char *kernel_filename = machine->kernel_filename;
199 const char *kernel_cmdline = machine->kernel_cmdline;
200 hwaddr initrd_base = 0;
201 int initrd_size = 0;
202 MemoryRegion *address_space_mem = get_system_memory();
203 DeviceState *dev;
204 PowerPCCPU *cpu;
205 CPUPPCState *env;
206 hwaddr ram_base = 0;
207 DriveInfo *dinfo;
208 MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
209 qemu_irq irq[32], *cpu_irq;
210 int kernel_size;
211 int i;
212
213
214 cpu = ppc440_init_xilinx(&ram_size, 1, machine->cpu_type, 400000000);
215 env = &cpu->env;
216
217 if (env->mmu_model != POWERPC_MMU_BOOKE) {
218 error_report("MMU model %i not supported by this machine",
219 env->mmu_model);
220 exit(1);
221 }
222
223 qemu_register_reset(main_cpu_reset, cpu);
224
225 memory_region_allocate_system_memory(phys_ram, NULL, "ram", ram_size);
226 memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
227
228 dinfo = drive_get(IF_PFLASH, 0, 0);
229 pflash_cfi01_register(PFLASH_BASEADDR, "virtex.flash", FLASH_SIZE,
230 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
231 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1);
232
233 cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
234 dev = qdev_create(NULL, "xlnx.xps-intc");
235 qdev_prop_set_uint32(dev, "kind-of-intr", 0);
236 qdev_init_nofail(dev);
237 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
238 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
239 for (i = 0; i < 32; i++) {
240 irq[i] = qdev_get_gpio_in(dev, i);
241 }
242
243 serial_mm_init(address_space_mem, UART16550_BASEADDR, 2, irq[UART16550_IRQ],
244 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
245
246
247 dev = qdev_create(NULL, "xlnx.xps-timer");
248 qdev_prop_set_uint32(dev, "one-timer-only", 0);
249 qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
250 qdev_init_nofail(dev);
251 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
252 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
253
254 if (kernel_filename) {
255 uint64_t entry, low, high;
256 hwaddr boot_offset;
257
258
259 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
260 &entry, &low, &high, 1, PPC_ELF_MACHINE,
261 0, 0);
262 boot_info.bootstrap_pc = entry & 0x00ffffff;
263
264 if (kernel_size < 0) {
265 boot_offset = 0x1200000;
266
267 kernel_size = load_image_targphys(kernel_filename,
268 boot_offset,
269 ram_size);
270 boot_info.bootstrap_pc = boot_offset;
271 high = boot_info.bootstrap_pc + kernel_size + 8192;
272 }
273
274 boot_info.ima_size = kernel_size;
275
276
277 if (machine->initrd_filename) {
278 initrd_base = high = ROUND_UP(high, 4);
279 initrd_size = load_image_targphys(machine->initrd_filename,
280 high, ram_size - high);
281
282 if (initrd_size < 0) {
283 error_report("couldn't load ram disk '%s'",
284 machine->initrd_filename);
285 exit(1);
286 }
287 high = ROUND_UP(high + initrd_size, 4);
288 }
289
290
291 boot_info.fdt = high + (8192 * 2);
292 boot_info.fdt &= ~8191;
293
294 xilinx_load_device_tree(boot_info.fdt, ram_size,
295 initrd_base, initrd_size,
296 kernel_cmdline);
297 }
298 env->load_info = &boot_info;
299}
300
301static void virtex_machine_init(MachineClass *mc)
302{
303 mc->desc = "Xilinx Virtex ML507 reference design";
304 mc->init = virtex_init;
305 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440-xilinx");
306}
307
308DEFINE_MACHINE("virtex-ml507", virtex_machine_init)
309
